The PARKAS team was established on April 1st 2011. It is located at École Normale Supérieure. The team is also a member of the Département d'Informatique of ENS.
Tobias Grosser has been awarded a Google European Doctoral Fellowship, a highly competitive 3 years scholarship of 120k €(14 recipients in 2011).
Our project is founded on our expertise in three complementary domains: (1) synchronous functional programming and its extensions to deal with features such as communication with bounded buffers and dynamic process creation; (2) mathematical models for synchronous circuits; (3) compilation techniques for synchronous languages and optimizing/parallelizing compilers.
A strong point of the team is its experience and investment in the development of languages and compilers. Members of the team also have direct collaborations for several years with major industrial companies in the field and several of our results are integrated in successful products. Our main results are briefly summarized below.
In
, Paul Caspi and Marc Pouzet introduced
synchronous Kahn networksas those Kahn networks that can be statically scheduled and executed with bounded buffers. This was the origin of the language
Lucid Synchrone,
In 2000, Marc Pouzet started to collaborate with the SCADE team of Esterel-Technologies on the design of a new version of SCADE.
Dassault-Systèmes (Grenoble R&D center, part of Delmia-automation) developed the language
LCM, a variant of
Lucid Synchronethat is used for the simulation of factories.
LCMfollows closely the principles and programming constructs of
Lucid Synchrone(higher-order, type inference, mix of data-flow and hierarchical automata). The team in Grenoble is integrating this development into
a new compiler for the language Modelica.
In parallel, the goal of
ReactiveML
The development of
ReactiveMLwas started by Louis Mandel during his PhD thesis
,
and is ongoing. The language extends
Ocaml
Several open problems have been solved by Louis Mandel: the interaction between ML features (higher-order) and reactive constructs with a proper type system; efficient simulation that avoids busy waiting. The latter problem is particularly difficult in synchronous languages because of possible reactions to the absence of a signal. In the ReactiveMLimplementation, there is no busy waiting: inactive processes have no impact on the overall performance. It turns out that this enables ReactiveMLto simulate millions of (logical) parallel processes and to compete with the best event-driven simulators .
ReactiveMLhas been used for simulating routing protocols in ad-hoc networks and large scale sensor networks . The designer benefits from a real programming language that gives precise control of the level of simulation (e.g., each network layer up to the MAC layer) and programs can be connected to models of the physical environment programmed with Lutin . ReactiveMLis used since 2006 by the synchronous team at VERIMAG, Grenoble (in collaboration with France-Telecom) for the development of low-consumption routing protocols in sensor networks.
In the data-flow synchronous model, the clock calculus is a static analysis that ensures execution in bounded memory. It checks that the values produced by a node are instantaneously consumed by connected nodes (synchronous constraint). To program Kahn process networks with bounded buffers (as in video applications), it is thus necessary to explicitly place nodes that implement buffers. The buffers sizes and the clocks at which data must be read or written have to be computed manually. In practice, it is done with simulation or successive tries and errors. This task is difficult and error prone. The aim of the n-synchronous model is to automatically compute at compile time these values while insuring the absence of deadlock.
Technically, it allows processes to be composed whenever they can be synchronized through a bounded buffer , . The new flexibility is obtained by relaxing the clock calculus by replacing the equality of clocks by a sub-typing rule. The result is a more expressive language which still offers the same guarantees as the original. The first version of the model was based on clocks represented as ultimately periodic binary words . It was algorithmically expensive and limited to periodic systems. In , an abstraction mechanism is proposed which permits direct reasoning on sets of clocks that are defined as a rational slope and two shifts. An implementation of the n-synchronous model, named Lucy-n, was developed in 2009 , as was a formalization of the theory in Coq . We also worked on low-level compiler and runtime support to parallelize the execution of relaxed synchronous systems, proposing a portable intermediate language and runtime library called Erbium .
This work started as a collaboration between Marc Pouzet (LIP6, Paris, then LRI and INRIA Proval, Orsay), Marc Duranton (Philips Research then NXP, Eindhoven), Albert Cohen (INRIA Alchemy, Orsay) and Christine Eisenbeis (INRIA Alchemy, Orsay) on the real-time programming of video stream applications in set-top boxes. It was significantly extended by Louis Mandel and Florence Plateau during her PhD thesis (supervised by Marc Pouzet and Louis Mandel). Low-level support has been investigated with Cupertino Miranda, Philippe Dumont (INRIA Alchemy, Orsay) and Antoniu Pop (Mines ParisTech).
Despite decades of progress, the best parallelizing and optimizing compilers still fail to extract parallelism and to perform the necessary optimizations to harness multi-core processors and their complex memory hierarchies. Polyhedral compilationaims at facilitating the construction of more effective optimization and parallelization algorithms. It captures the flow of data between individual instances of statements in a loop nest, allowing to accurately model the behavior of the program and represent complex parallelizing and optimizing transformations. Affine multidimensional scheduling is one of the main tools in polyhedral compilation . Albert Cohen, in collaboration with Cédric Bastoul, Sylvain Girbal, Nicolas Vasilache, Louis-Noël Pouchet and Konrad Trifunovic (LRI and INRIA Alchemy, Orsay) has contributed to a large number of research, development and transfer activities in this area.
The relation between polyhedral compilation and data-flow synchrony has been identified through data-flow array languages , , , and the study of the scheduling and mapping algorithms for these languages. We would like to deepen the exploration of this link, embedding polyhedral techniques into the compilation flow of data-flow, relaxed synchronous languages.
Our previous work led to the design of a theoretical and algorithmic framework rooted in the polyhedral model of compilation, and to the implementation of a set of tools based on
production compilers (Open64, GCC) and source-to-source prototypes (PoCC,
http://
After an initial experiment with Open64 , , we ported these techniques to the GCC compiler , , , applying them to multi-level parallelization and optimization problems, including vectorization and exploitation of thread-level parallelism. Independently, we made significant progress in the design of effective optimization heuristics, working on the interactions between the semantics of the compiler's intermediate representation and the structure of the optimization space , , , . These results open opportunities for complex optimizations that target larger problems, such as the scheduling and placement of process networks, or the offloading of computational kernels to hardware accelerators (such as GPUs).
For both cost and performance reasons, computing systems tightly couple parts realized in hardware with parts realized in software. The boundary between hardware and software keeps moving with the underlying technology and the external economic pressure. Moreover, thanks to FPGA technology, hardware itself has become programmable. There is now a pressing need from industry for hardware/software co-design, and for tools which automatically turn software code into hardware circuits, or more usually, into hybrid code that simultaneously targets GPUs, multiple cores, encryption ASICs, and other specialized chips.
Departing from customary C-to-VHDL compilation, we trust that sharper results can be achieved from source programs that specify bit-wise time/space behavior in a rigorous synchronous language, rather than just the I/O behavior in some (ill-specified) subset of C. This specification allows the designer to also program the (asynchronous) environment in which to operate the entire system, and to profile/measure/control each variable of the design.
At any time, the designer can edit a single specification of the system, from which both the software and the hardware are automatically compiled, and guaranteed to be compatible. Once correct (functionally and with respect to the behavioral specification), the application can be automatically deployed (and tested) on a hard/soft hybrid co-design support.
Key aspects of the advocated methodology were validated by Jean Vuillemin in the design of a PAL2HDTV video sampler , . The circuit was automatically compiled from a synchronous source specification, decorated and guided by a few key hints to the hardware back-end, that targetted an FPGA running at real-time video specifications: a tightly-packed highly-efficient design at 240MHz, generated 100% automatically from the application specification source code, and including all run-time/debug/test/validate ancillary software. It was subsequently commercialized on FPGA by LetItWave, and then on ASIC by Zoran. This successful experience underlines our research perspectives on parallel synchronous programming.
The goal of the PARKAS project is the design, semantics and compilation of languages for the implementation of provably safe and efficient computing systems. We are driven by the ideal of a unique source code used both to programand simulatea wide variety of systems, including (1) embedded real-time controllers (e.g., fly-by-wire, engine control); (2) computationally intensive applications (signal processing, numerical, non-numerical); (3) the simulation of (a possibly huge number of) embedded systems in close interaction (e.g., simulation of factories, electrical or sensor networks, train tracking). All these applications share the need for formally defined languages used both for simulation and the generation of target code. For that purpose, we design languages and experiment with compilers that transform mathematical specifications of systems into target code, that may execute on parallel (multi-core) architectures.
Our research team draws inspiration and focus from the simplicity and complementarity of the data-flow model of Kahn process networks , synchronous concurrency , and the expression of the two in functional languages , . To reach our goal, we plan to leverage a large body of formal principles: language design, semantics, type theory, concurrency models, synchronous circuits and algorithms (code generation, optimization, polyhedral compilation).
The activity of the project is in the field of formal methods and compilation techniques for the development of computing and communicating reactive applications.
The project addresses the design, semantics and implementation of programming languages together with compilation techniques to develop provably safe and efficient computing systems. Traditional applications can be found in safety critical embedded systems with hard real-time constraints such as avionics (e.g., fly-by-wire command), railways (e.g., on board control, engine control), nuclear plants (e.g., emergency control of the plant). While embedded applications have been centralized, they are now massively parallel and physically distributed (e.g., sensor networks, train tracking, distributed simulation of factories) and they integrate computationally intensive algorithms (e.g., video processing) with a mix of hard and soft real-time constraints. Finally, systems are heterogeneous with discrete devices communicating with physical ones (e.g., interface between analog and digital circuits). Programming and simulating a whole system from a unique source code, with static guarantees on the reproducibility of simulations together with a compiler to generate target embedded code is a scientific and industrial challenge of great importance.
The theoretical and practical interest of synchronous languages
is well established (Airbus A340 and A380 civil airplanes, EDF
nuclear plants, railway signaling, system-on-chip for consumer electronics, etc.). There are also a variety of modeling/programming tools for the development of embedded systems
(Simulink/StateFlow
The ability to program and simulate, from a single source codeboth the system (e.g., the discrete controller) and its environment. The environment can be made of possibly huge numbers of other processes that are added and removed dynamically, and that possibly evolve in continuous time. This raises the question of the semantics and efficient simulation of the whole, the interaction with numerical solvers, and the static isolation of parts of the code which execute in bounded time and memory.
The ability to generate efficient parallel code from a synchronous specification, targeting modern architectures including shared-memory multi-core processors, non-uniform or distributed memory many-core architectures, tiled processor arrays, and heterogeneous systems with hardware accelerators (like GPUs). This also raises the question of language annotations to describe architecture and behavioral (e.g., real-time) constraints while preserving modular composition. It requires language and compiler support for relaxed synchronous models with jittering or buffered communication.
Having these two objectives in mind, we adopt a language-centric approach, focusing our efforts on the development of languages together with dedicated type systems and compilation techniques. We insist on concrete implementations as they allow us to validate and experiment with our proposals. This experimental point of view can be related to the Ptolemy project of Edward Lee in Berkeley . Our technical approach is distinguished, however, by a focus on the synchronous model and a preference for typed functional programming.
There is also the observation that the synchronous model is expressive enough to account for other concurrency models (e.g., discrete-event and continuous , asynchronous communication ). Basing our study on the data-flow synchronous model will make it easier to design a sound, common semantics for all the language features. It will also simplify the remaining test and verification steps; this approach has proved to be crucial for the industrial success of the synchronous languages. Finding efficient ways to perform the early simulation of mixed discrete-continuous programs is also essential in the design flow of today's embedded systems. The creation of such simulation tools and associated tools for parallel code generation is a central and distinguishing feature of our proposal.
Lucid Synchrone is a language for the implementation of reactive systems. It is based on the synchronous model of time as provided by Lustre combined with features from ML languages. It provides powerful extensions such as type and clock inference, type-based causality and initialization analysis and allows to arbitrarily mix data-flow systems and hierarchical automata or flows and valued signals.
It is distributed under binary form, at URL
http://
The language was used, from 1996 to 2006 as a laboratory to experiment various extensions of the language Lustre. Several programming constructs (e.g. merge, last, mix of data-flow and control-structures like automata), type-based program analysis (e.g., typing, clock calculus) and compilation methods, originaly introduced in Lucid Synchrone are now integrated in the new SCADE 6 compiler developped at Esterel-Technologies and commercialized since 2008.
Three major release of the language has been done and the current version is V3 (dev. in 2006). The language is still used for teaching and in our research but we do not develop it anymore. Nonetheless, we have integrated several features from Lucid Synchrone in new research prototypes described below.
ReactiveML is a programming language dedicated to the implementation of interactive systems as found in graphical user interfaces, video games or simulation problems. ReactiveML is based on the synchronous reactive model due to Boussinot, embedded in an ML language (Objective Caml).
The Synchronous reactive model provides synchronous parallel composition and dynamic features like the dynamic creation of processes. In ReactiveML, the reactive model is integrated at the language level (not as a library) which leads to a safer and a more natural programming paradigm.
ReactiveML is distributed at URL
http://
The language was mainly used for the simulation of mobile ad hoc networks at the University Paris 6 and for the simulation of sensor networks at France Telecom and Verimag (CNRS, Grenoble).
Heptagon is an experimental language for the implementation of embedded real-time reactive systems. It is developed inside the Synchronics large-scale initiative, in collaboration with INRIA Rhones-Alpes. It is essentially a subset of Lucid Synchrone, without type inference, type polymorphism and higher-order. It is thus a Lustre-like language extended with hierchical automata in a form very close to SCADE 6. The intention for making this new language and compiler is to develop new aggressive optimization techniques for sequential C code and compilation methods for generating parallel code for different platforms. This explains much of the simplifications we have made in order to ease the development of compilation techniques.
Some extensions have already been made, most notably automata. It's currently used to experiment with linear typing for arrays and also to introduce a concept of asynchronous parallel computations. The compiler developed in our team generates C, java and VHDL code.
Heptagon is jointly developed by Gwenael Delaval and Alain Girault from the INRIA POP ART team (Grenoble).
http://
Lucy-n is a language to program in the n-synchronous model. The language is similar to Lustre with a buffer construct. The Lucy-n compiler ensures that programs can be executed in bounded memory and automatically computes buffer sizes. Hence this language allows to program Kahn networks, the compiler being able to statically compute bounds for all FIFOs in the program.
ML-Sundials library provides an Ocaml interface to the Sundials numerical suite
solver sessions are configured through algebraic data types rather than through multiple function calls,
error conditions are signalled by exceptions rather than return codes (including in user-supplied callback routines),
closures (partial applications of higher-order functions) are used to share user data between callback routines, and,
explicit free commands are not necessary nor provided since Ocaml is a garbage-collected language.
The library is in use in a new synchronous hybrid language we are currently developping.
Licence: GPLv3+ and LGPLv3+
The GNU Compiler Collection includes front ends for C, C++, Objective-C, Fortran, Java, Ada, and Go, as well as libraries for these languages (libstdc++, libgcj,...). GCC was originally written as the compiler for the GNU operating system. The GNU system was developed to be 100% free software, free in the sense that it respects the user's freedom.
PARKAS contributes to the polyhedral compilation framework, also known as Graphite. We also distribute an experimental branch for a stream-programming extension of OpenMP, parallel data-flow programming, and automatic parallelization to a data-flow runtime or architecture. This experiment borrows key design elements to synchronous data-flow languages.
Tobias Grosser is the maintainer of the Graphite optimization pass of GCC.
http://
Licence: LGPLv2.1+
isl is a library for manipulating sets and relations of integer points bounded by linear constraints. Supported operations on sets include intersection, union, set difference, emptiness check, convex hull, (integer) affine hull, integer projection, transitive closure (and over-approximation), computing the lexicographic minimum using parametric integer programming. It also includes an ILP solver based on generalized basis reduction. isl also supports affine transformations for polyhedral compilation.
The paper Modular Static Scheduling of Synchronous Data-flow Programsby M. Pouzet and P. Raymond (VERIMAG Grenoble) has been selected among the two best papers at EMSOFT 2009. An extended version is published in a special issue of the Journal of Design Automation for Embedded Systems, in 2010. This work solves a 20 years problem raised by P. Raymond in 88 .
Significant extensions have been provided to the Heptagon language. C. Pasteur contributed a memory optimization pass, combining a static analysis with user-given annotations (a paper on this subject is submitted to LCTES'2012), and the integration of discrete controller synthesis, developed and used by the SARDES team at INRIA Rhones-Alpes. Other work-in-progress extensions and experiments conducted inside the PARKAS team include the generation of VHDL code, parallel code generation, and n-synchronous code generation from Lucy-n.
Hybrid systems modelers have become the corner stone of embedded system development, with Simulink
In collaboration with Albert Benveniste and Benoit Caillaud (INRIA Rennes) we have proposed using non standard analysis as a semantic domain for hybrid systems. Non standard analysis is an extension of classical analysis in which infinitesimals can be manipulated as first class citizens. This allows us to provide a denotational semantics and a constructive semantics for hybrid systems, thus establishing simulation engines on a firm mathematical basis. In passing, we cleanly separate the job of the numerical analyst (solving differential equations) from that of the computer scientist (generating execution schemes).
In late 2010, we presented in 49th Conference on Design and Controlin 2010 the use of non standard semantics as a semantical ground for a hybrid synchronous language.
Since the, we have extended this work in the following directions: 1/ a synchronous Kahn semantics for hybrid programs. Programs are viewed as synchronous ones running on
an infinitely fast discrete base clock of the form
Starting from a minimal, yet full-featured, Lustre-like synchronous language, we have proposed a conservative extension where data-flow equations can be mixed with
ordinary differential equations (ODEs) with possible reset. A type system is proposed to statically distinguish discrete computations from continuous ones and to ensure that signals are
used in their proper domains. The extended data-flow language is realized through a source-to-source transformation into a synchronous subset, which can then be compiled using existing
tools into routines that are both efficient and bounded in their use of memory. These routines are orchestrated with a single off-the-shelf numerical solver using a simple but precise
algorithm which treats causally-related cascades of zero-crossings. We have validated the viability of the approach through experiments with the SUNDIALS
This work shows that it is possible to define a language which combines both the expressiveness of synchronous a synchronous language and that of ODEs where continuous solvers are approximated by a black-box solver. The most noticiable result was to recycleseveral techniques developed for synchronous languages: Kahn semantics, compilation techniques, static analysis. During year 2011, we extended the basic language with with hierarchical automata. This work has been presented at the ACM International Conference on Embedded Software, 2011 .
In parallel with these theoretical works, M. Pouzet and T. Bourke have developed during year 2011 a new synchronous language and its compiler. The language, called Zelus, extends a synchronous language with ODEs. It is first-order, functional and which mixes continuous-time and discrete-time signals. The expressiveness is that of (the first-order subset of) Lucid Synchrone (e.g., type inference and polymorphism, mix of data-flow and hierarchical automata) and ODEs with possible reset. Continuous trajectories are computed by a black-box numerical solver and we made our experiments with SUNDIALS.
The n-synchronous model introduced a way to compose streams which have almost the same clockand can be synchronized through the use of a finite buffer.
We have designed the language Lucy-n to program in this model of computation , . This language is similar to the first order synchronous data-flow language Lustre in which a buffer operator is added. A dedicated type system allows to check that programs can be executed in bounded memory and to compute the buffers sizes needed. Technically it is done through the introduction of a subtyping constraint at each bufferization point.
To solve the subtyping constraints we have defined an algorithm that uses an improved version of the state-of-the-art abstraction. We have proved the correctness properties of this new abstraction in Coq.
We also worked on new typing algorithms that do not use clock abstraction and thus allows to model Latency Insensitive Design in Lucy-n .
A. Guatto, together with L. Mandel and M. Pouzet, worked on the code generation for Lucy-n. They investigated two approaches. The first one was to use the schedules and buffer sizes computed by the compiler to generate a classical Lustre program. The second approach was to define a dynamic scheduling protocol similar to the ones used in latency insensitive designs.
L. Mandel, in collaboration with F. Plateau (Prove&Run), developed a new resolution constraint algorithm for the clocking of Lucy-n programs . Even if the new algorithm is less efficient that the one using abstraction, it has the advantage to be more precise and thus to accept more programs.
L. Mandel, F. Plateau and M. Pouzet have extended the Lucy-n language with a new operator to be able to model Latency Insensitive Designs. Thanks to the new resolution constraint algorithm, the Lucy-n compiler is able to compute static schedules for such designs .
Followed up on J. Vuillemin's result that the XOR variant of non-deterministic automata can be efficiently minimized , we explore this newly opened branch of computational automata theory. One contribution is a Decision Diagramfor Boolean functions which has minimal dimension: this is appealing for both the verification and synthesis of memory-less circuits. Parts of this recent work were presented at the Boole ANR cooperation and Synchron 2011.
An extension of Boolean Decison Diagrams to integer representation and operations is given in : we pursue software experimentations with arithmetics on such gigantic (yet sparse) numbers.
The paper was translated to English from the 1974 original and published in honor of Gilles Kahn.
ReactiveML is an extension of OCaml with synchronous concurrency, based on synchronous parallel composition and broadcast of signals. The goal is to provide a general model of deterministic concurrency inside a general purpose functional language to program reactive systems. It is particularly suited to program discrete simulations, for instance of sensor networks. The current focus of the research is being able to simulate huge systems, composed of millions of agents, by extending the current purely sequential implementation in order to be able to take advantage of multi-core and distributed architectures.
A first experiment consisted in creating a parallel runtime without any modification to the language. As the OCaml language on which ReactiveML is based (the ReactiveML compiler generates OCaml code) does not allow to create parallel programs communicating via shared memory, the new runtime was written in the F# language, part of Microsoft .Net environment. As the language is almost source to source compatible with OCaml, the ReactiveML compiler was left untouched. Several parallel runtimes were written, using traditional task scheduling techniques like work stealing or directly using light task mechanisms available in F#. This experiment demonstrated many speedup opportunities by parallelizing the runtime but also highlighted several problems and limitations of the language. Although this experiment was very useful in understanding the stakes of parallelizing ReactiveML, the performance gap between OCaml and F# (OCaml generates sequential code that is about 10 times slower) makes this version of the runtime of little practical use. We then proposed an extension of ReactiveML called clock domains. It consists in creating local notions of instants that are invisible from the outside. This extension should solve most of the problems raised by the previous experiment and help the parallelization of the language. The sequential runtime was adapted to this extension and a distributed version, using processes communicating via message passing, is currently being developed.
In collaboration with P. Attar (INRIA), F. Boussinot (INRIA) and J.-F. Susini (CNAM), L. Mandel worked on the design of DSL , a script language for the orchestration of concurrent programs. L .Mandel developed in ReactiveML and JoCaml an interpreter for the DSL language.
L.-N. Pouchet presented fundamental advances in the construction and linear optimization of multidimensional affine transformation spaces at the POPL 2011 conference, in collaboration with A. Cohen and colleagues from Paris Sud University, Louisiana State University and Ohio State University.
Our team is actively integrating the polyhedral optimization framework in two production compilers: the Graphiteframework in GCC and the Pollyframework in LLVM. We are also working towards using the polyhedral framework to target GPGPU and manycore architectures, and to generate aggressively optimized code starting from high level languages. New isl-based version of Graphite and Polly have been contributed, enabling state-of-the-art affine transformations in GCC and LLVM, respectively. Dramatic performance improvements are expected in 2012, impacting the upcoming GCC 4.8 and LLVM 3.1, respectively.
K. Trifunovic, F. Li and A. Cohen, in collaboration with R. Ladelsky from IBM Research Haifa, presented a paper about some of these progresses at the GROW 2011 workshop .
Among the challenges that arise when adapting the polyhedral framework to production compilers, Riyadh Baghdadi has been working on memory-based dependences. Part of it is a practical
compiler construction issue, where upstream passes such as the transformation to three-address code and PRE/CSE introduce new scalar variables leading to additional memory-based dependences.
The other difficulty is to identify a profitable tradeoff between memory expansion (privatization, renaming) and parallelism. Memory-based dependences not only increase the complexity of the
optimization but most importantly, they reduce the degree of freedom available to express effective loop nest transformations, limiting the overall effectiveness of the polyhedral framework. We
designed and implemented a technique that solves this problem by allowing a compiler to relax the constraint of memory-based dependences on loop nest transformations and that does not incur the
memory footprint overhead of scalar and array expansion. The proposed technique is based on the concept of polyhedral live range interval interference. While previous polyhedral optimization
techniques could not achieve any speedups in benchmarks with scalar variables. This technique enabled a speedup of up to
A. Pop defended his PhD thesis in September at MINES ParisTech, on a data-flow, streaming extension of OpenMP. Semantical, compilation and runtime system aspects have been covered in depth. Early results were published at HiPEAC 2011 and presented by A. Pop, in collaboration with A. Cohen. Follow-up work include the maturation of the proposed semantics and language extensions, with a thorough implementation and experimentation.
In parallel, F. Li, in collaboration with A. Pop and A. Cohen, explores the automatic compilation of SSA programs into dynamic data-flow parallelism, and the integration of streaming dependences to extend the method to non-scalar data flow. A paper has been published at WIR 2011 (workshop associated to CGO 2011), and a comprehensive, modular compilation method for arbitrary control flow, will be presented at MULTIPROG 2012 (associated with HiPEAC 2012).
Classical compilation techniques, found in Lustre, Scade, Lucid Synchrone, and all the dataflow synchronous languages, generate very efficient sequential code. Thus our main goal is to allow parallel code generation without changing the generation of the sequential code. To this matter, we introduced in the dataflow synchronous setting the famous asynchronous calls bundled with futures, which date back to MultiLisp designed by R. Halstead in the early 1980. It allows to separate the request of a computation from the actual use of its result. This approach has two main advantages. First, the compilation of these asynchronous calls is implemented by a simple wrapper encapsulating the called sequential code. It permits full compatibility with existing generated code. The futures are treated like usual values, so except for the asynchronous calls, we use the known sequential code generation. Second, this asynchronous calls and futures are only annotations and may be fully erased without changing the semantics of the program.
L. Gérard implements this proposition in our Heptagon compiler. The first backend was done in Java, as a proof of concept, using the threads and futures of the Java language. More efficient back-ends are being explored, using OpenMP stream-computing extensions and the TStar data-flow primitives.
Google European Doctoral Fellowship for Tobias Grosser, 120k €.
This project is funded by INRIA for 4 years and started in Jan. 2008. The coordinators are A. Girault (INRIA Rhône Alpes) and M. Pouzet.
http://
The goal of the project is to propose new languages for the development of embedded systems allowing from a unique sourceto both simulate the system with its environment and generate code. It capitalizes on recent extensions of data-flow synchronous languages (Lucid Synchrone, ReactiveML), a relaxed form of synchrony, and means to mix discrete and continous systems inside the synchronous model of time.
The project focuses on language extensions to increase modularity, dedicated type systems to ensure safety properties, efficient compilation and the mix of discrete and continuous time.
Partners: INRIA Rhône Alpes (Gwenaël Delaval, Alain Girault, Bertrand Jeannet), IRISA (Benoit Caillaud), VERIMAG (Erwan Jahier, Pascal Raymond), INRIA Rocquencourt (Albert Cohen, Marc Pouzet, Louis Mandel)
This project is funded by ANR (program DEFIS).
http://
It started on january 2009 for 4 years; the coordinator is Frédéric Boussinot from INRIA Indes.
Partners: INRIA Indes, CNAM, LRI.
The goal of the project PARTOUT is, from a programming language point of view, to study the impact on programming of the globalization of parallelism which now covers all the spectrum of informatics, ranging from multicore architectures and distributed systems, up to applications deployed on the Web.
Partners: INRIA CompSys, ALF, Arenaire.
Mediacom is one of the projects of the Nano2012 collaboration framework between STMicroelectronics and INRIA, 09/2009–12/2012. Mediacom is a collaboration between the compilation group of STMicroelectronics HED, led by Christian Bertin, and the INRIA CompSys, ARENAIRE, ALF and PARKAS (formerly ALCHEMY) groups. We are working on portable concurrent intermediate languages, inspired by data-flow synchronous languages and polyhedral compilation, and on just-in-time parallelization algorithms.
HiPEAC is a network of excellence on High-Performance Embedded Architectures and Compilers. It was first established as an FP6 network in 2004, and renewed as an FP7 4 years later. INRIA is one of the partners of the network. Albert Cohen leads the Compiler Platform cluster (9 research clusters in total). 02/2008–01/2012.
The TERAFLUX project is funded under the FP7 FET pro-active program on teradevice computing, 01/2010-12/2013. Albert Cohen is responsible for WP4. Our work addresses data-flow synchronous parallel programming, polyhedral compilation for data-flow programs, and compiler support for data-driven multi-threaded architectures with hundreds of computing cores. We contribute compilation algorithms and experimental language designs, with prototypes based on Lucid Synchroneand direct contributions to GCC through the design of data-flow synchronous extensions of OpenMP. One of our goals is to transfer results of the project to production tools, including GCC and simulation platforms for many-core processors. A standardization effort (supported by INRIA's D2T) aims for the adoption of the language extensions by the OpenMP Architecture Review Board.
The PHARAON project is funded on the embedded systems strategic objective, 09/2011–08/2014. Albert Cohen is responsible for WP5. Our work addresses data-flow synchronous programming for multiprocessor systems-on-chip, with an emphasis on an embedded development methodology and tools to optimize energy consumption and facilitate the correct-by-construction refinement of a functional specification. The Heptagon and Streaming OpenMP platforms of the team are used in the project. PHARAON is led by Thales Communications and Security.
The CARP project is funded on the computing systems strategic objective, 12/2011–11/2014. Our work addresses polyhedral automatic parallelization for vector accelerators, with an emphasis on extending the scope of polyhedral compilation and integrating vectorization and specialization techniques. isl is an important component of this work, along with a new source-to-source compilation framework being developed in the project. CARP is led by Imperial College, and our team collaborates closely with ARM Cambridge in the specification of a portable parallel intermediate language to facilitate automatic parallelization and vectorization.
This new action started in April 2011. It aims at consolidating European research on transactional memory, by coordinating the research groups working on the development of complementary, interdisciplinary aspects of Transactional Memories, including theoretical foundations, algorithms, hardware and operating system support, language integration and development tools, and applications. Our participation is focused on the interaction between data-flow and transactional memory models.
November 2011: Alex Nicolau, UCI. Variability, Accuracy, and Performance evaluation.
September 2011: Daisuke Ishii, JSPS, National Institute of Informatics (Tokyo) and ProVal team, INRIA Saclay. An Execution Algorithm for a Hybrid Modeling Language HydLa.
August 2011: Peter Gammie, the Australian National University and National ICT Australia. Verified Synthesis of Knowledge-Based Programs in Finite Synchronous Environments.
June 2011: Jan Vitek, Purdue University. Virtualizing Real-time Embedded Systems with Java.
May 2011: Walid Najjar, University of California Riverside. Performance, Productivity and Programmability: The Coming of Age of FPGA Code Accelerators.
March 2011: Eunjung Park, University of Delaware. Predictive Modeling in a Polyhedral Optimization Space.
John Cavazos, University of Delaware, visited us in January and July 2011. We have been collaborating on statistical methods in polyhedral compilation since John's postdoc at the University of Edinburgh. A joint paper was published at CGO 2011. Albert Cohen is on the PhD thesis committee of his student, Eunjung Park.
P. Sadayappan, Ohio State University, visited us in December 2011. We collaborate for a long time on polyhedral compilation methods and tools. A joint paper was published at POPL 2011. P. Sadayappan has been the Master thesis advisor of Tobias Grosser and he is participating to the direction of his PhD thesis, and he hosts a former student, Louis-Noël Pouchet for more than 1 year as a postdoc.
John Plaice, University of New South Wales, visited us in December 2011. He is a long-time synchronous programming and functional programming expert. His Translucid language experiment could be the basis for a collaboration on efficient compilation of array-based computations and synchronous language expressiveness.
Marc Pouzet supervised the 12-month post-doc of Timothy Bourke, from the University of New South Wales, from September 2010 to October 2011, and funded by the large scale initiative SYNCHRONICS of INRIA. Timothy worked on the semantics and implementation of hybrid modelers.
Albert Cohen co-advised the PhD thesis of Sean Halle, from the University of California Santa Cruz, defended in June 2011. Sean Halle worked on parallel programming models and analytical performance models.
Albert Cohen is the General Chair of the 7th HiPEAC conference, January 2012. Louis Mandel is member of the local arrangements committee.
The conference is pionneering a new “journal first” publication model, and has been completely reorganized into a large networking event with 27 parallel events, an industry exhibit with 50 companies booths and posters, and a European project exhibit with 46 projects from the computing systems, embedded systems strategic objectives of the FP7 and from the FET programme.
475 registered participants, 34 ACM TACO journal papers will be presented (the record number for previous HiPEAC conferences was 210 participants).
Albert Cohen co-organized the 9th Symposium on Code Generation and Optimization, as a finance chair, April 2011. CGO is co-sponsored by ACM and IEEE, in Chamonix
http://
Marc Pouzet organised the 18th annual edition of the international workshop SYNCHRON
http://
This year, we have invited collegues from IRCAM (Paris) and GRAME (Lyon) for a half day presentation of their work on programming languages for music.
The workshop has been a great success with 80 participant whereas the workshop usually have 50.
Jean Vuillemin is on the board of 5 international journals.
Marc Pouzet is associate editor of the EURASIP Journal on Embedded systems (
http://
Marc Pouzet is “directeur de collection” for Hermes publisher.
Albert Cohen is on the editorial board of the International Journal on Parallel Programming (IJPP,
http://
M. Pouzet is a member of the program committee of the following conferences: Design, Automation & Test in Europe (DATE 2011 and DATE 2012); Approches Formelles dans l'Assistance au Développement de Logiciels (AFADL 2011 and AFADL 2012); Conference on Real-Time and Network Systems (RTNS 2011); Modélisation des systèmes Réactifs (MSR 2011); ACM Conf. on the Principles and Applications of Declarative Programming (PADL 2012), located with POPL;
M. Pouzet is an expert reviewer for the Design Automation Conference (DAC) in 2011 and 2012.
A. Cohen is a co-chair of the DAC 2012 ESS1&2 TPC.
A. Cohen is a member of the program committee of the following conferences: PLDI 2011, LCTES 2011, PPOPP 2011, ICS 2012, CC 2013.
A. Cohen is a member of the program committee of the following workshops: IMPACT 2011, GROW 2011, WIR 2011, IMPACT 2012, INTERACT 2012, GPGPU 2012.
L. Mandel, member of the program committee of the Journées Francophones des Langages Applicatifs (JFLA 2012).
M. Pouzet was a reviewer of the following PhD theses: Tayeb Bouhadiba (Université de Grenoble; dir: Florence Maraninchi; September 16th, 2010); Daniel Reynaud (INPL, Nancy; dir: Jean-Yves Marion; October 15th, 2010); Antony Coadou (Université de Nice; dir: Robert de Simone; December 3th, 2010).
M. Pouzet was president of the PhD jury of Nicolas Vallée (July 12, 2011), Univ. Paris-Diderot; Nicolas Pouillon (Sept. 26, 2011), Université Pierre et Marie Curie.
A. Cohen was a reviewer of the following PhD theses: Per Larsen (August 2011, DTU, Copenhagen); Paul Carpenter, (September 2011, UPC Barcelona); Serge Guelton (September 2011, UBO and Telecom Bretagne); Benoît Pradelle (December 2011, Université Louis Pasteur, Strasbourg); Nicolas Benoît (January 2012, Université de Versailles St-Quentin).
A. Cohen was a committee member of the following PhD theses: Matthias Eriksson (May 2011, Linköping U.); Antoniu Pop (September 2011, MINES ParisTech); Asma Charfi (December 2011, Université Paris Sud);
A. Cohen was on the Prelim committee of Eunjung Park (December 2011, University of Delaware).
L. Mandel and M. Pouzet, were invited to give a lecture at IRCAM in the Master of “Acoustique, Traitement du signal, Informatique, Appliqués à la Musique”. Nov. 2010 and Nov. 2011.
M. Pouzet was invited speaker at Complex Systems Design & Management (CSDM), Paris, in Dec. 2011. The title of the talk was: Programming hybrid systems with synchronous languages.
M. Pouzet was invited speaker by Hilding Elmquist, CTO at Dassault-Systèmes and the founder of the Modelica Language, at the 69th Modelica Design Meeting, Munich, Germany, in Jan. 2011. M. Pouzet gave two one-hour talks. The titles were Lucid Synchrone, a Functional Synchronous Languageand Design, Semantics and Compilation for a Hybrid Synchronous Language.
A. Cohen was a keynote speaker at the CTHPC 2011 workshop in Tai Chung, Taiwan, titled “Polyhedral Compilation Runs Out of (Static) Control!”, July 2011.
A. Cohen gave an invited presentation at the National Tsing Hua University, Hsin Chu, Taiwan, titled “Work-Streaming: a Combined Language, Compiler and Runtime Approach to Deterministic, Scalable and Efficient Parallel Computing”, July 2011.
Since 2007, Marc Pouzet is a junior member of the IUF ( “Institut Universitaire de France”), that distinguishes each year a few French university professors for the high quality of their research activities.
M. Pouzet is an elected member of the INRIA Evaluation Committee.
A. Cohen is an elected member of the INRIA Scientific Council.
A. Cohen is a member of the BCP of INRIA Rocquencourt.
A. Cohen is the scientific representative for the International Relations of INRIA for INRIA Rocquencourt, and a member of the COST GTRI committee.
J. Vuillemin was head of Computer Science at ENS from 2007 to 2011.
J. Vuillemin is a 2011 member of the International Scientific Advisory Board, National ICT Australia.
J. Vuillemin chairs the 2011 Scientific Advisory Board of I2R in Singapore.
J. Vuillemin received the “Grand prix 2008 des sciences de l'Informatique et de leurs applications”, from the French Academy of Sciences and foundation EADS.
J. Vuillemin was "Directeur Scientifique" at INRIA from 2005 to 2007.
L. Mandel is in charge of the International Selection of ENS with J. Bertrane (ENS) for the computer science department.
M. Pouzet was president of the hiring committee for a Chaire position funded by CNRS and École Polytechnique, in the computer science department of École Polytechnique, in january 2011.
M. Pouzet was a member of the hiring committee for an Assistant Professor position at École Nationale Supérieure des Techniques Avancées (ENSTA), in May 2011; a Full Professor position in Université de Nice, in May 2011.
A. Cohen was a member of two hiring committees for Associate Professor positions at UPMC in May and September 2011.
A. Cohen jointly created and operates the Electrical Engineering multidisciplinary program at at École Polytechnique (Master 1 level), with Yvan Bonnassieu (physics department) and Frédéric Bonnans (applied mathematics department).
M. Pouzet is scientific advisor for the compagny Esterel-Technology on the evolution of SCADE (start in nov. 2011).
A. Cohen initiated and manages a 20 man-year R&D project in production-ready polyhedral compilation within GCC (Graphite project, since GCC 4.5), in collaboration with AMD, IBM Research, and several GCC developers.
Licence: “Projet de programmation” (L3), L. Mandel (23h), Université Paris-Sud 11, France
Licence: “Systèmes et réseaux” (L3), M. Pouzet (24h), L. Mandel (24h), École Normale Supérieure, France
Licence: “Langages de programmation et compilation” (L3), L. Mandel (24h), École Normale Supérieure, France
Licence: “Components of a Computing System Introduction to Computer Architecture and Operating Systems” (L3), A. Cohen (44h), École Polytechnique, France
Master 1 École Polytechnique: “Operating Systems Principles and Programming” (M1), A. Cohen (38h), École Polytechnique, France
Master Parisien de Recherche en Informatique (MPRI): “Synchronous systems” (M2), M. Pouzet (12h), J. Vuillemin (12h), L. Mandel (6h), A. Cohen (6h), École Normale Supérieure and Université Paris Diderot, France
Master sur les Systèmes Industriels Complexes (COMASIC): Univ. Paris-Sud, École Polytechnique, INSTN. Synchronous Languages (24h), M. Pouzet.