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Bibliography

Publications of the year

Articles in International Peer-Reviewed Journals

  • 1F. Brandner, Q. Colombet.
    Elimination of parallel copies using code motion on data dependence graphs, in: Computer Languages, Systems and Structures, 2013, vol. 39, no 1, pp. 25 - 47. [ DOI : 10.1016/j.cl.2012.09.001 ]
    http://hal.inria.fr/hal-00768781
  • 2N. Fauzia, V. Elango, M. Ravishankar, J. Ramanujam, F. Rastello, A. Rountev, L.-N. Pouchet, P. Sadayappan.
    Beyond Reuse Distance Analysis: Dynamic Analysis for Characterization of Data Locality Potential, in: Transaction on Architecture and Code Optimization, December 2013, vol. 10, no 4.
    http://hal.inria.fr/hal-00920031
  • 3L. Gonnord, P. Schrammel.
    Abstract Acceleration in Linear Relation Analysis, in: Science of Computer Programming, 2013. [ DOI : 10.1016/j.scico.2013.09.016 ]
    http://hal.inria.fr/hal-00876627, http://hal.inria.fr/hal-00787212/en

International Conferences with Proceedings

  • 4C. Alias, A. Darte, A. Plesco.
    Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA, in: Design, Automation, and Test in Europe (DATE'13), Grenoble, France, 2013.
    http://hal.inria.fr/hal-00761533
  • 5A. Darte, A. Isoard.
    Parametric Tiling with Inter-Tile Data Reuse, in: 4th International Workshop on Polyhedral Compilation Techniques (IMPACT'14), Vienna, Austria, S. Rajopadhye, S. Verdoolaege (editors), 2014, To be published.
    http://hal.inria.fr/hal-00915831
  • 6B. Diouf, A. Cohen, F. Rastello.
    A Polynomial Spilling Heuristic: Layered Allocation, in: CGO 2013 - International Symposium on Code Generation and Optimization, Shenzhen, China, IEEE, 2013. [ DOI : 10.1109/CGO.2013.6495005 ]
    http://hal.inria.fr/hal-00911887
  • 7P. Feautrier, E. Violard, A. Ketterlin.
    Improving X10 Program Performances by Clock Removal, in: Compiler Construction 2014, Grenoble, France, January 2014.
    http://hal.inria.fr/hal-00924206
  • 8G. Iooss, S. Rajopadhye, C. Alias, Y. Zou.
    CART: Constant Aspect Ratio Tiling, in: IMPACT 2014, Vienna, Austria, January 2014, Not yet published.
    http://hal.inria.fr/hal-00915827
  • 9A. Tavares, F. Rastello, B. Boissinot, F. Pereira.
    Parameterized Construction of Program Representations for Sparse Dataflow Analyses, in: CC 2014 - 23rd International Conference on Compiler Construction, Grenoble, France, A. Cohen (editor), Springer, 2014.
    http://hal.inria.fr/hal-00921461
  • 10T. Yuki, P. Feautrier, S. Rajopadhye, V. Saraswat.
    Array Dataflow Analysis for Polyhedral X10 Programs, in: 18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'13), Shenzhen, China, ACM, 2013.
    http://hal.inria.fr/hal-00761537

Conferences without Proceedings

  • 11C. Alias, A. Darte, P. Feautrier, L. Gonnord.
    Rank: a tool to check program termination and computational complexity, in: Constraints in Software Testing Verification and Analysis, Luxembourg, March 2013.
    http://hal.inria.fr/hal-00801571

Internal Reports

  • 12P. Feautrier, A. Gamatié, L. Gonnord.
    Enhancing the Compilation of Synchronous Dataflow Programs with a Combined Numerical-Boolean Abstraction, July 2013.
    http://hal.inria.fr/hal-00780521

Other Publications

References in notes
  • 14C. Alias, A. Darte, P. Feautrier, L. Gonnord.
    Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs, in: 17th International Static Analysis Symposium (SAS'10), Perpignan, France, ACM press, September 2010, pp. 117-133.
  • 15G. Andrieu, C. Alias, L. Gonnord.
    SToP: Scalable Termination Analysis of (C) Programs (Tool Presentation), in: International Workshop on Tools for Automatic Program Analysis (TAPAS'12), Deauville, France, September 2012.
    http://hal.inria.fr/hal-00760926
  • 16P. Boulet, P. Feautrier.
    Scanning Polyhedra without DO loops, in: International Conference on Parallel Architecture and Compilation Techniques (PACT'98), Paris, France, IEEE Computer Society, October 1998, pp. 4-11.
  • 17A. Darte, R. Schreiber, G. Villard.
    Lattice-Based Memory Allocation, in: IEEE Transactions on Computers, October 2005, vol. 54, no 10, pp. 1242-1257, Special Issue: Tribute to B. Ramakrishna (Bob) Rau.
  • 18F. De Dinechin, C. Klein, B. Pasca.
    Generating High-Performance Custom Floating-Point Pipelines, in: Field Programmable Logic and Applications, IEEE, August 2009.
    http://prunel.ccsd.cnrs.fr/ensl-00379154/
  • 19B. Dupont de Dinechin, C. Monat, F. Rastello.
    Parallel Execution of Saturated Reductions, in: Workshop on Signal Processing Systems (SIPS'01), IEEE Computer Society Press, 2001, pp. 373-384.
  • 20P. Feautrier.
    Scalable and Structured Scheduling, in: International Journal of Parallel Programming, October 2006, vol. 34, no 5, pp. 459–487.
  • 21P. Feautrier.
    Bernstein's Conditions, in: Encyclopedia of Parallel Programming, D. Padua (editor), Springer, 2011.
  • 22P. Feautrier.
    Simplification of Boolean Affine Formulas, Inria, July 2011, no RR-7689.
    http://hal.inria.fr/inria-00609519/PDF/RR-7689.pdf
  • 23P. Feautrier.
    Dataflow Analysis of Scalar and Array References, in: International Journal of Parallel Programming, February 1991, vol. 20, no 1, pp. 23–53.
  • 24P. Feautrier, A. Gamatié, L. Gonnord.
    Enhancing the Compilation of Synchronous Dataflow Programs with a Combined Numerical-Boolean Abstraction, in: CSI Journal of Computing, 2012, vol. 1, no 4, 8:86 p.
  • 25A. Fraboulet, K. Godary, A. Mignotte.
    Loop Fusion for Memory Space Optimization, in: International Symposium on System Synthesis (ISSS'01), Montréal, Canada, IEEE Press, October 2001, pp. 95–100.
  • 26A. Gamatié, L. Gonnord.
    Static Analysis of Synchronous Programs in Signal for Efficient Design of Multi-Clocked Embedded Systems, in: International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'11), Chicago, USA, April 2011.
  • 27J.-W. Hong, H. T. Kung.
    I/O Complexity: The Red-Blue Pebble Game, in: 13th Annual ACM Symposium on Theory of Computing (STOC'81), ACM, 1981, pp. 326–333.
  • 28R. Johnson, M. Schlansker.
    Analysis Techniques for Predicated Code, in: 29th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO-29), Paris, France, IEEE Computer Society, 1996, pp. 100–113.
  • 29J. Le Guen, C. Guillon, F. Rastello.
    MinIR, a Minimalistic Intermediate Representation, in: Workshop on Intermediate Representations (WIR'11), held with CGO'11, Chamonix, F. Bouchez, S. Hack, E. Visser (editors), April 2011, pp. 5-12.
  • 30A. Stoutchinin, F. De Ferrière.
    Efficient Static Single Assignment Form for Predication, in: 34th Annual ACM/IEEE International Symposium on Microarchitecture (MICRO-34), Austin, Texas, IEEE Computer Society, 2001, pp. 172–181.
  • 31A. Turjan, B. Kienhuis, E. Deprettere.
    Translating Affine Nested-Loop Programs to Process Networks, in: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'04), New York, NY, USA, ACM, 2004, pp. 220–229.
  • 32S. Verdoolaege, H. Nikolov, N. Todor, P. Stefanov.
    Improved Derivation of Process Networks, in: International Workshop on Optimization for DSP and Embedded Systems (ODES'06), 2006.

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