Bibliography

Major publications by the team in recent years

• 1A. C. Aljundi, J.-L. Dekeyser, M. T. Kechadi, I. D. Scherson.
  A universal performance factor for multi-criteria evaluation of multistage interconnection networks, in: Future Generation Comp. Syst., 2006, vol. 22, n^o 7, pp. 794-804.
• 2A. Cuccuru, J.-L. Dekeyser, P. Marquet, P. Boulet.
  Towards UML 2 extensions for compact modeling of regular complex topologies, in: MODELS/UML 2005, ACM/IEEE 8th international conference on model driven engineering languages and systems, Montego Bay, Jamaica, October 2005.
• 3A. W. De Oliveira Rodrigues, F. Guyomarc'h, J.-L. Dekeyser, Y. Le Menach.
  Automatic Multi-GPU Code Generation applied to Simulation of Electrical Machines, in: Compumag 2011, Sydney, Australia, July 2011.
  http://hal.inria.fr/inria-00605645/en
• 4A. Gamatié, É. Rutten, H. Yu, P. Boulet, J.-L. Dekeyser.
  Synchronous Modeling and Analysis of Data Intensive Applications, in: EURASIP Journal on Embedded Systems,eurasip, july 2008, vol. 2008, Article ID 561863.
• 5A. Gamatié.
  Design of Streaming Applications on MPSoCs using Abstract Clocks, in: Design, Automation and Test in Europe Conference (DATE'2012), Dresden, Allemagne, 2012.
  http://hal.inria.fr/hal-00647480/en/
• 6A. Gamatié, S. Le Beux, É. Piel, R. Ben Atitallah, A. Etien, P. Marquet, J.-L. Dekeyser.
  A Model Driven Design Framework for Massively Parallel Embedded Systems, in: ACM Transactions on Embedded Computing Systems (TECS), 2011, vol. 10, n^o 4.
  http://hal.inria.fr/inria-00637595/en
• 7C. Glitia, P. Boulet, E. Lenormand, M. Barreteau.
  Repetitive model refactoring strategy for the design space exploration of intensive signal processing applications, in: Journal of Systems Architecture, January 2011, vol. 57, n^o 9, pp. 815-829. [ DOI : 10.1016/j.sysarc.2010.12.002 ]
  http://hal.inria.fr/inria-00605069/en
• 8S. Le Beux, P. Marquet, J.-L. Dekeyser.
  A Model Driven Co-Design Approach for High Perforamnce Embedded Systems Dedicated to Transport, in: Studies in Informatics and Control Journal, 2008, vol. 2008, n^o 4.
• 9P. Marquet, S. Duquennoy, S. Le Beux, S. Meftali, J.-L. Dekeyser.
  Massively Parallel Processing on a Chip, in: ACM Int'l Conf. on Computing Frontiers, Ischia, Italy, May 2007.
• 10Santhosh Kumar. Rethinagiri, R. Ben Atitallah, S. Niar, E. Senn, J.-L. Dekeyser.
  Hybrid System Level Power Consumption Estimation for 29FPGA-Based MPSoC, in: 29th IEEE International Conference on Computer Design ICCD 2011, October 2011.
• 11V. Rusu.
  Embedding Domain-Specific Modelling Languages in Maude Specifications, in: ACM SIGSOFT Software Engineering Notes, January 2011, vol. 36, n^o 1, Extended version accepted in the Systems and Software Engineering Journal.. [ DOI : 10.1145/1921532.1921557 ]
  http://hal.inria.fr/inria-00527859/en/
• 12C. Trabelsi, S. Meftali, R. Ben Atitallah, A. Jemai, J.-L. Dekeyser, S. Niar.
  An MDE Approach for Energy Consumption Estimation in MPSoC Design, in: 2nd Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Italie Pisa, Jan 2010, 6 p. p.
  http://hal.inria.fr/inria-00486200/en

Publications of the year

Articles in International Peer-Reviewed Journals

• 13A. W. De Oliveira Rodrigues, F. Guyomarc'h, J.-L. Dekeyser, Y. Le Menach.
  Automatic Multi-GPU Code Generation Applied to Simulation of Electrical Machines, in: Magnetics, IEEE Transactions on, February 2012, vol. 48, n^o 2, pp. 831 - 834. [ DOI : 10.1109/TMAG.2011.2179527 ]
  http://hal.inria.fr/hal-00670150
• 14P. Devienne, A. Ammar.
  Extended Model Driven Architecture to B Method, in: Ubiquitous Computing and Communication Journal, 2012.
  http://hal.inria.fr/hal-00641131
• 15C. Glitia, J. Deantoni, F. Mallet, J.-V. Millo, P. Boulet, A. Gamatié.
  Progressive and explicit refinement of scheduling for multidimensional data-flow applications using uml marte, in: Design Automation for Embedded Systems, 2012, vol. 16, n^o 2, pp. 137-169. [ DOI : 10.1007/s10617-012-9093-y ]
  http://hal.inria.fr/hal-00727239
• 16G. Ochoa-Ruiz, O. Labbani, E.-B. Bourennane, P. Soulard, S. Cherif.
  A High-level Methodology for Automatically Generating Dynamic Partially Reconfigurable Systems using IP-XACT and the UML MARTE Profile., in: Design Automation for Embedded Systems, December 2012.
  http://hal.inria.fr/hal-00745377
• 17I. R. Quadri, A. Gamatié, P. Boulet, S. Meftali, J.-L. Dekeyser.
  Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: advantages, limitations and alternatives, in: Journal of Systems Architecture, 2012. [ DOI : 10.1016/j.sysarc.2012.01.001 ]
  http://hal.inria.fr/hal-00666014
• 18V. Rusu.
  Embedding domain-specific modeling languages into Maude specifications, in: Software and Systems Modeling, 2012, To appear. [ DOI : 10.1007/s10270-012-0232-5 ]
  http://hal.inria.fr/hal-00660104

International Conferences with Proceedings

• 19A. Gamatié.
  Design of Streaming Applications on MPSoCs using Abstract Clocks, in: Design, Automation and Test in Europe Conference (DATE'2012), Dresden, Allemagne, 2012.
  http://hal.inria.fr/hal-00647480/en/
• 20S. Kumar Rethinagiri, R. Ben Atitallah, J.-L. Dekeyser.
  Virtual Platform for Embedded System Power Estimation, in: DATE-2012, Dresden, Germany, Rainer Leupers, March 2012.
  http://hal.inria.fr/hal-00673911
• 21S. Kumar Rethinagiri, R. Ben Atitallah, J.-L. Dekeyser.
  Virtual Platform for Embedded System Power Estimation, in: QVVP'12 (conjunction with DATE), Dresden, Germany, Rainer Leupers, March 2012.
  http://hal.inria.fr/hal-00673917
• 22S. K. Rethinagiri, R. Ben Atitallah, J.-L. Dekeyser, S. Niar, E. Senn.
  An Efficient Power Estimation Methodology for Complex RISC Processor-based Platforms, in: GLSVLSI 2012, Salt lake city, UTAH, United States, J. Cavallaro (editor), ACM, May 2012.
  http://hal.inria.fr/hal-00675469
• 23W. Rodrigues, L. Chevalier, Y. Le Menach, F. Guyomarch.
  Test Harness on a Preconditioned Conjugate Gradient Solver on GPUs: An Efficiency Analysis, in: CEFC - 2012, Oita, Japon, November 2012.
  http://hal.inria.fr/hal-00759476
• 24V. Rusu, D. Lucanu.
  A K-Based Formal Framework for Domain-Specific Modelling Languages, in: Formal Verification of Object-Oriented Systems, Torino, Italy, Lecture Notes in Computer Science, Springer Verlag, 2012, vol. 7421, pp. 214-231. [ DOI : 10.1007/978-3-642-31762-0 ]
  http://hal.inria.fr/inria-00637099
• 25A. Tinzefte, Y. Le Menach, F. Guyomarch.
  A New Preconditionner Based on F.I.T Applied To Solve F.E.M Problem, in: CEFC - 2012, Iota, Japon, November 2012.
  http://hal.inria.fr/hal-00759484
• 26P. Wattebled, J.-P. Diguet, J.-L. Dekeyser.
  Membrane-based design and management methodology for parallel dynamically reconfigurable embedded systems, in: RecoSoc 2012, YORK, United Kingdom, July 2012.
  http://hal.inria.fr/hal-00745150

Scientific Books (or Scientific Book chapters)

• 27J.-L. Dekeyser, A. Gamatié, S. Meftali, I. R. Quadri.
  Models for Co-Design of Heterogeneous Dynamically Reconfigurable SoCs, in: Heterogeneous Embedded Systems - Design Theory and Practice, G. Nicolescu, I. O'Connor, C. Piguet (editors), Springer, 2012, 26 p. p.
  http://hal.inria.fr/inria-00525023

Internal Reports

• 28A. Arusoaie, D. Lucanu, V. Rusu.
  A Generic Approach to Symbolic Execution, Inria, December 2012, n^o RR-8189, 21 p.
  http://hal.inria.fr/hal-00766220
• 29D. Lucanu, V. Rusu.
  Program Equivalence by Circular Reasoning, Inria, October 2012, n^o RR-8116, 26 p.
  http://hal.inria.fr/hal-00744374

Other Publications

• 30G. Afonso, R. Ben Atitallah, J.-L. Dekeyser.
  Software Implementation vs. Hardware Implementation: The Avionic Test System Case-Study, March 2012.
  http://hal.inria.fr/hal-00665162
• 31H. Krichene, M. Baklouti, M. Abid, P. Marquet, J.-L. Dekeyser.
  Broadcast with mask on a Massively Parallel Processing on a Chip, 2012, DRNoC.
  http://hal.inria.fr/hal-00688309
• 32H. Krichene, M. Baklouti, M. Abid, P. Marquet, J.-L. Dekeyser.
  Broadcast with mask on a Massively Parallel Processing on a Chip, 2012, workshop drnoc2012.
  http://hal.inria.fr/hal-00688418
• 33C. Trabelsi, S. Meftali, J.-L. Dekeyser.
  Distributed control for reconfigurable FPGA systems: a high-level design approach, June 2012, Workshop Recosoc 2012.
  http://hal.inria.fr/hal-00709755
• 34C. Trabelsi, S. Meftali, J.-L. Dekeyser.
  Semi-distributed control for FPGA-based reconfigurable systems, September 2012, Conférence DSD Turquie.
  http://hal.inria.fr/hal-00703093

References in notes

• 35The Eclipse Project, 2003.
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• 36EMF Eclipse Modeling Framework, 2007.
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• 37Acceleo, 2009.
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• 38Object Management Group, Inc. (editor)
  U2 Partners' (UML 2.0): Superstructure, 2nd revised submission, January 2003.
  http://www.omg.org/cgi-bin/doc?ptc/03-01-02
• 39Object Management Group, Inc. (editor)
  (UML 2.0): Superstructure Draft Adopted Specification, July 2003.
  http://www.omg.org/cgi-bin/doc?ptc/03-07-06
• 40SystemC, 2002.
  http://www.systemc.org/
• 41OpenMP Application Programme Interface, May 2005.
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• 42A. Agrawal.
  Graph Rewriting And Transformation (GReAT): A Solution For The Model Integrated Computing Bottleneck, in: 18th IEEE International Conference on Automated Software Engineering (ASE'03), 2003, pp. 364-368.
• 43V. Aranega, A. Etien, J.-L. Dekeyser.
  Using an Alternative Trace for QVT, in: Workshop on Multi-Paradigm Modeling, Norvège Olso, Oct 2010.
  http://hal.inria.fr/inria-00524153/en
• 44V. Aranega, J.-M. Mottu, A. Etien, J.-L. Dekeyser.
  Traceability Mechanism for Error Localization in Model Transformation, in: ICSOFT, Bulgaria, July 2009.
• 45V. Aranega, J.-M. Mottu, A. Etien, J.-L. Dekeyser.
  Using Traceability to Enhance Mutation Analysis Dedicated to Model Transformation, in: Workshop on Model driven Engineering Verification and Validation, Norvège Olso, Oct 2010.
  http://hal.inria.fr/inria-00524150/en
• 46A. Benveniste, P. Caspi, S. Edwards, N. Halbwachs, P. Le Guernic, R. de Simone.
  The Synchronous Languages Twelve Years Later, in: Proceedings of the IEEE, January 2003, vol. 91, n^o 1, pp. 64-83.
• 47P. Boulet.
  Array-OL Revisited, Multidimensional Intensive Signal Processing Specification, Inria, February 2007, n^o RR-6113, 24 p.
  http://hal.inria.fr/inria-00128840/en
• 48P. Boulet, J.-L. Dekeyser, J.-L. Levaire, P. Marquet, J. Soula, A. Demeure.
  Visual Data-parallel Programming for Signal Processing Applications, in: 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001, Mantova, Italy, February 2001, pp. 105–112.
• 49T. Buchmann, A. Dotor, S. Uhrig, B. Westfechtel.
  Model-Driven Software Development with Graph Transformations: A Comparative Case Study, in: Applications of Graph Transformations with Industrial Relevance, Third International Symposium (AGTIVE'07), 2007, pp. 345-360.
• 50P. Caspi, D. Pilaud, N. Halbwachs, J.A. Plaice.
  Lustre: a declarative language for real-time programming, in: Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages (POPL'87), ACM Press, 1987, pp. 178-188.
• 51G. Csertán, G. Huszerl, I. Majzik, Z. Pap, A. Pataricza, D. Varró.
  VIATRA - Visual Automated Transformations for Formal Verification and Validation of UML Models, in: 17th IEEE International Conference on Automated Software Engineering (ASE'02), 2002, pp. 267-270.
• 52A. Demeure, A. Lafage, E. Boutillon, D. Rozzonelli, J.-C. Dufourd, J.-L. Marro.
  Array-OL : Proposition d'un Formalisme Tableau pour le Traitement de Signal Multi-Dimensionnel, in: Gretsi, Juan-Les-Pins, France, September 1995.
• 53A. Demeure, Y. Del Gallo.
  An Array Approach for Signal Processing Design, in: Sophia-Antipolis conference on Micro-Electronics (SAME 98), France, October 1998.
• 54M. Egea, V. Rusu.
  Formal executable semantics for conformance in the MDE framework, in: Innivations in Software and Systems Engineering, 2010.
  http://hal.inria.fr/inria-00527502/en
• 55M. Elhaji, P. Boulet, S. Meftali, A. Zitouni, J.-L. Dekeyser, R. Tourki.
  An MDE approach for modeling network on chip topologies, in: Design and Technology of Integrated Systems in Nanoscale Era (DTIS), 2010 5th International Conference on, Tunisie Hammamet, 2010.
  http://hal.inria.fr/inria-00526629/en
• 56A. Etien, A. Muller, T. Legrand, X. Blanc.
  Combining Independent Model Transformations, in: ACM Symposium On Applied Computing (SAC), Suisse Sierre, Mar 2010.
  http://hal.inria.fr/inria-00516708/en
• 57D. D. Gajski, R. Kuhn.
  Guest Editor Introduction: New VLSI-Tools, in: IEEE Computer, December 1983, vol. 16, n^o 12, pp. 11-14.
• 58I. Galvão, A. Goknil.
  Survey of Traceability Approaches in Model-Driven Engineering, in: IEEE International Enterprise Distributed Object Computing Conference (EDOC 2007), October 2007, pp. 313-326.
• 59F. Jouault.
  Loosely Coupled Traceability for ATL, in: European Conference on Model Driven Architecture (ECMDA) workshop on traceability, 2005, pp. 29–37.
• 60S. Le Beux, P. Marquet, J.-L. Dekeyser.
  Model Driven Engineering Benefits for High Level Synthesis, Inria, 2008, n^o 6615.
  http://hal.inria.fr/inria-00311300/en/
• 61P. Le Guernic, J.-P. Talpin, J.-C. Le Lann.
  Polychrony for System Design, in: Journal for Circuits, Systems and Computers, April 2003, vol. 12, n^o 3, pp. 261–304.
• 62J.-M. Mottu, B. Baudry, Y. Le Traon.
  Mutation Analysis Testing for Model Transformations, in: proceedings of the European Conference on Model Driven Architecture (ECMDA 06), Bilbao, Spain, July 2006.
• 63Object Management Group, Inc..
  Meta Object Facility (MOF) Core Specification, Version 2.0, January 2006.
  http://www.omg.org
• 64Object Management Group, Inc..
  MOF Query / Views / Transformations, July 2007, OMG paper.
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• 65J. Rivera, E. Guerra, J. De Lara, A. Vallecillo..
  Analyzing Rule-Based Behavioral Semantics of Visual Modeling Languages with Maude, in: Proc. 1st International Conference on Software Language Engineering (SLE'08), LNCS, 2008, vol. 5452, pp. 54-73.
• 66V. Rusu, L. Gonnord, B. Combemale.
  Formally Tracing Executions From an Analysis Tool Back to a Domain Specific Modeling Language's Operational Semantics, Inria, Oct 2010, n^o RR-7423.
  http://hal.inria.fr/inria-00526561/en
• 67V. Rusu.
  Embedding Domain-Specific Modelling Languages in Maude Specifications, in: ACM SIGSOFT Software Engineering Notes, 2010.
  http://hal.inria.fr/inria-00527859/en
• 68D. Schmidt.
  Model-Driven Engineering, in: IEEE Computer, February 2006, vol. 39, n^o 2, pp. 41-47.
• 69G. Taentzer.
  AGG: A Graph Transformation Environment for Modeling and Validation of Software, in: Applications of Graph Transformations with Industrial Relevance, Second International Workshop (AGTIVE'03), 2003, pp. 446-453.
• 70J. Taillard, F. Guyomarc'h, J.-L. Dekeyser.
  A Graphical Framework for High Performance Computing using an MDE Approach, in: 16th Euromicro International Conference on Parallel, Distributed and network-based Processing, Toulouse, France, February 2008.
• 71Y. Velegrakis, R. J. Miller, J. Mylopoulos.
  Representing and Quering Data transformations, in: International conference on Data Engineering (ICDE), April 2005, pp. 81-92.