Bibliography

Major publications by the team in recent years

• 1M. Cornero, R. Costa, R. Fernández Pascual, A. Ornstein, E. Rohou.
  An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems, in: Conference on HiPEAC, Göteborg, Sweden, P. Stenström, M. Dubois, M. Katevenis, R. Gupta, T. Ungerer (editors), Springer, January 2008, pp. 130–144.
• 2R. Costa, E. Rohou.
  Comparing the size of .NET applications with native code, in: 3rd Intl Conference on Hardware/software codesign and system synthesis, Jersey City, NJ, USA, P. Eles, A. Jantsch, R. A. Bergamaschi (editors), ACM, September 2005, pp. 99–104.
• 3D. Hardy, I. Puaut.
  WCET analysis of multi-level non-inclusive set-associative instruction caches, in: Proc. of the 29th IEEE Real-Time Systems Symposium, Barcelona, Spain, December 2008.
• 4T. Lafage, A. Seznec.
  Choosing Representative Slices of Program Execution for Microarchitecture Simulations: A Preliminary Application to the Data Stream, in: Workload Characterization of Emerging Applications, Kluwer Academic Publishers, 2000, pp. 145–163.
• 5P. Michaud, Y. Sazeides, A. Seznec, T. Constantinou, D. Fetis.
  A study of thread migration in temperature-constrained multi-cores, in: ACM Transactions on Architecture and Code Optimization, 2007, vol. 4, n^o 2, 9 p.
• 6P. Michaud, A. Seznec, S. Jourdan.
  An Exploration of Instruction Fetch Requirement in Out-of-Order Superscalar Processors, in: International Journal of Parallel Programming, 2001, vol. 29, n^o 1, pp. 35-58.
• 7E. Rohou, M. Smith.
  Dynamically managing processor temperature and power, in: Second Workshop on Feedback-Directed Optimizations, 1999.
• 8A. Seznec, P. Michaud.
  A case for (partially)-tagged geometric history length predictors, in: Journal of Instruction Level Parallelism (http://www.jilp.org/vol8), April 2006.
  http://www.jilp.org/vol8
• 9A. Seznec, N. Sendrier.
  HAVEGE: a user-level software heuristic for generating empirically strong random numbers, in: ACM Transactions on Modeling and Computer Systems, October 2003.
• 10A. Seznec.
  Analysis of the O-GEHL branch predictor, in: Proceedings of the 32nd Annual International Symposium on Computer Architecture, June 2005.

Publications of the year

Doctoral Dissertations and Habilitation Theses

• 11J. Lai.
  Modèle analytique de performance orienté débit d'évaluation de performance des accélérateurs programmables, Université de Rennes I, February 2013.
  http://hal.inria.fr/tel-00908579
• 12B. Lesage.
  Architecture multi-coeurs et temps d'exécution au pire cas, Université Rennes 1, May 2013.
  http://hal.inria.fr/tel-00870971
• 13N. Prémillieu.
  Améliorer la performance séquentielle à l'ère des processeurs massivement multicœurs, Université Rennes 1, December 2013.
  http://hal.inria.fr/tel-00916589
• 14R. A. Velásquez Vélez.
  Behavioral Application-dependent Superscalar Core Modeling, Université Rennes 1, April 2013.
  http://hal.inria.fr/tel-00908544

Articles in International Peer-Reviewed Journals

• 15E. Rohou, K. Williams, D. Yuste.
  Vectorization Technology To Improve Interpreter Performance, in: ACM Transactions on Architecture and Code Optimization, January 2013, vol. 9, n^o 4, 26:1 p. [ DOI : 10.1145/2400682.2400685 ]
  http://hal.inria.fr/hal-00747072
• 16R. A. Velasquez, P. Michaud, A. Seznec.
  BADCO: Behavioral Application-Dependent Superscalar Core Models, in: International Journal of Parallel Programming, October 2013. [ DOI : 10.1007/s10766-013-0278-1 ]
  http://hal.inria.fr/hal-00907659

Articles in National Peer-Reviewed Journals

• 17N. Brunie, S. Collange.
  Reconvergence de contrôle implicite pour les architectures SIMT, in: Technique et Science Informatiques (TSI), February 2013, vol. 32, n^o 2, pp. 153-178. [ DOI : 10.3166/TSI.32.153-178 ]
  http://hal.inria.fr/hal-00787749

International Conferences with Proceedings

• 18M. Arnold, S. Collange.
  The Denormal Logarithmic Number System, in: ASAP 2013 - 24th IEEE International Conference on Application-specific Systems, Architectures and Processors, Washington D.C., United States, June 2013, pp. 117-124.
  http://hal.inria.fr/hal-00832505
• 19F. Bodin, D. Romain, G. Colin De Verdiere.
  One OpenCL to Rule Them All?, in: International Workshop on Multi-/Many-core Computing Systems
, Edinburgh, United Kingdom, September 2013.
  http://hal.inria.fr/hal-00920910
• 20D. Hardy, M. Kleanthous, I. Sideris, A. Saidi, E. Ozer, Y. Sazeides.
  An Analytical Framework for Estimating TCO and Exploring Data Center Design Space, in: IEEE International Symposium on Performance Analysis of Systems and Software, Austin, United States, April 2013.
  http://hal.inria.fr/hal-00914593
• 21D. Hardy, I. Puaut.
  Static probabilistic Worst Case Execution Time Estimation for architectures with Faulty Instruction Caches, in: 21st International Conference on Real-Time Networks and Systems, Sophia Antipolis, France, October 2013. [ DOI : 10.1145/2516821.2516842 ]
  http://hal.inria.fr/hal-00862604
• 22J. Lai, A. Seznec.
  Performance Upper Bound Analysis and Optimization of SGEMM on Fermi and Kepler GPUs, in: CGO '13 - 2013 International Symposium on Code Generation and Optimization, Shenzhen, China, February 2013.
  http://hal.inria.fr/hal-00789958
• 23D. Potop-Butucaru, I. Puaut.
  Integrated Worst-Case Execution Time Estimation of Multicore Applications, in: 13th International Workshop on Worst-Case Execution Time Analysis, Paris, France, C. Maiza (editor), Schloss Dagstuh, July 2013, vol. 30, pp. 21-31. [ DOI : 10.4230/OASIcs.WCET.2013.i ]
  http://hal.inria.fr/hal-00909330
• 24E. Riou, E. Rohou, P. Clauss, N. Hallou, A. Ketterlin.
  PADRONE: a Platform for Online Profiling, Analysis, and Optimization, in: DCE 2014 - International workshop on Dynamic Compilation Everywhere, Vienne, Austria, January 2014.
  http://hal.inria.fr/hal-00917950
• 25M. Solinas, R. Badia, F. Bodin, A. Cohen, P. Evripidou, P. Faraboschi, B. Fechner, G. R. Gao, A. Garbade, S. Girbal, D. Goodman, B. Khan, S. Koliai, F. Li, M. Luján, L. Morin, A. Mendelson, N. Navarro, A. Pop, P. Trancoso, T. Ungerer, M. Valero, S. Weis, I. Watson, S. Zuckerman, R. Giorgi.
  The TERAFLUX Project: Exploiting the DataFlow Paradigm in Next Generation Teradevices, in: DSD, Los Alamitos, United States, 2013, pp. 272-279.
  http://hal.inria.fr/hal-00920903
• 26R. A. Velasquez, P. Michaud, A. Seznec.
  Selecting Benchmark Combinations for the Evaluation of Multicore Throughput, in: International Symposium on Performance Analysis of Systems and Software, Austin, United States, February 2013.
  http://hal.inria.fr/hal-00788824
• 27M. Yusuf, A. El-Mahdy, E. Rohou.
  On-Stack Replacement to Improve JIT-based Obfuscation - A Preliminary Study, in: International Japan-Egypt Conference on Electronics, Communications, and Computers, Cairo, Egypt, December 2013.
  http://hal.inria.fr/hal-00909722

Internal Reports

• 28M. Arnold, S. Collange.
  Options for Denormal Representation in Logarithmic Arithmetic, Inria, January 2014, n^o RR-8412, 27 p.
  http://hal.inria.fr/hal-00909096
• 29S. Eyerman, P. Michaud.
  Defining metrics for multicore throughput on multiprogrammed workloads, Inria, November 2013, n^o RR-8401.
  http://hal.inria.fr/hal-00908864
• 30S. N. Natarajan, B. Swamy, A. Seznec.
  Modeling multi-threaded programs execution time in the many-core era, Inria, December 2013, n^o RR-8453, 23 p.
  http://hal.inria.fr/hal-00914335
• 31A. Perais, A. Seznec.
  EOLE: Paving the Way for an Effective Implementation of Value Prediction, Inria, November 2013, n^o RR-8402, 25 p.
  http://hal.inria.fr/hal-00907973
• 32A. Perais, A. Seznec.
  Practical Data Value Speculation for Future High-end Processors, Inria, November 2013, n^o RR-8395, 21 p.
  http://hal.inria.fr/hal-00904743
• 33D. Potop-Butucaru, I. Puaut.
  Integrated Worst-Case Response Time Evaluation of Multicore Non-Preemptive Applications, Inria, February 2013, n^o RR-8234.
  http://hal.inria.fr/hal-00787931
• 34N. Prémillieu, A. Seznec.
  Efficient Out-of-Order Execution of Guarded ISAs, Inria, November 2013, n^o RR-8406, 24 p.
  http://hal.inria.fr/hal-00910335
• 35N. Prémillieu, A. Seznec.
  SPREPI: Selective Prediction and REplay for predicated Instructions, Inria, August 2013, n^o RR-8351, 25 p.
  http://hal.inria.fr/hal-00856160
• 36E. Rohou, B. Narasimha Swamy, A. Seznec.
  Branch Prediction and the Performance of Interpreters - Don't Trust Folklore, Inria, November 2013, n^o RR-8405, 23 p.
  http://hal.inria.fr/hal-00911146
• 37D. Sampaio, R. De Souza, S. Collange, F. Magno Quintão Pereira.
  Divergence Analysis, Inria, November 2013, n^o RR-8411, 42 p.
  http://hal.inria.fr/hal-00909072

Other Publications

• 38M. Hataba, A. El-Mahdy, A. Shoukry, E. Rohou.
  OJIT: A Novel Secure Remote Execution Technology By Obfuscated Just-In-Time Compilation, April 2013, The Third European LLVM Conference.
  http://hal.inria.fr/hal-00909766

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• 41R. S. Chappell, J. Stark, S. P. Kim, S. K. Reinhardt, Y. N. Patt.
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• 42C. Ferdinand, R. Wilhelm.
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• 45Y. Liang, T. Mitra.
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• 46T. Lundqvist, P. Stenström.
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• 48T. Sherwood, E. Perelman, G. Hamerly, B. Calder.
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• 49K. Skadron, M. Stan, W. Huang, S. Velusamy.
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