Project-Team Espresso
Members
Overall Objectives
Research Program
Application Domains
Software and Platforms
New Results
Partnerships and Cooperations
Dissemination
Bibliography
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Bibliography

Major publications by the team in recent years
  • 1A. Benveniste, P. Caspi, S. Edwards, N. Halbwachs, P. Le Guernic, R. de Simone.
    The Synchronous Languages Twelve Years Later, in: Proceedings of the IEEE Special issue on Modeling and Design of Embedded Systems, 2003, vol. 91, no 1.
    http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.96.1117
  • 2L. Besnard, T. Gautier, P. Le Guernic, J.-P. Talpin.
    Compilation of Polychronous Data Flow Equations, in: Synthesis of Embedded Software, S. K. Shukla, J.-P. Talpin (editors), Springer, 2010, pp. 1-40. [ DOI : 10.1007/978-1-4419-6400-7_1 ]
    http://hal.inria.fr/inria-00540493
  • 3L. Besnard, T. Gautier, M. Moy, J.-P. Talpin, K. Johnson, F. Maraninchi.
    Automatic translation of C/C++ parallel code into synchronous formalism using an SSA intermediate form, in: Electronic Communication of the European Association of Software Science and Technology, 2009, vol. 23, Automated Verification of Critical Systems 2009.
    http://journal.ub.tu-berlin.de/eceasst/article/view/312/301
  • 4C. Brunette, J.-P. Talpin, A. Gamatié, T. Gautier.
    A metamodel for the design of polychronous systems, in: The Journal of Logic and Algebraic Programming, 2009, vol. 78, no 4, pp. 233 - 259, IFIP WG1.8 Workshop on Applying Concurrency Research in Industry. [ DOI : 10.1016/j.jlap.2008.11.005 ]
    http://www.sciencedirect.com/science/article/pii/S1567832608000957
  • 5A. Gamatié, T. Gautier, P. Le Guernic, J.-P. Talpin.
    Polychronous Design of Embedded Real-Time Applications, in: ACM Transactions on Software Engineering and Methodology (TOSEM), April 2007, vol. 16, no 2.
    http://doi.acm.org/10.1145/1217295.1217298
  • 6A. Gamatié, T. Gautier.
    The Signal Synchronous Multiclock Approach to the Design of Distributed Embedded Systems, in: IEEE Transactions on Parallel and Distributed Systems, 2010, vol. 21, no 5, pp. 641-657. [ DOI : 10.1109/TPDS.2009.125 ]
    http://hal.inria.fr/inria-00522794
  • 7A. Gamatié, T. Gautier, P. Le Guernic.
    Synchronous design of avionic applications based on model refinements, in: Journal of Embedded Computing (IOS Press), 2006, vol. 2, no 3-4, pp. 273-289.
    http://hal.archives-ouvertes.fr/hal-00541523
  • 8P. Le Guernic, J.-P. Talpin, J.-C. Le Lann.
    Polychrony for system design, in: Journal of Circuits, Systems and Computers, Special Issue on Application Specific Hardware Design, June 2003, vol. 12, no 03.
    http://hal.inria.fr/docs/00/07/18/71/PDF/RR-4715.pdf
  • 9D. Potop-Butucaru, Y. Sorel, R. de Simone, J.-P. Talpin.
    From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations, in: Fundamenta Informaticae, January 2011, vol. 108, no 1-2, pp. 91–118.
    http://dl.acm.org/citation.cfm?id=2362088.2362094
  • 10J.-P. Talpin, P. Le Guernic, S. K. Shukla, R. Gupta.
    A compositional behavioral modeling framework for embedded system design and conformance checking, in: International Journal of Parallel Programming, December 2005, vol. 33, no 6, pp. 613-643. [ DOI : 10.1007/s10766-005-8907-y ]
    http://hal.archives-ouvertes.fr/hal-00541986
  • 11J.-P. Talpin, J. Ouy, T. Gautier, L. Besnard, P. Le Guernic.
    Compositional design of isochronous systems, in: Science of Computer Programming, February 2012, vol. 77, no 2, pp. 113-128. [ DOI : 10.1016/j.scico.2010.06.006 ]
    http://hal.archives-ouvertes.fr/hal-00768341
Publications of the year

Doctoral Dissertations and Habilitation Theses

Articles in International Peer-Reviewed Journals

  • 14J. Brandt, M. Gemünde, K. Schneider, S. K. Shukla, J.-P. Talpin.
    Embedding Polychrony into Synchrony, in: IEEE Transactions on Software Engineering, 2013.
    http://hal.inria.fr/hal-00763317
  • 15V. C. Ngo, L. Besnard, P. Le Guernic, J.-P. Talpin, T. Gautier.
    Formal Verification of Synchronous Data-flow Program Transformations Toward Certified Compilers, in: Frontiers in Computer Science, July 2013.
    http://hal.inria.fr/hal-00846279
  • 16H. Yu, Y. Ma, T. Gautier, L. Besnard, P. Le Guernic, J.-P. Talpin.
    Polychronous modeling, analysis, verification and simulation for timed software architectures, in: Journal of Systems Architecture, November 2013, vol. 59, no 10, pp. 1157-1170. [ DOI : 10.1016/j.sysarc.2013.08.004 ]
    http://hal.inria.fr/hal-00916418
  • 17H. Yu, Y. Ma, T. Gautier, L. Besnard, J.-P. Talpin, P. Le Guernic, Y. Sorel.
    Exploring system architectures in AADL via Polychrony and SynDEx, in: Frontiers of Computer Science, October 2013, vol. 7, no 5, pp. 627-649. [ DOI : 10.1007/s11704-013-2307-z ]
    http://hal.inria.fr/hal-00916445

International Conferences with Proceedings

  • 18A. Bouakaz, J.-P. Talpin.
    Buffer Minimization in Earliest-Deadline First Scheduling of Dataflow Graphs, in: ACM SIG- PLAN/SIGBED conference on languages, compilers and tools for embedded systems, Seattle, WA, United States, June 2013, vol. 48, pp. 133-142. [ DOI : 10.1145/2499369.2465558 ]
    http://hal.inria.fr/hal-00916485
  • 19A. Bouakaz, J.-P. Talpin.
    Design of Safety-Critical Java Level 1 Applications Using Affine Abstract Clocks, in: International Workshop on Software and Compilers for Embedded Systems, St. Goar, Germany, June 2013, pp. 58-67. [ DOI : 10.1145/2463596.2463600 ]
    http://hal.inria.fr/hal-00916487
  • 20Y. Ma, H. Yu, T. Gautier, P. Le Guernic, J.-P. Talpin, L. Besnard, M. Heitz.
    Toward Polychronous Analysis and Validation for Timed Software Architectures in AADL, in: The Design, Automation, and Test in Europe (DATE) conference, Grenoble, France, March 2013, 6 p.
    http://hal.inria.fr/hal-00763379
  • 21J.-P. Talpin, J. Brandt, M. Gemünde, K. Schneider, S. Shukla.
    Constructive Polychronous Systems, in: Logical Foundations of Computer Science, San Diego, CA, United States, S. Artemov, A. Nerode (editors), Lecture Notes in Computer Science, Springer, 2013, vol. 7734.
    http://hal.inria.fr/hal-00763371
References in notes
  • 22Cost-efficient methods and processes for safety relevant embedded systems (CESAR project), 2012.
    http://www.cesarproject.eu/
  • 23Open Platform for the Engineering of Embedded Systems (OPEES Project), 2012.
    http://www.opees.org/
  • 24Polychrony Update Site for Eclipse plug-ins, 2009.
    http://www.irisa.fr/espresso/Polychrony/update/
  • 25Airlines Electronic Engineering Committee.
    ARINC Report 651-1: Design Guidance for Integrated Modular Avionics, Aeronautical radio, Inc., Annapolis, Maryland, 1997.
  • 26Airlines Electronic Engineering Committee.
    ARINC Specification 653: Avionics Application Software Standard Interface, Aeronautical radio, Inc., Annapolis, Maryland, 1997.
  • 27P. Amagbegnon, L. Besnard, P. Le Guernic.
    Implementation of the data-flow synchronous language SIGNAL, in: ACM SIGPLAN Notices, June 1995, vol. 30, no 6, pp. 163-173. [ DOI : 10.1145/223428.207134 ]
    http://hal.archives-ouvertes.fr/hal-00544128
  • 28S. S. Battacharyya, E. A. Lee, P. K. Murthy.
    Software synthesis from dataflow graphs, Kluwer Academic Publishers, Norwell, MA, USA, 1996.
  • 29A. Benveniste, B. Caillaud, P. Le Guernic.
    From synchrony to asynchrony, in: CONCUR'99, Concurrency Theory, 10th International Conference, J. C. M. Baeten, S. Mauw (editors), Lecture Notes in Computer Science, Springer, August 1999, vol. 1664, pp. 162–177.
    http://hal.inria.fr/inria-00073032
  • 30A. Benveniste, P. Caspi, L. Carloni, A. Sangiovanni-Vincentelli.
    Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment, in: Embedded Software Conference (EMSOFT'03), Springer Verlag, 2003.
  • 31A. Benveniste, P. Le Guernic, P. Aubry.
    Compositionality in dataflow synchronous languages: specification & code generation, in: Compositionality: The Significant Difference, Springer, 1998, pp. 61–80.
    http://hal.inria.fr/inria-00073379
  • 32A. Benveniste, P. Le Guernic, C. Jacquemot.
    Synchronous programming with events and relations: the Signal language and its semantics, in: Science of Computer Programming, September 1991, vol. 16, no 2, pp. 103-149.
    http://dx.doi.org/10.1016/0167-6423(91)90001-E
  • 33L. Besnard, T. Gautier, P. Le Guernic.
    SIGNAL V4-Inria version: Reference Manual, 2009.
    http://www.irisa.fr/espresso/Polychrony/index.php
  • 34G. Blisen, M. Engels, R. Lauwereins, J. Peperstraete.
    Cycle-static dataflow, in: Trans. Sig. Proc., February 1996, vol. 44, no 2, pp. 397–408.
  • 35A. Bouakaz, J.-P. Talpin, J. Vitek.
    Affine Data-Flow Graphs for the Synthesis of Hard Real-Time Applications, in: Proceedings of the 2012 12th International Conference on Application of Concurrency to System Design, Hamburg, Germany, ACM, 2012, pp. 183-192. [ DOI : 10.1109/ACSD.2012.16 ]
    http://hal.inria.fr/hal-00763387
  • 36J. Brandt, K. Schneider.
    Separate Translation of Synchronous Programs to Guarded Actions, Department of Computer Science, University of Kaiserslautern, Kaiserslautern, Germany, March 2011, no 382/11.
  • 37R. I. Davis, A. Burns.
    A survey of hard real-time scheduling for multiprocessor systems, in: ACM Comput. Surv., 2011, vol. 43, no 4, pp. 35:1–35:44.
  • 38B. Dutertre, L. de Moura.
    Yices sat-solver, 2009.
    http://yices.csl.sri.com
  • 39A. Gamatié.
    Designing Embedded Systems with the SIGNAL Programming Language, Springer, 2009.
    http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4419-0940-4
  • 40T. Gautier, P. Le Guernic.
    Code generation in the SACRES project, in: Towards System Safety, Proceedings of the Safety-critical Systems Symposium, SSS'99, Huntingdon, Royaume-Uni, Springer, 1999, pp. 127-149.
    http://hal.archives-ouvertes.fr/hal-00543824
  • 41A. Girault.
    A survey of automatic distribution method for synchronous programs, in: International workshop on synchronous languages, applications and programs, SLAP, 2005, vol. 5.
  • 42Inria AOSTE TEAM.
    SynDEx, 2013.
    http://www-rocq.inria.fr/syndex/
  • 43JSR-302.
    Safety critical Java technology specification, 2010.
  • 44G. Kahn.
    The Semantics of a Simple Language for Parallel Programming, in: IFIP Congress, 1974, pp. 471-475.
  • 45P. Le Guernic, T. Gautier, M. Le Borgne, C. Le Maire.
    Programming Real-Time Applications with Signal, in: Proceedings of the IEEE, 1991, vol. 79, no 9, pp. 1321-1336. [ DOI : 10.1109/5.97301 ]
    http://hal.inria.fr/inria-00540460
  • 46E. A. Lee, D. G. Messerschmitt.
    Synchronous data flow, in: Proceedings of the IEEE, 1987, pp. 1235–1245.
  • 47V. C. Ngo.
    SigCert, 2013.
    https://scm.gforge.inria.fr/svn/sigcert/trunk
  • 48A. Pnueli, M. Siegel, E. Singerman.
    Translation validation: From SIGNAL to C, in: Correct Sytem Design Recent Insights and Advances, 2000, pp. 231-255.
  • 49A. Pnueli, M. Siegel, E. Singerman.
    Translation validation, in: Proceedings of TACAS'98, 1998, pp. 151-166.
  • 50K. Schneider.
    The Synchronous Programming Language Quartz, Department of Computer Science, University of Kaiserslautern, Kaiserslautern, Germany, December 2009, no 375.
  • 51L. Sha, T. Abdelzaher, K.-E. Arzén, A. Cervin, T. Baker, A. Burns, G. Buttazzo, M. Caccamo, J. Lehoczky, A. K. Mok.
    Real time scheduling theory: a historical perspective, in: Real-Time Syst., 2004, vol. 28, no 2-3, pp. 101–155.
  • 52D. Tang, A. Plsek, J. Vitek.
    Static checking of safety critical Java annotations, in: Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems, 2010, pp. 148–154.
  • 53J.-B. Tristan, P. Govereau, G. Morrisett.
    Evaluating value-graph translation validation for LLVM, in: ACM SIGPLAN Conference on Programming and Language Design Implementation, 2011.
  • 54L. de Moura, N. Bjorner.
    Satisfiability Modulo Theories: An appetizer, in: Brazilian Symposium on Formal Methods, 2009.

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