Bibliography

Articles in International Peer-Reviewed Journals

• 1V. Elango, N. Sedaghati, F. Rastello, L.-N. Pouchet, J. Ramanujam, r. Teodorescu, P. Sadayappan.
  On Using the Roofline Model with Lower Bounds on Data Movement, in: ACM Transactions on Architecture and Code Optimization (TACO) , January 2015, vol. 11, n^o 4, pp. 67:1–67:23.
  https://hal.inria.fr/hal-01104765

International Conferences with Proceedings

• 2B. Dupont De Dinechin, D. van Amstel, M. Poulhies, G. Lager.
  Time-critical computing on a single-chip massively parallel processor, in: Conference on Design, Automation & Test in Europe, Dresden, Germany, European Design and Automation Association (editor), Proceedings of the Conference on Design, Automation & Test in Europe 2014, March 2014, pp. 97:1-97:6.
  https://hal.inria.fr/hal-01090449
• 3B. Dupont De Dinechin, D. Yves, D. van Amstel, A. Ghiti.
  Guaranteed Services of the NoC of a Manycore Processor, in: International Workshop on Network-on-Chips, Cambridge, United Kingdom, Proceedings of the International Workshop on Network-on-Chips 2014, December 2014, 6 p.
  https://hal.inria.fr/hal-01102657
• 4V. Elango, F. Rastello, L.-N. Pouchet, J. Ramanujam, P. Sadayappan.
  On Characterizing the Data Movement Complexity of Computational DAGs for Parallel Execution, in: Symposium on Parallelism in Algorithms and Architectures (SPAA '14), Prague, Poland, ACM, 2014.
  https://hal.inria.fr/hal-01016090
• 5V. Elango, F. Rastello, L.-N. Pouchet, J. Ramanujam, P. Sadayappan.
  On Characterizing the Data Access Complexity of Programs, in: 42nd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL, Mumbai, India, ACM, January 2015, pp. 567-580.
  https://hal.inria.fr/hal-01104556
• 6K. Stock, M. Kong, T. Grosser, L.-N. Pouchet, F. Rastello, J. Ramanujam, P. Sadayappan.
  A Framework for Enhancing Data Reuse via Associative Reordering, in: PLDI '14 - 35th ACM SIGPLAN Conference on Programming Language Design and Implementation, Edinburgh, United Kingdom, ACM, June 2014, pp. 65-76. [ DOI : 10.1145/2594291.2594342 ]
  https://hal.inria.fr/hal-01016093
• 7A. Tavares, F. Rastello, B. Boissinot, F. Pereira.
  Parameterized Construction of Program Representations for Sparse Dataflow Analyses, in: CC 2014 - 23rd International Conference on Compiler Construction, Grenoble, France, Springer, 2014.
  https://hal.inria.fr/hal-00921461

Internal Reports

• 8L. Domagala, F. Rastello, S. Ponnuswany, D. Van Amstel.
  A Tiling Perspective for Register Optimization, May 2014, n^o RR-8541, 24 p.
  https://hal.inria.fr/hal-00998915
• 9V. Elango, F. Rastello, L.-N. Pouchet, J. Ramanujam, P. Sadayappan.
  On Characterizing the Data Movement Complexity of Computational DAGs for Parallel Execution, April 2014, n^o RR-8522, 27 p.
  https://hal.inria.fr/hal-00980580
• 10A. Tavares, B. Boissinot, F. Pereira, F. Rastello.
  Parameterized Construction of Program Representations for Sparse Dataflow Analyses, Inria, March 2014, n^o RR-8491, 27 p.
  https://hal.inria.fr/hal-00963590