Project-Team Tea
Members
Overall Objectives
Research Program
Application Domains
Highlights of the Year
New Software and Platforms
New Results
Bilateral Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography
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Bibliography

Major publications by the team in recent years
  • 1L. Besnard, T. Gautier, P. Le Guernic, J.-P. Talpin.
    Compilation of Polychronous Data Flow Equations, in: Synthesis of Embedded Software, S. K. Shukla, J.-P. Talpin (editors), Springer, 2010, pp. 1-40. [ DOI : 10.1007/978-1-4419-6400-7_1 ]
    http://hal.inria.fr/inria-00540493
  • 2A. Bouakaz, J.-P. Talpin.
    Design of Safety-Critical Java Level 1 Applications Using Affine Abstract Clocks, in: International Workshop on Software and Compilers for Embedded Systems, St. Goar, Germany, June 2013, pp. 58-67. [ DOI : 10.1145/2463596.2463600 ]
    https://hal.inria.fr/hal-00916487
  • 3C. Brunette, J.-P. Talpin, A. Gamatié, T. Gautier.
    A metamodel for the design of polychronous systems, in: The Journal of Logic and Algebraic Programming, 2009, vol. 78, no 4, pp. 233 - 259, IFIP WG1.8 Workshop on Applying Concurrency Research in Industry. [ DOI : 10.1016/j.jlap.2008.11.005 ]
    http://www.sciencedirect.com/science/article/pii/S1567832608000957
  • 4A. Gamatié, T. Gautier, P. Le Guernic, J.-P. Talpin.
    Polychronous Design of Embedded Real-Time Applications, in: ACM Transactions on Software Engineering and Methodology (TOSEM), April 2007, vol. 16, no 2.
    http://doi.acm.org/10.1145/1217295.1217298
  • 5A. Gamatié, T. Gautier.
    The Signal Synchronous Multiclock Approach to the Design of Distributed Embedded Systems, in: IEEE Transactions on Parallel and Distributed Systems, 2010, vol. 21, no 5, pp. 641-657. [ DOI : 10.1109/TPDS.2009.125 ]
    http://hal.inria.fr/inria-00522794
  • 6A. Gamatié, T. Gautier, P. Le Guernic.
    Synchronous design of avionic applications based on model refinements, in: Journal of Embedded Computing (IOS Press), 2006, vol. 2, no 3-4, pp. 273-289.
    http://hal.archives-ouvertes.fr/hal-00541523
  • 7T. Gautier, C. Guy, A. Honorat, P. Le Guernic, J.-P. Talpin, L. Besnard.
    Polychronous Automata and their Use for Formal Validation of AADL Models, in: Frontiers of Computer Science -Springer-, December 2016.
    https://hal.inria.fr/hal-01411257
  • 8P. Le Guernic, J.-P. Talpin, J.-C. Le Lann.
    Polychrony for system design, in: Journal of Circuits, Systems and Computers, Special Issue on Application Specific Hardware Design, June 2003, vol. 12, no 03.
    http://hal.inria.fr/docs/00/07/18/71/PDF/RR-4715.pdf
  • 9D. Potop-Butucaru, Y. Sorel, R. de Simone, J.-P. Talpin.
    From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations, in: Fundamenta Informaticae, January 2011, vol. 108, no 1-2, pp. 91–118.
    http://dl.acm.org/citation.cfm?id=2362088.2362094
  • 10J.-P. Talpin, J. Ouy, T. Gautier, L. Besnard, P. Le Guernic.
    Compositional design of isochronous systems, in: Science of Computer Programming, February 2012, vol. 77, no 2, pp. 113-128. [ DOI : 10.1016/j.scico.2010.06.006 ]
    http://hal.archives-ouvertes.fr/hal-00768341
  • 11H. Yu, J. Prashi, J.-P. Talpin, S. K. Shukla, S. Shiraishi.
    Model-Based Integration for Automotive Control Software, in: Digital Automation Conference, San Francisco, United States, ACM, June 2015.
    https://hal.inria.fr/hal-01148905
Publications of the year

Articles in International Peer-Reviewed Journals

  • 12T. Gautier, C. Guy, A. Honorat, P. Le Guernic, J.-P. Talpin, L. Besnard.
    Polychronous Automata and their Use for Formal Validation of AADL Models, in: Frontiers of Computer Science -Springer-, December 2016.
    https://hal.inria.fr/hal-01411257

International Conferences with Proceedings

  • 13D. Baelde, S. Lunel, S. Schmitz.
    A Sequent Calculus for a Modal Logic on Finite Data Trees, in: CSL 2016, Marseille, France, J.-M. Talbot, L. Regnier (editors), Leibniz International Proceedings in Informatics, LZI, September 2016, vol. 62, no 32, pp. 1–16. [ DOI : 10.4230/LIPIcs.CSL.2016.32 ]
    https://hal.inria.fr/hal-01191172
  • 14L. Besnard, T. Gautier, C. Guy, P. Le Guernic, J.-P. Talpin, B. R. Larson, E. Borde.
    Formal semantics of behavior specifications in the architecture analysis and design language standard, in: 18th IEEE International High-Level Design Validation and Test Workshop, Santa Cruz, United States, High-level design, verification and test, IEEE, October 2016, pp. 30 - 39. [ DOI : 10.1109/HLDVT.2016.7748252 ]
    https://hal.inria.fr/hal-01419968
  • 15C. Junke, T. Gautier, J.-P. Talpin, L. Besnard.
    Integration of polychrony and QGen model compiler, in: ERTS'16 - European Congress on Embeddd Real-Rime Software and Systems, Toulouse, France, January 2016.
    https://hal.inria.fr/hal-01241808
  • 16V. C. Ngo, A. Legay, V. Joloboff.
    PSCV: A Runtime Verification Tool for Probabilistic SystemC Models, in: CAV 2016 - 28th International Conference on Computer Aided Verification, Toronto, Canada, S. Chaudhuri, A. Farzan (editors), LNCS - Lecture Notes in Computer Science, Springer, July 2016, vol. 9779, pp. 84 - 91. [ DOI : 10.1007/978-3-319-41528-4_5 ]
    https://hal.inria.fr/hal-01406488
  • 17D. Yue, V. Joloboff, F. Mallet.
    Flexible Runtime Verification Based On Logical Clock Constraints, in: FDL 2016 - Forum on specification & Design Languages, Bremen, Germany, September 2016.
    https://hal.inria.fr/hal-01421890

Conferences without Proceedings

  • 18O. Aumage, D. Barthou, A. Honorat.
    A Stencil DSEL for Single Code Accelerated Computing with SYCL, in: SYCL 2016 1st SYCL Programming Workshop during the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Barcelone, Spain, March 2016.
    https://hal.archives-ouvertes.fr/hal-01290099
  • 19O. Sankur, J.-P. Talpin.
    An Abstraction Technique For Parameterized Model Checking of Leader Election Protocols: Application to FTSP, in: 23rd International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), Uppsala, Sweden, April 2017.
    https://hal.archives-ouvertes.fr/hal-01431472

Internal Reports

  • 20L. Besnard, T. Gautier, P. Le Guernic, C. Guy, J.-P. Talpin, B. Larson, E. Borde.
    Formal semantics of behavior specifications in the architecture analysis and design language standard, Inria, 2016, no 8950, pp. 30 - 39. [ DOI : 10.1109/HLDVT.2016.7748252 ]
    https://hal.inria.fr/hal-01419973

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