Project-Team Pacap
Team, Visitors, External Collaborators
Overall Objectives
Research Program
Application Domains
Highlights of the Year
New Software and Platforms
New Results
Bilateral Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography
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Bibliography

Major publications by the team in recent years
  • 1F. Bodin, T. Kisuki, P. M. W. Knijnenburg, M. F. P. O'Boyle, E. Rohou.
    Iterative Compilation in a Non-Linear Optimisation Space, in: Workshop on Profile and Feedback-Directed Compilation (FDO-1), in conjunction with PACT '98, October 1998.
  • 2A. Cohen, E. Rohou.
    Processor Virtualization and Split Compilation for Heterogeneous Multicore Embedded Systems, in: DAC, June 2010, pp. 102–107.
  • 3N. Hallou, E. Rohou, P. Clauss, A. Ketterlin.
    Dynamic Re-Vectorization of Binary Code, in: SAMOS, July 2015.
    https://hal.inria.fr/hal-01155207
  • 4D. Hardy, I. Sideris, N. Ladas, Y. Sazeides.
    The performance vulnerability of architectural and non-architectural arrays to permanent faults, in: MICRO 45, Vancouver, Canada, December 2012.
    https://hal.inria.fr/hal-00747488
  • 5S. Kalathingal, S. Collange, B. Narasimha Swamy, A. Seznec.
    Dynamic Inter-Thread Vectorization Architecture: extracting DLP from TLP, in: International Symposium on Computer Architecture and High-Performance Computing (SBAC-PAD), Los Angeles, United States, October 2016.
    https://hal.inria.fr/hal-01356202
  • 6S. Kalathingal, S. Collange, B. Swamy, A. Seznec.
    DITVA: Dynamic Inter-Thread Vectorization Architecture, in: Journal of Parallel and Distributed Computing, October 2018, pp. 1-32. [ DOI : 10.1016/j.jpdc.2017.11.006 ]
    https://hal.archives-ouvertes.fr/hal-01655904
  • 7P. Michaud.
    A Best-Offset Prefetcher Champion, in: 2nd Data Prefetching Championship, Portland, OR, USA, June 2015.
    https://hal.inria.fr/hal-01165600
  • 8P. Michaud, A. Mondelli, A. Seznec.
    Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters, in: ACM Transactions on Architecture and Code Optimization (TACO) , August 2015, vol. 13, no 3, 22 p. [ DOI : 10.1145/2800787 ]
    https://hal.inria.fr/hal-01193178
  • 9P. Michaud, A. Seznec.
    Pushing the branch predictability limits with the multi-poTAGE+SC predictor : Champion in the unlimited category, in: 4th JILP Workshop on Computer Architecture Competitions (JWAC-4): Championship Branch Prediction (CBP-4), Minneapolis, United States, June 2014.
    https://hal.archives-ouvertes.fr/hal-01087719
  • 10A. Perais, A. Seznec.
    EOLE: Paving the Way for an Effective Implementation of Value Prediction, in: International Symposium on Computer Architecture, Minneapolis, MN, United States, ACM/IEEE, June 2014, vol. 42, pp. 481 - 492. [ DOI : 10.1109/ISCA.2014.6853205 ]
    https://hal.inria.fr/hal-01088130
  • 11A. Perais, A. Seznec.
    Practical data value speculation for future high-end processors, in: International Symposium on High Performance Computer Architecture, Orlando, FL, United States, IEEE, February 2014, pp. 428 - 439. [ DOI : 10.1109/HPCA.2014.6835952 ]
    https://hal.inria.fr/hal-01088116
  • 12E. Riou, E. Rohou, P. Clauss, N. Hallou, A. Ketterlin.
    PADRONE: a Platform for Online Profiling, Analysis, and Optimization, in: Dynamic Compilation Everywhere, Vienna, Austria, January 2014.
  • 13S. Sardashti, A. Seznec, D. A. Wood.
    Skewed Compressed Caches, in: 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, Minneapolis, United States, December 2014.
    https://hal.inria.fr/hal-01088050
  • 14S. Sardashti, A. Seznec, D. A. Wood.
    Yet Another Compressed Cache: a Low Cost Yet Effective Compressed Cache, in: ACM Transactions on Architecture and Code Optimization, September 2016, 25 p.
    https://hal.inria.fr/hal-01354248
  • 15A. Sembrant, T. Carlson, E. Hagersten, D. Black-Shaffer, A. Perais, A. Seznec, P. Michaud.
    Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors, in: International Symposium on Microarchitecture, Micro 2015, Honolulu, United States, Proceeding of the International Symposium on Microarchitecture, Micro 2015, ACM, December 2015.
    https://hal.inria.fr/hal-01225019
  • 16A. Seznec, P. Michaud.
    A case for (partially)-tagged geometric history length predictors, in: Journal of Instruction Level Parallelism, April 2006.
    http://www.jilp.org/vol8
  • 17A. Seznec, J. San Miguel, J. Albericio.
    The Inner Most Loop Iteration counter: a new dimension in branch history , in: 48th International Symposium On Microarchitecture, Honolulu, United States, ACM, December 2015, 11 p.
    https://hal.inria.fr/hal-01208347
  • 18A. Seznec.
    A New Case for the TAGE Branch Predictor, in: MICRO 2011 : The 44th Annual IEEE/ACM International Symposium on Microarchitecture, 2011, Porto Allegre, Brazil, ACM, December 2011.
    https://hal.inria.fr/hal-00639193
  • 19A. Seznec.
    TAGE-SC-L Branch Predictors: Champion in 32Kbits and 256 Kbits category, in: JILP - Championship Branch Prediction, Minneapolis, United States, June 2014.
    https://hal.inria.fr/hal-01086920
Publications of the year

Doctoral Dissertations and Habilitation Theses

  • 20R. Bouziane.
    Software-level Analysis and Optimization to Mitigate the Cost of Write Operations on Non-Volatile Memories, Université de Rennes 1 [UR1], December 2018.
    https://hal.inria.fr/tel-01954076
  • 21V. A. Nguyen.
    Cache-conscious Off-Line Real-Time Scheduling for Multi-Core Platforms: Algorithms and Implementation, Université de Rennes 1 [UR1], February 2018.
    https://hal.inria.fr/tel-01933422
  • 22S. Rokicki.
    Hardware Accelerated Dynamic Binary Translation, Université de Rennes 1 [UR1], December 2018.
    https://hal.archives-ouvertes.fr/tel-01959136
  • 23B. Rouxel.
    Minimising communication costs impact when scheduling real-time applications on multi-core architectures, Université de Rennes 1, December 2018.
    https://hal.inria.fr/tel-01945456

Articles in International Peer-Reviewed Journals

  • 24S. Kalathingal, S. Collange, B. Swamy, A. Seznec.
    DITVA: Dynamic Inter-Thread Vectorization Architecture, in: Journal of Parallel and Distributed Computing, October 2018, pp. 1-32. [ DOI : 10.1016/j.jpdc.2017.11.006 ]
    https://hal.archives-ouvertes.fr/hal-01655904
  • 25P. Michaud.
    An Alternative TAGE-like Conditional Branch Predictor, in: ACM Transactions on Architecture and Code Optimization, May 2018, vol. 15, no 3, pp. 1-24. [ DOI : 10.1145/3226098 ]
    https://hal.inria.fr/hal-01799442
  • 26S. Rokicki, E. Rohou, S. Derrien.
    Hybrid-DBT: Hardware/Software Dynamic Binary Translation Targeting VLIW, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August 2018, pp. 1-14. [ DOI : 10.1109/TCAD.2018.2864288 ]
    https://hal.archives-ouvertes.fr/hal-01856163
  • 27M. Yusuf, A. El-Mahdy, E. Rohou.
    Runtime, Speculative On-Stack Parallelization of For-Loops in Binary Programs, in: IEEE Letters of the Computer Society, October 2018, pp. 1-4. [ DOI : 10.1109/LOCS.2018.2872454 ]
    https://hal.inria.fr/hal-01890719

Invited Conferences

  • 28C. Silvano, G. Agosta, A. Bartolini, A. R. Beccari, L. Benini, L. Besnard, J. Bispo, R. Cmar, J. M. R. Cardoso, C. Cavazzoni, S. Cherubin, D. Gadioli, M. Golasowski, I. Lasri, J. Martinovič, G. Palermo, P. Pinto, E. Rohou, N. Sanna, K. Slaninová, E. Vitali.
    ANTAREX: A DSL-based Approach to Adaptively Optimizing and Enforcing Extra-Functional Properties in High Performance Computing, in: Euromicro DSD/SEEA 2018, Prague, Czech Republic, August 2018, pp. 1-8.
    https://hal.inria.fr/hal-01890152
  • 29C. Silvano, G. Palermo, G. Agosta, A. H. Ashouri, D. Gadioli, S. Cherubin, E. Vitali, L. Benini, A. Bartolini, D. Cesarini, J. Cardoso, J. Bispo, P. Pinto, R. Nobre, E. Rohou, L. Besnard, I. Lasri, N. Sanna, C. Cavazzoni, R. Cmar, J. Martinovič, K. Slaninová, M. Golasowski, A. R. Beccari, C. Manelfi.
    Autotuning and Adaptivity in Energy Efficient HPC Systems: The ANTAREX Toolbox, in: CF 2018 - 15th ACM International Conference on Computing Frontiers, Ischia, Italy, ACM, May 2018, pp. 270-275. [ DOI : 10.1145/3203217.3205338 ]
    https://hal.inria.fr/hal-01932706

International Conferences with Proceedings

  • 30A. A. Ap, K. Le Bon, B. Hawkins, E. Rohou.
    FITTCHOOSER: A Dynamic Feedback-Based Fittest Optimization Chooser, in: HPCS 2018 - 16th International Conference on High Performance Computing & Simulation - Special Session on Compiler Architecture, Design and Optimization, Orléans, France, July 2018, pp. 1-8.
    https://hal.inria.fr/hal-01808658
  • 31R. Bouziane, E. Rohou, A. Gamatié.
    Compile-Time Silent-Store Elimination for Energy Efficiency: an Analytic Evaluation for Non-Volatile Cache Memory, in: RAPIDO: Rapid Simulation and Performance Evaluation, Manchester, United Kingdom, ACM, January 2018, pp. 1-8. [ DOI : 10.1145/3180665.3180666 ]
    https://hal.inria.fr/hal-01660686
  • 32R. Bouziane, E. Rohou, A. Gamatié.
    Energy-Efficient Memory Mappings based on Partial WCET Analysis and Multi-Retention Time STT-RAM, in: RTNS: Real-Time Networks and Systems, Poitiers, France, October 2018, pp. 148-158. [ DOI : 10.1145/3273905.3273908 ]
    https://hal.inria.fr/hal-01871320
  • 33T. Lefeuvre, E. K. Kasnakli, I. Fassi, I. Puaut, C. Cullmann, S. Derrien, G. Gebhard.
    Using Polyhedral Techniques to Tighten WCET Estimates of Optimized Code: A Case Study with Array Contraction, in: DATE 2018 - Design Automation and Test Europe, Dresden, Germany, IEEE, March 2018, pp. 925-930. [ DOI : 10.23919/DATE.2018.8342142 ]
    https://hal.inria.fr/hal-01815499
  • 34B. Panda, A. Seznec.
    Synergistic Cache Layout For Reuse and Compression, in: PACT ’18 - International conference on Parallel Architectures and Compilation Techniques, Limassol, Cyprus, November 2018, pp. 1-13. [ DOI : 10.1145/3243176.3243178 ]
    https://hal.inria.fr/hal-01888880
  • 36I. Puaut, M. Dardaillon, C. Cullmann, G. Gebhard, S. Derrien.
    Fine-Grain Iterative Compilation for WCET Estimation, in: WCET 2018 - 18th International Workshop on Worst-Case Execution Time Analysis, Barcelona, Spain, July 2018, pp. 1-12. [ DOI : 10.4230/OASIcs.WCET.2018.9 ]
    https://hal.inria.fr/hal-01889944
  • 37S. Rokicki, E. Rohou, S. Derrien.
    Supporting Runtime Reconfigurable VLIWs Cores Through Dynamic Binary Translation, in: DATE 2018 - IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition, Dresden, Germany, IEEE, March 2018, pp. 1009-1014. [ DOI : 10.23919/DATE.2018.8342160 ]
    https://hal.archives-ouvertes.fr/hal-01653110
  • 38S. Rokicki, E. Rohou, S. Derrien.
    Aggressive Memory Speculation in HW/SW Co-Designed Machines, in: DATE 2019 - IEEE/ACM Design, Automation and Test in Europe, Florence, Italy, March 2019.
    https://hal.archives-ouvertes.fr/hal-01941876
  • 40M. Y. Siraichi, V. F. d. Santos, S. Collange, F. M. Quintão Pereira.
    Qubit Allocation, in: CGO 2018 - International Symposium on Code Generation and Optimization, Vienna, Austria, February 2018, pp. 1-12. [ DOI : 10.1145/3168822 ]
    https://hal.archives-ouvertes.fr/hal-01655951

Conferences without Proceedings

  • 41R. Bouziane, E. Rohou, A. Gamatié.
    Partial Worst-Case Execution Time Analysis, in: ComPAS: Conférence en Parallélisme, Architecture et Système, Toulouse, France, July 2018, pp. 1-8.
    https://hal.inria.fr/hal-01803006

Other Publications

  • 42G. Berthou, A. Carer, H.-P. Charles, S. Derrien, K. Marquet, I. Miro-Panades, D. Pala, I. Puaut, F. Rastello, T. Risset, E. Rohou, G. Salagnac, O. Sentieys, B. Yarahmadi.
    The Inria ZEP project: NVRAM and Harvesting for Zero Power Computations, March 2018, 10th Annual Non-Volatile Memories Workshop (NVMW), Poster.
    https://hal.inria.fr/hal-01941766
References in notes
  • 43M. Hataba, A. El-Mahdy, E. Rohou.
    OJIT: A Novel Obfuscation Approach Using Standard Just-In-Time Compiler Transformations, in: International Workshop on Dynamic Compilation Everywhere, January 2015.
  • 44R. Kumar, D. M. Tullsen, N. P. Jouppi, P. Ranganathan.
    Heterogeneous chip multiprocessors, in: IEEE Computer, nov. 2005, vol. 38, no 11, pp. 32–38.
  • 45S. Nassif, N. Mehta, Y. Cao.
    A resilience roadmap, in: Design, Automation Test in Europe Conference Exhibition (DATE), 2010, March 2010, pp. 1011-1016.
  • 46R. Omar, A. El-Mahdy, E. Rohou.
    Arbitrary control-flow embedding into multiple threads for obfuscation: a preliminary complexity and performance analysis, in: Proceedings of the 2nd international workshop on Security in cloud computing, ACM, 2014, pp. 51–58.
  • 47B. Ransford, B. Lucia.
    Nonvolatile memory is a broken time machine, in: Proceedings of the workshop on Memory Systems Performance and Correctness, ACM, 2014, 5 p.
  • 48A. Seznec, N. Sendrier.
    HAVEGE: A user-level software heuristic for generating empirically strong random numbers, in: ACM Transactions on Modeling and Computer Simulation (TOMACS), 2003, vol. 13, no 4, pp. 334–346.
  • 49H. Wong, T. M. Aamodt.
    The Performance Potential for Single Application Heterogeneous Systems, in: 8th Workshop on Duplicating, Deconstructing, and Debunking, 2009.

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