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      <div class="TdmEntry">Overall Objectives<ul><li><a href="./uid3.html">Introduction</a></li><li><a href="./uid6.html">General Presentation</a></li><li class="tdmActPage"><a href="./uid11.html">Summary of Compsys I Achievements</a></li><li><a href="./uid17.html">Quick view of Compsys II
Achievements and directions for Compsys III</a></li><li><a href="./uid20.html">Highlights of the Year</a></li></ul></div>
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using Extremal Counter-Examples</a></li><li><a href="uid98.html&#10;&#9;&#9;  ">Data-Aware Process Networks</a></li><li><a href="uid107.html&#10;&#9;&#9;  ">Program Equivalence Modulo A/C (Associativity/Commutativity)</a></li><li><a href="uid110.html&#10;&#9;&#9;  ">Constant Aspect-Ratio Parametric Tiling</a></li><li><a href="uid111.html&#10;&#9;&#9;  ">Parametric Tiling with Inter-Tile
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        <h2>Section: 
      Overall Objectives</h2>
        <h3 class="titre3">Summary of Compsys I Achievements</h3>
        <p>The Compsys team has been evaluated by Inria for the first time in April
2007. The evaluation, conducted by Erik Hagersted (Uppsala University), Vinod
Kathail (Synfora, inc), J. (Ram) Ramanujam (Baton Rouge University) was
positive. Compsys I thus continued into Compsys II for 4-5 years but in
a new configuration as Tanguy Risset and Antoine Fraboulet left the project to
follow research directions closer to their host laboratory at Insa-Lyon. The main
achievements of Compsys I, for this period, were the following:</p>
        <ul>
          <li>
            <p class="notaparagraph"><a name="uid12"> </a>The development of a strong collaboration with the compilation group at
STMicroelectronics, with important results in aggressive optimizations for
instruction cache and register allocation.</p>
          </li>
          <li>
            <p class="notaparagraph"><a name="uid13"> </a>New results on the foundation of high-level program
transformations, including scheduling techniques for process networks
and a general technique for array contraction (memory reuse) based on the
theory of lattices.</p>
          </li>
          <li>
            <p class="notaparagraph"><a name="uid14"> </a>Many original contributions with partners closer to hardware constraints,
including CEA, related to SoC simulation, hardware/software interfaces, power
models, and simulators.</p>
          </li>
        </ul>
        <p>Due to Compsys size reduction (from 5 permanent researchers to 3 in 2008,
then 4 again in 2009), the team then focused, in Compsys II, on two research
directions only:</p>
        <ul>
          <li>
            <p class="notaparagraph"><a name="uid15"> </a>Code generation for embedded processors, on the two opposite, though
connected, aspects: aggressive compilation and just-in-time compilation.</p>
          </li>
          <li>
            <p class="notaparagraph"><a name="uid16"> </a>High-level program analysis and transformations for high-level synthesis
tools.</p>
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