Team Dreampal
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Bibliography

Publications of the year

Doctoral Dissertations and Habilitation Theses

  • 1G. Afonso.
    Vers une nouvelle génération de systèmes de test et de simulation avionique dynamiquement reconfigurables, Université des Sciences et Technologie de Lille - Lille I, July 2013.
    http://hal.inria.fr/tel-00921874
  • 2S. Kumar Rethinagiri.
    Une approche système pour l'estimation de la consommation de puissance des plateformes MPSoC, Université de Valenciennes et du Hainaut-Cambresis, March 2013.
    http://hal.inria.fr/tel-00921894
  • 3C. Trabelsi.
    Contrôle matériel des systèmes partiellement reconfigurables sur FPGA : de la modélisation à l'implémentation, Université des Sciences et Technologie de Lille - Lille I, July 2013.
    http://hal.inria.fr/tel-00852361

Articles in International Peer-Reviewed Journals

  • 4R. Ben Atitallah, E. Senn, D. Chillet, M. Lanoe, D. Blouin.
    An Efficient Framework for Power-Aware Design of Heterogeneous MPSoC, in: IEEE Transactions on Industrial Informatics, February 2013, vol. 9, no 1, pp. 487-501. [ DOI : 10.1109/TII.2012.2198657 ]
    http://hal.inria.fr/hal-00921900
  • 5S. Meftali, J.-L. Dekeyser, C. Trabelsi.
    Decentralized control for dynamically reconfigurable FPGA systems, in: Microprocessors and Microsystems, 2013.
    http://hal.inria.fr/hal-00922290
  • 6V. Rusu.
    Embedding domain-specific modeling languages into Maude specifications, in: Software and Systems Modeling, 2013, vol. 12, no 4, pp. 847-869. [ DOI : 10.1007/s10270-012-0232-5 ]
    http://hal.inria.fr/hal-00660104

International Conferences with Proceedings

  • 7G. Afonso, Z. Baklouti, D. Duvivier, R. Ben Atitallah, E. Billauer, S. Stilkerich.
    Heterogeneous CPU/FPGA reconfigurable computing system for avionic test application, in: IEEE 27th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), Cambridge, United Kingdom, May 2013.
    http://hal.inria.fr/hal-00922004
  • 8A. Ait El Cadi, R. Ben Atitallah, A. Artiba.
    Mathematical Programming Models for Scheduling in a CPU/FPGA Architecture with Communication Delay, in: IESM'2013 - International Conference on Industrial Engineering and Systems Management - 2013, Rabat, Morocco, October 2013.
    http://hal.inria.fr/hal-00922014
  • 9A. Arusoaie, D. Lucanu, V. Rusu.
    A Generic Framework for Symbolic Execution, in: 6th International Conference on Software Language Engineering, Indianapolis, United States, M. Erwig, R. Paige, E. Van Wyk (editors), Lecture Notes in Computer Science, Springer Verlag, August 2013, vol. LNCS 8225, pp. 281-301.
    http://hal.inria.fr/hal-00853588
  • 10Z. Baklouti, D. Duvivier, R. Ben Atitallah, A. Artiba, N. Belanger.
    Real-Time Simulator supporting Heterogeneous CPU/FPGA Architecture, in: International Conference on Industrial Engineering and Systems Management, Rabat, Morocco, October 2013.
    http://hal.inria.fr/hal-00922009
  • 11H. Krichene, M. Baklouti, J.-L. Dekeyser, P. Marquet, M. Abid.
    Master-Slave Control structure for massively parallel System on Chip, in: DSD SEAA - 16th Euromicro Conference on Digital System Design, Santander, Spain, 2013.
    http://hal.inria.fr/hal-00906906
  • 12D. Lucanu, V. Rusu.
    Program Equivalence by Circular Reasoning, in: Integrated Formal Methods, Turku, Finland, Lecture Notes in Computer Science, Springer, June 2013, vol. LNCS 7940, pp. 362-377.
    http://hal.inria.fr/hal-00820871

National Conferences with Proceedings

  • 13P. Wattebled, J.-P. Diguet.
    Méthodologie basée sur des membranes pour la gestion de la reconfiguration dynamique dans les systèmes embarqués parallèles, in: ComPAS, Grenoble, France, January 2013.
    http://hal.inria.fr/hal-00922289

Internal Reports


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