Team:DREAMPAL

Team Dreampal

Members

Overall Objectives

Executive Summary

Research Program

Application Domains

Software and Platforms

Software and Platforms

New Results

Language-Independent Symbolic Execution, Program Equivalence, and Program Verification
Master-Slave Control Structure for MP-SoC Architectures
Toward a Massively Parallel and Reflective Execution Model
Power Estimation at System-Level for MPSoC Based Platforms
Dynamically reconfigurable CPU/FPGA architecture for the testing and simulation of avionic systems
A custom reconfiguration controller for partial and dynamic reconfiguration in HoMade based systems
Hardware control for partially and dynamically reconfigurable systems: from modelling to implementation
A model-based approach for dynamically reconfigurable systems design: from MARTE to RecoMARTE

Bilateral Contracts and Grants with Industry

Partnerships and Cooperations

Dissemination

Bibliography

Publications of the year

Inria | Raweb 2013 | Presentation of the Team DREAMPAL | DREAMPAL Web Site


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2013 Team Activity Report

DREAMPAL

Dynamic Reconfigurable Massively Parallel Architectures and Languages

Research centre: Lille - Nord Europe

Field: Algorithmics, Programming, Software and Architecture
Theme: Architecture, Languages and Compilation

Keywords: Embedded Systems, Reconfigurable Hardware, Programming Languages, Formal Methods