Project-Team Dreampal
Members
Overall Objectives
Research Program
Highlights of the Year
New Software and Platforms
New Results
Bilateral Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
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Bibliography

Publications of the year

Articles in International Peer-Reviewed Journals

  • 1A. Ait El Cadi, O. Souissi, R. Ben Atitallah, N. Belanger, A. Artiba.
    Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays, in: Journal of Intelligent Manufacturing, April 2015, pp. 1-12. [ DOI : 10.1007/s10845-015-1075-z ]
    https://hal.inria.fr/hal-01247399
  • 2A. Arusoaie, D. Lucanu, V. Rusu.
    Symbolic execution based on language transformation, in: Computer Languages, Systems and Structures, 2015, 42 p. [ DOI : 10.1016/j.cl.2015.08.004 ]
    https://hal.inria.fr/hal-01186008
  • 3M. Baklouti, P. Marquet, J.-L. Dekeyser, M. Abid.
    FPGA-based many-core System-on-Chip design, in: Microprocessors and Microsystems, 2015, 38 p. [ DOI : 10.1016/j.micpro.2015.03.007 ]
    https://hal.inria.fr/hal-01144977
  • 4S. Ciobaca, D. Lucanu, V. Rusu, G. Rosu.
    A Language-Independent Proof System for Mutual Program Equivalence, in: Formal Aspects of Computing, 2016, forthcoming.
    https://hal.inria.fr/hal-01245528
  • 5H. Krichene, M. Baklouti, M. Abid, P. Marquet, J.-L. Dekeyser.
    G-MPSoC: Generic Massively Parallel Architecture on FPGA, in: WSEAS Transactions on Circuits and Systems, November 2015, vol. 14.
    https://hal.inria.fr/hal-01246675
  • 6D. Lucanu, V. Rusu, A. Arusoaie.
    A Generic Framework for Symbolic Execution: Theory and Applications, in: Journal of Symbolic Computation, 2016, forthcoming.
    https://hal.inria.fr/hal-01238696
  • 7D. Lucanu, V. Rusu.
    Program Equivalence by Circular Reasoning, in: Formal Aspects of Computing, 2015, vol. 27, no 4, pp. 701-726. [ DOI : 10.1007/s00165-014-0319-6 ]
    https://hal.inria.fr/hal-01065830
  • 8J. Perier, W. Chouchene, J.-L. Dekeyser.
    Circuit Merging versus Dynamic Partial Reconfiguration -The HoMade Implementation, in: i-manager's Journal on Embedded Systems(JES), 2016.
    https://hal.inria.fr/hal-01245800
  • 9V. Rusu, D. Lucanu, T.-F. Şerbănuţă, A. Arusoaie, A. Ştefănescu, G. Roşu.
    Language Definitions as Rewrite Theories, in: Journal of Logic and Algebraic Methods in Programming, 2015, 48 p, forthcoming. [ DOI : 10.1016/j.jlamp.2015.09.001 ]
    https://hal.inria.fr/hal-01186005

Invited Conferences

  • 10D. Lucanu, V. Rusu, A. Arusoaie, D. Nowak.
    Verifying Reachability-Logic Properties on Rewriting-Logic Specifications, in: Logic, Rewriting, and Concurrency - Festschrift Symposium in Honor of José Meseguer, Urbana Champaign, United States, Logic, Rewriting, and Concurrency Essays Dedicated to José Meseguer on the Occasion of His 65th Birthday, Springer Verlag, September 2015, vol. 9200. [ DOI : 10.1007/978-3-319-23165-5_21 ]
    https://hal.inria.fr/hal-01158941

International Conferences with Proceedings

  • 11S. Ciobaca, D. Lucanu, V. Rusu, G. Rosu.
    A Theoretical Foundation for Programming Languages Aggregation, in: 22nd International Workshop on Algebraic Development Techniques, Sinaia, Romania, LNCS, Spriger Verlag, 2015, vol. 9463.
    https://hal.inria.fr/hal-01076641

Conferences without Proceedings

  • 12K. M. A. Ali, R. B. Atitallah, N. Fakhfakh, J.-L. Dekeyser.
    Using hardware parallelism for reducing power consumption in video streaming applications, in: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015, Bremen, Germany, June 2015. [ DOI : 10.1109/ReCoSoC.2015.7238104 ]
    https://hal.inria.fr/hal-01247130
  • 13J.-L. Dekeyser, A. S. Aljendi.
    Adopting New Learning Strategies for Computer Architecture in Higher Education Case Study: Building the S3 Microprocessor in 24 Hours, in: Workshop on Computer Architecture Education held in conjunction with the 42nd International Symposium on Computer Architeture, Portland, United States, June 2015.
    https://hal.inria.fr/hal-01152144
  • 14H. Krichene, M. Baklouti, M. Abid, P. Marquet, J.-L. Dekeyser, S. Meftali.
    SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively parallel SoC, in: The 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, Heraklion, Greece, February 2016.
    https://hal.inria.fr/hal-01247298
  • 15V. Viswanathan, R. B. Atitallah, J.-L. Dekeyser.
    Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System , in: IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2015, Vancouver, BC , Canada, May 2015. [ DOI : 10.1109/FCCM.2015.13 ]
    https://hal.inria.fr/hal-01247116
  • 16V. Viswanathan, R. Ben Atitallah, J.-L. Dekeyser, B. Nakache, M. Nakache.
    A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications, in: The 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '15, Monterey, California, United States, February 2015. [ DOI : 10.1145/2684746.2689115 ]
    https://hal.inria.fr/hal-01247133

Internal Reports

  • 17A. Arusoaie, D. Lucanu, V. Rusu.
    A Generic Framework for Symbolic Execution: Theory and Applications, Inria, September 2015, no RR-8189, 41 p.
    https://hal.inria.fr/hal-00766220
  • 18A. Arusoaie, D. Nowak, V. Rusu, D. Lucanu.
    Formal Proof of Soundness for an RL Prover, Inria Lille - Nord Europe ; Alexandru Ioan Cuza, University of Iasi, December 2015, no RR-471, 27 p.
    https://hal.inria.fr/hal-01244578
  • 19J. Forget, F. Guyomarch, V. Rusu.
    Programming with hardware/software functions, Inria Lille Nord Europe, December 2015, no 8835, 18 p.
    https://hal.inria.fr/hal-01248163

Patents


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