Bibliography

Publications of the year

Doctoral Dissertations and Habilitation Theses

• 1C. Alias.
  Contributions to Program Optimization and High-Level Synthesis, ENS de Lyon, May 2019, Habilitation à diriger des recherches.
  https://hal.inria.fr/tel-02151877

Articles in International Peer-Reviewed Journals

• 2W. Ahrendt, L. Henrio, W. Oortwijn.
  Who is to Blame? Runtime Verification of Distributed Objects with Active Monitors, in: Electronic Proceedings in Theoretical Computer Science, August 2019, vol. 302, pp. 32-46, https://arxiv.org/abs/1908.10042 - In Proceedings VORTEX 2018, arXiv:1908.09302. [ DOI : 10.4204/EPTCS.302.3 ]
  https://hal.archives-ouvertes.fr/hal-02303148
• 3L. Henrio, C. Kessler, L. Li.
  Leveraging access mode declarations in a model for memory consistency in heterogeneous systems, in: Journal of Logical and Algebraic Methods in Programming, January 2020, vol. 110, pp. 1-17, 100498, https://arxiv.org/abs/1910.11110. [ DOI : 10.1016/j.jlamp.2019.100498 ]
  https://hal.archives-ouvertes.fr/hal-02331964

International Conferences with Proceedings

• 4C. Alias.
  fkcc: the Farkas Calculator, in: 10th Workshop on Tools for Automatic Program Analysis, Porto, Portugal, Lecture Notes in Computer Science, Springer, December 2019.
  https://hal.inria.fr/hal-02414224
• 6S. Bliudze, L. Henrio, E. Madelaine.
  Verification of concurrent design patterns with data, in: 21th International Conference on Coordination Languages and Models (COORDINATION), Kongens Lyngby, Denmark, H. R. Nielson, E. Tuosto (editors), Coordination Models and Languages, Springer International Publishing, 2019, vol. LNCS-11533, pp. 161-181, t Part 4: Coordination Patterns. [ DOI : 10.1007/978-3-030-22397-7_10 ]
  https://hal.archives-ouvertes.fr/hal-02143782
• 7G. Busnot, T. Sassolas, N. Ventroux, M. Moy.
  Standard-compliant Parallel SystemC simulation of Loosely-Timed Transaction Level Models, in: 25th Asia and South Pacific Design Automation Conference (ASP-DAC 2020), Beijing, China, January 2020.
  https://hal.archives-ouvertes.fr/hal-02416253
• 9M. Dupont De Dinechin, M. Schuh, M. Moy, C. Maïza.
  Scaling Up the Memory Interference Analysis for Hard Real-Time Many-Core Systems, in: Design, Automation and Test in Europe Conference (DATE), Grenoble, France, March 2020.
  https://hal.archives-ouvertes.fr/hal-02431273
• 10K. Fernandez-Reyes, D. Clarke, L. Henrio, E. Broch Johnsen, T. Wrigstad.
  Godot: All the Benefits of Implicit and Explicit Futures, in: ECOOP 2019 - 33rd European Conference on Object-Oriented Programming, London, Royume-Uni, Leibniz International Proceedings in Informatics (LIPIcs), 2019, pp. 1-28.
  https://hal.archives-ouvertes.fr/hal-02302214
• 11Z. Ganjei, A. Rezine, L. Henrio, P. Eles, Z. Peng.
  On Reachability in Parameterized Phaser Programs, in: TACAS 2019 - 25th International Conference on Tools and Algorithms for the Construction and Analysis of Systems, Prague, Czech Republic, LNCS, Springer, April 2019, vol. 11427, pp. 299-315, https://arxiv.org/abs/1811.07142. [ DOI : 10.1007/978-3-030-17462-0_17 ]
  https://hal.archives-ouvertes.fr/hal-02061520
• 12P. Leca, L. Henrio, F. Baude, W. Suijlen.
  Distributed futures for efficient data transfer between parallel processes, in: The 35th ACM/SIGAPP Symposium On Applied Computing, Brno, Czech Republic, March 2020. [ DOI : 10.1145/3341105.3373932 ]
  https://hal.archives-ouvertes.fr/hal-02417953

Conferences without Proceedings

• 13C. Alias.
  Farkas Lemma made easy, in: IMPACT 2020 - 10th International Workshop on Polyhedral Compilation Techniques, Bologna, Italy, December 2019, pp. 1-6.
  https://hal.inria.fr/hal-02422033
• 14A. Graillat, C. Maiza, M. Moy, P. Raymond, B. Dupont De Dinechin.
  Response Time Analysis of Dataflow Applications on a Many-Core Processor with Shared-Memory and Network-on-Chip, in: RTNS 2019 - 27th International Conference on Real-Time Networks and Systems, Toulouse, France, ACM, November 2019, pp. 61-69. [ DOI : 10.1145/3356401.3356416 ]
  https://hal.archives-ouvertes.fr/hal-02320463

Internal Reports

• 15C. Alias, J. Rudeau.
  Pipeline-aware Scheduling of Polyhedral Process Networks, Inria Grenoble - Rhone-Alpes, December 2019, n^o RR-9314.
  https://hal.inria.fr/hal-02414340
• 16C. Alias, S. Thibault, L. Gonnord.
  A Compiler Algorithm to Guide Runtime Scheduling, Inria Grenoble ; Inria Bordeaux - Sud-Ouest, December 2019, n^o RR-9315.
  https://hal.inria.fr/hal-02421327

Scientific Popularization

• 17L. Henrio.
  Pourquoi créer des nouveaux langages de programmation ?, in: Interstices, January 2019.
  https://hal.inria.fr/hal-02008111

Other Publications

• 18C. Alias.
  On Channel Restructuring for Complete FIFO Recovery, November 2019, ICCD 2019 - 37th IEEE International Conference on Computer Design, Poster.
  https://hal.inria.fr/hal-02433318

References in notes

• 19IEEE 1666 Standard: SystemC Language Reference Manual, Open SystemC Initiative, 2011.
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• 20OSCI TLM-2.0 Language Reference Manual, Open SystemC Initiative (OSCI), June 2008.
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• 21C. Alias, A. Darte, P. Feautrier, L. Gonnord.
  Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs, in: International Static Analysis Symposium (SAS'10), 2010.
• 22C. Alias, A. Plesco.
  Method of Automatic Synthesis of Circuits, Device and Computer Program associated therewith, April 2014, Patent FR1453308.
• 23C. Alias, A. Plesco.
  Data-aware Process Networks, Inria - Research Centre Grenoble – Rhône-Alpes, June 2015, n^o RR-8735, 32 p.
  https://hal.inria.fr/hal-01158726
• 24C. Alias, A. Plesco.
  Optimizing Affine Control with Semantic Factorizations, in: ACM Transactions on Architecture and Code Optimization (TACO) , December 2017, vol. 14, n^o 4, 27 p.
• 25I. Amer, C. Lucarz, G. Roquier, M. Mattavelli, M. Raulet, J.-F. Nezan, O. Deforges.
  Reconfigurable video coding on multicore, in: Signal Processing Magazine, IEEE, 2009, vol. 26, n^o 6, pp. 113–123.
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• 26S. Ananian.
  The Static Single Information Form, MIT, September 1999.
• 27C. B. Aoun, L. Andrade, T. Maehne, F. Pêcheux, M.-M. Louërat, A. Vachouxy.
  Pre-simulation elaboration of heterogeneous systems: The SystemC multi-disciplinary virtual prototyping approach, in: Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015 International Conference on, IEEE, 2015, pp. 278–285.
• 28D. Becker, M. Moy, J. Cornet.
  Parallel Simulation of Loosely Timed SystemC/TLM Programs: Challenges Raised by an Industrial Case Study, in: MDPI Electronics, 2016, vol. 5, n^o 2, 22 p. [ DOI : 10.3390/electronics5020022 ]
  https://hal.archives-ouvertes.fr/hal-01321055
• 29N. Bjørner, K. McMillan, A. Rybalchenko.
  On Solving Universally Quantified Horn Clauses, in: Static Analysis: 20th International Symposium, SAS 2013, Seattle, WA, USA, June 20-22, 2013. Proceedings, Berlin, Heidelberg, F. Logozzo, M. Fähndrich (editors), Springer Berlin Heidelberg, 2013, pp. 105–125.
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• 30D. Caromel, L. Henrio.
  A Theory of Distributed Objects, Springer-Verlag, 2004.
• 31P. Cousot, R. Cousot.
  Abstract interpretation: A unified lattice model for static analysis of programs by construction or approximation of fixpoints, in: 4th ACM Symposium on Principles of Programming Languages (POPL'77), Los Angeles, January 1977, pp. 238-252.
• 32F. De Boer, V. Serbanescu, R. Hähnle, L. Henrio, J. Rochas, C. C. Din, E. Broch Johnsen, M. Sirjani, E. Khamespanah, K. Fernandez-Reyes, A. M. Yang.
  A Survey of Active Object Languages, in: ACM Comput. Surv., October 2017, vol. 50, n^o 5, pp. 76:1–76:39.
  http://doi.acm.org/10.1145/3122848
• 33M. Duranton, D. Black-Schaffer, K. De Bosschere, J. Maebe.
  The HIPEAC VISION FOR ADVANCED COMPUTING IN HORIZON 2020, https://www.hipeac.net/v13, 2013.
  https://www.hipeac.net/v13
• 34P. Feautrier.
  Scalable and Structured Scheduling, in: International Journal of Parallel Programming, October 2006, vol. 34, n^o 5, pp. 459–487.
• 35P. Feautrier.
  Dataflow analysis of array and scalar references, in: International Journal of Parallel Programming, 1991, vol. 20, n^o 1, pp. 23–53.
• 36P. Feautrier, A. Gamatié, L. Gonnord.
  Enhancing the Compilation of Synchronous Dataflow Programs with a Combined Numerical-Boolean Abstraction, in: CSI Journal of Computing, 2012, vol. 1, n^o 4, pp. 8:86–8:99.
  http://hal.inria.fr/hal-00860785
• 37K. Fernandez-Reyes, D. Clarke, E. Castegren, H.-P. Vo.
  Forward to a Promising Future, in: Conference proceedings COORDINATION 2018, 2018.
• 38R. Fontaine, L. Gonnord, L. Morel.
  Polyhedral Dataflow Programming: a Case Study, in: SBAC-PAD 2018 - 30th International Symposium on Computer Architecture and High-Performance Computing, Lyon, France, IEEE, September 2018, pp. 1-9.
  https://hal-cea.archives-ouvertes.fr/cea-01855997
• 39L. Gonnord, P. Iannetta, L. Morel.
  Semantic Polyhedral Model for Arrays and Lists, Inria Grenoble Rhône-Alpes ; UCBL ; LIP - ENS Lyon ; CEA List, June 2018, n^o RR-9183.
  https://hal.archives-ouvertes.fr/hal-01815759
• 40M. I. Gordon.
  Compiler techniques for scalable performance of stream programs on multicore architectures, Massachusetts Institute of Technology. Dept. of Electrical Engineering and Computer Science, 2010.
• 41O. Hakjoo, L. Wonchan, H. Kihong, Y. Hongseok, Y. Kwangkeun.
  Selective context-sensitivity guided by impact pre-analysis, in: ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI '14, Edinburgh, United Kingdom - June 09 - 11, 2014, ACM, 2014, 49 p.
• 42N. Halbwachs, P. Caspi, P. Raymond, D. Pilaud.
  The synchronous data flow programming language LUSTRE, in: Proceedings of the IEEE, Sep 1991, vol. 79, n^o 9, pp. 1305-1320.
• 43L. Henrio.
  Data-flow Explicit Futures, I3S, Université Côte d'Azur, April 2018.
  https://hal.archives-ouvertes.fr/hal-01758734
• 44P. Iannetta, L. Gonnord, L. Morel, T. Yuki.
  Semantic Array Dataflow Analysis, Inria Grenoble Rhône-Alpes, December 2018, n^o RR-9232, pp. 1-22.
  https://hal.archives-ouvertes.fr/hal-01954396
• 45G. Kahn.
  The semantics of a simple language for parallel programming, in: Information processing, North-Holland, 1974.
• 46M. Maalej, V. Paisante, P. Ramos, L. Gonnord, F. Pereira.
  Pointer Disambiguation via Strict Inequalities, in: Code Generation and Optimisation, Austin, United States, February 2017.
  https://hal.archives-ouvertes.fr/hal-01387031
• 47M. Maalej Kammoun.
  Low-cost memory analyses for efficient compilers, Université Lyon 1, 2017, Thèse de doctorat, Université Lyon1.
  http://www.theses.fr/2017LYSE1167
• 48D. Monniaux, L. Gonnord.
  Cell morphing: from array programs to array-free Horn clauses, in: 23rd Static Analysis Symposium (SAS 2016), Edimbourg, United Kingdom, X. Rival (editor), Static Analysis Symposium, September 2016.
  https://hal.archives-ouvertes.fr/hal-01206882
• 49M. Moy.
  Parallel Programming with SystemC for Loosely Timed Models: A Non-Intrusive Approach, in: DATE, Grenoble, France, March 2013, 9 p.
  https://hal.archives-ouvertes.fr/hal-00761047
• 50V. Paisante, M. Maalej, L. Barbosa, L. Gonnord, F. M. Q. Pereira.
  Symbolic Range Analysis of Pointers, in: International Symposium of Code Generation and Optmization, Barcelon, Spain, March 2016, pp. 791-809.
  https://hal.inria.fr/hal-01228928
• 51A. Plesco.
  Program Transformations and Memory Architecture Optimizations for High-Level Synthesis of Hardware Accelerators, Ecole normale supérieure de lyon - ENS LYON, September 2010.
  https://tel.archives-ouvertes.fr/tel-00544349
• 52P. Quinton.
  Automatic synthesis of systolic arrays from uniform recurrent equations, in: ACM SIGARCH Computer Architecture News, 1984, vol. 12, n^o 3, pp. 208–214.
• 53H. Rihani, M. Moy, C. Maïza, R. I. Davis, S. Altmeyer.
  Response Time Analysis of Synchronous Data Flow Programs on a Many-Core Processor, in: Proceedings of the 24th International Conference on Real-Time Networks and Systems, New York, NY, USA, RTNS '16, ACM, 2016, pp. 67–76.
  http://doi.acm.org/10.1145/2997465.2997472
• 54H. N. W. Santos, I. Maffra, L. Oliveira, F. Pereira, L. Gonnord.
  Validation of Memory Accesses Through Symbolic Analyses, in: Proceedings of the 2014 ACM International Conference on Object Oriented Programming Systems Languages And Applications (OOPSLA'14), Portland, Oregon, United States, October 2014.
  http://hal.inria.fr/hal-01006209
• 55W. Thies.
  Language and compiler support for stream programs, Massachusetts Institute of Technology, 2009.
• 56A. Turjan.
  Compiling Nested Loop Programs to Process Networks, Universiteit Leiden, 2007.
• 57N. Ventroux, T. Sassolas.
  A new parallel SystemC kernel leveraging manycore architectures, in: Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, IEEE, 2016, pp. 487–492.
• 58S. Verdoolaege.
  Polyhedral Process Networks, Handbook of Signal Processing Systems, Springer, 2010, pp. 931–965.
• 59S. Williams, A. Waterman, D. Patterson.
  Roofline: an insightful visual performance model for multicore architectures, in: Communications of the ACM, 2009, vol. 52, n^o 4, pp. 65–76.
• 60B. da Silva, A. Braeken, E. H. D'Hollander, A. Touhafi.
  Performance modeling for FPGAs: extending the roofline model with high-level synthesis tools, in: International Journal of Reconfigurable Computing, 2013, vol. 2013, 7 p.