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CAIRN - 2011
CAIRN - 2011


Project Team Cairn


Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography


Project Team Cairn


Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography




Section: Dissemination

Teaching and Responsibilities

Teaching Responsibilities

There is a strong teaching activity in the Cairn team since most of the permanent members are Professors or Associate Professors.

 

C. Wolinski is the Director of Esir since March 2011.

P. Quinton is the deputy-director of Ecole Normale Supérieure de Cachan, responsible of the Brittany branch of this school.

E. Casseau is the Director of Academic Studies of Enssat .

D. Chillet is the Head of the Electronics Engineering department of Enssat .

O. Sentieys is responsible of the ”Embedded Systems” branch of the SISEA Master of Research (M2R).

 

Enssat stands for ”École Nationale Supérieure des Sciences Appliquées et de Technologie” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Lannion.

ISTIC is the Electrical Engineering and Computer Science Department of the University of Rennes 1.

Esir (formerly DIIC) stands for ”École supérieure d'ingénieur de Rennes” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Rennes.

M2R stands for Master by Research, second year.

 

D. Chillet is member of the French National University Council since 2009 in signal processing and electronics (Conseil National des Universités en 61ème section).

D. Chillet is member of the Permanent Committee of the French National University Council since november 2011 in signal processing and electronics (Commission Permanente du Conseil National des Universités en 61ème section).

Teaching

  • O. Berder: introduction to signal processing, 38h, Enssat (L3)

  • O. Berder: microprocessors and digital systems, 19h, Enssat (L3)

  • O. Berder: wireless communications, 23h, Enssat (M2)

  • O. Berder: digital signal processing, 60h, Enssat (M1)

  • O. Berder: ad hoc networks, 58h, Enssat (M1-M2)

  • O. Berder: signal processing, 24h, IUT Lannion (L2)

  • E. Casseau: verification, 12h, Master by Research and Enssat (M2)

  • E. Casseau: high-level synthesis, 3h, Enssat (M2)

  • E. Casseau: hardware description language, 24h, Enssat (M1)

  • E. Casseau: design methodology of real-time systems, 24h, Enssat (M1)

  • E. Casseau: verification, 4h, ENSEIRB (M1)

  • E. Casseau: signal processing, 16h, Enssat (L3)

  • F. Charot: specification of applications with the signal synchronous language, 24h, Esir (M1)

  • F. Charot: virtual prototyping of multiprocessor system-on-chip, 48h, Esir (M1, M2)

  • D. Chillet: advanced processors architectures, 24h, Master by Research and Enssat (M2)

  • D. Chillet: low-power digital CMOS circuits, 6h, Telecom Bretagne and University of Occidental Brittany (UBO) (M2)

  • D. Menard: embedded software for signal processing, 14 h, Master by Research and Enssat (M2)

  • D. Menard: embedded systems, 18 h, Enssat (M1)

  • D. Menard: digital signal processors, 20 h, Enssat (M1)

  • D. Menard: digital systems, 38 h, Enssat (L3)

  • D. Menard: embedded processors, 40 h, Enssat (L3)

  • S. Pillement: embedded microprocessors, 28h, Enssat (M2)

  • S. Pillement: initiation to electronic system integration, 12h, Enssat (L3)

  • S. Pillement: computer architecture, 61h, IUT Lannion (L2)

  • S. Pillement: data acquisition, 21h, IUT Lannion (L2)

  • S. Pillement: micro-controller programming, 30h, IUT Lannion (L1)

  • S. Pillement: digital electronics, 43h, IUT Lannion (L1)

  • R. Rocher: electricity, 16h, IUT Lannion (L1)

  • R. Rocher: electronics, 56h, IUT Lannion (L1)

  • R. Rocher: telecommunications, 94h, IUT Lannion (L1)

  • R. Rocher: signal processing, 12h, IUT Lannion (L2)

  • R. Rocher: digital communications, 56h, IUT Lannion (L2)

  • O. Sentieys: methodologies for system-on-chip design, 6h, Master by Research and Enssat (M2)

  • O. Sentieys: VLSI integrated circuit design, 66h, Enssat (M1)

  • O. Sentieys: high-level synthesis of digital signal processors, 16h, Master by Research and Enssat (M2)

  • A. Tisserand: GPU programming, 6h, Enssat (M2)

  • A. Tisserand: hardware computer arithmetic operators, 6h, Master by Research, Univ. Rennes 1 (M2)

  • A. Tisserand: computer arithmetic, 12h, ENS Cachan, Antenne de Bretagne, Magister Computer Science and Telecommunications (L3)

  • C. Wolinski: architecture 1, 64h, Esir (L3)

  • C. Wolinski: architecture 2, 28h, Esir (L3)

  • C. Wolinski: design of Embedded Systems, 48h, Esir (M1)

  • C. Wolinski: signal, image, architecture, 26h, Esir (M1)

  • C. Wolinski: programmable architectures, 10h, Esir (M1)

  • C. Wolinski: component and system synthesis, 10h, Master by Research (MRI ISTIC) (M2)

HDR and PhD

  • HDR: Daniel Menard, Contributions à la conception de systèmes en virgule fixe, Habilitation à Diriger des Recherches, University of Rennes 1, Nov. 2011.

  • HDR: Steven Derrien, Contributions à la conception d'architectures matérielles dédiées, Habilitation à Diriger des Recherches, University of Rennes 1, Dec. 2011.

  • PhD: Erwan Raffin, Déploiement d'applications multimédia sur architecture reconfigurable à gros grain : modélisation avec la programmation par contraintes, University of Rennes 1, Jul. 2011, C. Wolinski, F. Charot.

  • PhD: Ludovic Devaux, Réseaux d'interconnexion flexibles pour architectures reconfigurables dynamiquement, University of Rennes 1, Nov. 2011, S. Pillement, D. Demigny.

  • PhD: Hai-Nam Nguyen, Optimisation de la précision de calcul pour la réduction d'énergie des systèmes embarqués, University of Rennes 1, Dec. 2011, D. Menard, O. Sentieys.

  • PhD in progress: Naeem Abbas, Flexible Hardware Accelerators for Biocomputing Applications, Jan. 2009, P. Quinton, S. Derrien

  • PhD in progress: Mahtab Alam, Power Aware Signal Processing for Reconfigurable Radios in the context of Wireless Sensor Networks, Nov. 2009, O. Sentieys, O. Berder, D. Menard

  • PhD in progress: Andrei Banciu, New Digital Design Methodology for Multi Giga bits/s Tranceivers, Oct. 2008, E. Casseau, D. Menard

  • PhD in progress: Karim Bigou, RNS Hardware Units for ECC, Oct. 2011, A. Tisserand

  • PhD in progress: Robin Bonamy, Power Consumption Modelling and Optimisation for Reconfigurable Platform, Oct. 2009, D. Chillet

  • PhD in progress: Franck Bucheron, Secure Virtualization for Embedded Systems, Oct. 2011, A. Tisserand

  • PhD in progress: Thomas Chabrier, Reconfigurable Arithmetic Units for Cryptoprocessors with Protection against Side Channel Attacks, Oct. 2009, A. Tisserand, E. Casseau

  • PhD in progress: Aymen Chakhari, Analytical approach for decision errors in fixed-point digital communication systems, Oct. 2010, R. Rocher, P. Scalart

  • PhD in progress: Antoine Eiche, Real-Time Scheduling for Heterogeneous and Reconfigurable Architectures using Neural Network Structures, Oct. 2009, D. Chillet, S. Pillement

  • PhD in progress: Antoine Floch, Pattern Recognition for Processor Instruction-Set Extension, Jan. 2009, C. Wolinski, F. Charot

  • PhD in progress: Clément Guy, Generic Definition of Domain Specific Analysis using MDE, Oct. 2010, S. Derrien, jointly with J.M. Jezequel and B. Combemale from Triskell EPI

  • Trong-Nhan Le, Global power management system for self-powered autonomous wireless sensor nodes, Jan. 2011, O. Sentieys, O. Berder

  • PhD in progress: Antoine Morvan, Loop Transformations for Design Space Exploration in High-Level Synthesis, Oct. 2009, P. Quinton, S. Derrien

  • PhD in progress: Jean-Charles Naud, Source-to-Source Code Transformation for Fixed-Point Conversion, Oct. 2009, D. Menard

  • PhD in progress: Quoc-Tuong Ngo, Optimization of Precoding Strategies for Multi-User MIMO-OFDM Systems, Oct. 2008, P. Scalart, O. Berder

  • PhD in progress: Cécile Beaumin, Reconfigurable Architecture for High-Performance Video Transcoding, Oct. 2008, O. Sentieys, E. Casseau

  • PhD in progress: Karthick Parashar, System-level Approach for Implementation and Optimization of Signal Processing Applications into Fixed-Point Architectures, Oct. 2008, O. Sentieys, D. Menard

  • PhD in progress: Danuta Pamula, Arithmetic Operators for Cryptography, Oct. 2009, A. Tisserand

  • PhD in progress: Matthieu Texier, Low-Power Embedded Multi-Core Architectures for Mobile Systems, Oct. 2009, O. Sentieys, jointly with R. David from CEA List

  • PhD in progress: Michel Theriault, Transmit Beam-forming for Distributed Wireless Access with Centralized Signal Processing, Oct. 2007, O. Sentieys, jointly with S. Roy from U. Laval, Canada

  • PhD in progress: Vivek Dwarakanath-Tovinakere, Ultra-Low Power Reconfigurable Controllers for Wireless Sensor Networks, Oct. 2009, O. Sentieys

  • PhD in progress: Le Quang Vinh Tran, Energy Optimisation of Cooperative Transmissions for Wireless Sensor Networks, Oct. 2009, O. Berder, O. Sentieys

  • Ganda-Stéphane Ouedraogo, Automatic synthesis of hardware accalerator from high-level specifications in flexible radios, Oct. 2011, M. Gautier, O. Sentieys

  • PhD in progress: Pramod Udupa, Sampling, synchronising, digital processing and FPGA implementation of 100Gbps optical OFDM signals, Jan. 2011, O. Sentieys

  • PhD in progress: Chenglong Xiao, Pattern-Based Guided High-Level Synthesis, Oct. 2009, E. Casseau

  • PhD in progress: Hervé Yviquel, Video coding design framework based on SoC-based platforms, Oct. 2010, E. Casseau