Section: Partnerships and Cooperations
Pôle de compétitivité Minalogic/ARAVIS
ARAVIS (Architecture reconfigurable et asynchrone intégrée sur puce) is a project sponsored by the Minalogic Pole, started in October 2007 for 3 years (http://www.minalogic.com/PAR_TPL_IDENTIFIANT/903/TPL_CODE/TPL_PROJET/31-recherche.htm ). The project has been extended to december 2011. The innovation key deals with bringing architecture and design solutions to calculation platform problems for embedded systems at the 32-nm and 22-nm scales by combining three core technologies: - ST’s DSPfacbric coarse-grain structure, which aims to implement several dozen identical data paths on the same System-on-Chip (SoC) and to reconfigure them according to the needs of the application - Techniques based on asynchronous logic (in other words, without a clock) to resolve issues arising from the variability of physical characteristics within each processing node - Advanced automatic techniques for dynamic power and activity management according to oftencontradictory demands such as low voltage and calculation power. The project is headed by STMicroelectronics, the other partners are CEA-Leti, TIMA laboratory and the Sardes and NeCS teams at Inria . Previous works on a high-performance controller development for a novel discrete DVS converter were done within this project  .