Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
- Logical time in Model-Driven Engineering embedded design
- Semantic translation of CCSL constraints into appropriate Büchi automata for trace recognition
- Timing refinement for multidimensional dataflow models using MARTE Time Model
- Process Network analysis
- Transformation from MARTE Time Model and CCSL to formal analysis models
- Use of MARTE Time Model and Logical Time in automotive design and AUTOSAR/TADL
- Multiview modeling and power intent in Systems-on-chip
- Correct and efficient implementation of polychronous formalisms
- Programmable On-Chip Networks
- Uniprocessor Real-Time Scheduling
- Multiprocessor Real-Time Scheduling
- Variability of program execution times on multicore processors
Bilateral Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
- Logical time in Model-Driven Engineering embedded design
- Semantic translation of CCSL constraints into appropriate Büchi automata for trace recognition
- Timing refinement for multidimensional dataflow models using MARTE Time Model
- Process Network analysis
- Transformation from MARTE Time Model and CCSL to formal analysis models
- Use of MARTE Time Model and Logical Time in automotive design and AUTOSAR/TADL
- Multiview modeling and power intent in Systems-on-chip
- Correct and efficient implementation of polychronous formalisms
- Programmable On-Chip Networks
- Uniprocessor Real-Time Scheduling
- Multiprocessor Real-Time Scheduling
- Variability of program execution times on multicore processors
Bilateral Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography
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