Section: Partnerships and Cooperations

Regional Initiatives

Function field sieve: implementation and hardware acceleration

Participants : Jérémie Detrey [contact] , Pierrick Gaudry, Hamza Jeljeli, Vlad-Cristian Miclea, Emmanuel Thomé.

The team has obtained for the years 2012 and 2013 a financial support from the Région Lorraine and Inria for a project focusing on the hardware implementation and acceleration of the function field sieve (FFS).

The FFS algorithm is currently the best known method to compute discrete logarithms in small-characteristic finite fields, such as may occur in pairing-based cryptosystems. Its study is therefore crucial to accurately assess the key-lengths which such cryptosystems should use. More precisely, this project aims at quantifying how much this algorithm can benefit from recent hardware technologies such as GPUs or CPU-embedded FPGAs, and how this might impact current key length recommendations.

The funding obtained was used to buy an FPGA ML-605 development board, on which Vlad-Cristian Miclea implemented operators for polynomial arithmetic in characteristic two and three during his internship; along with a GeForce GTX 580 graphics card, on which Hamza Jeljeli developed a GPU-based implementation of sparse linear algebra routines for solving discrete-logarithm problems [16] .