## Section: Research Program

### Hardware and FPGA arithmetic

The main characteristic of reconfigurable circuits, or FPGAs, is precisely their reconfigurability: the circuit implemented in an FPGA can be changed according to the needs of the target applications. The challenge here is to exploit this reconfigurability to design operators specifically for the applications: not only should their low-level architecture match the peculiar metrics of FPGAs, but also, the high-level architecture, and even the operator specifications should be as application-specific as possible, and probably completely different to what we are used to design into VLSI circuits. Indeed, operators that would make no economical sense in a processor make perfect sense in an FPGA if an application requires them.

Exotic operators worth considering include specialized operators (such as a multiplier by a constant, a squarer, etc.), arbitrary numerical functions, fused operators such as the Euclidean norm $\sqrt{{x}^{2}+{y}^{2}}$, etc. The list is infinite, and exploring it is the purpose of the FloPoCo operator generator project started in 2008 (see Section 5.2 ). We plan to extend it to support many more operators, starting with a fully featured mathematical library.

To support this research on new operators, FloPoCo is also a prototype of arithmetic core generator in constant evolution. It already features an original approach to the generation of efficient and correct-by-construction arithmetic pipelines, and testbench generation. With increasingly complex operators, we now need to enrich it with a clean support for fixed-point semantic.

FloPoCo is also designed as a back-end for high-level synthesis (HLS) tools. The highly pipelined operators of FloPoCo may require specific optimization work from an HLS compiler.