Section: Dissemination

Teaching - Supervision - Juries

Teaching Responsibilities

There is a strong teaching activity in the Cairn team since most of the permanent members are Professors or Associate Professors.

 

C. Wolinski is the Director of Esir .

P. Quinton is the director of Ecole Normale Supérieure de Rennes.

D. Chillet is the Director of Academic Studies of Enssat .

P. Scalart is the Head of the Electronics Engineering department of Enssat .

S. Derrien is the responsible of the first year of the master of computer science at ISTIC since Sep. 2012.

O. Sentieys is responsible of the ”Embedded Systems” branch of the SISEA Master of Research (M2R).

D. Chillet is the co-repsonsible of the Embedded System speciality of the ICT Master of University of Science and Technology of Hanoi.

 

Enssat stands for ”École Nationale Supérieure des Sciences Appliquées et de Technologie” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Lannion.

ISTIC is the Electrical Engineering and Computer Science Department of the University of Rennes 1.

Esir stands for ”École supérieure d'ingénieur de Rennes” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Rennes.

M2R stands for Master by Research, second year.

 

D. Chillet is member of the French National University Council since 2009 in signal processing and electronics (Conseil National des Universités en 61e section).

D. Chillet is member of the Permanent Committee of the French National University Council since november 2011 in signal processing and electronics (Commission Permanente du Conseil National des Universités en 61e section).

A. Tisserand is member of the French National University Council since 2011 in computer science (Conseil National des Universités en 27e section).

Teaching

• O. Berder: introduction to signal processing, 38h, Enssat (L3)

• O. Berder: microprocessors and digital systems, 30h, Enssat (L3)

• O. Berder: wireless communications, 23h, Enssat (M2)

• O. Berder: ad hoc networks, 58h, Enssat (M1-M2)

• O. Berder: signal processing, 12h, IUT Lannion (L2)

• E. Casseau: signal processing, 16h, Enssat (L3)

• E. Casseau: low power design, 6h, Enssat (M1)

• E. Casseau: real time design methodology, 24h, Enssat (M1)

• E. Casseau: computer architecture, 36h, Enssat (M1)

• E. Casseau: system on chip and verification, 10h, Master by Research and Enssat (M2)

• E. Casseau: reconfigurable architectures, 25h, USTH (M2)

• S. Derrien: component and system synthesis, 16h, Research Master (MRI ISTIC) (M2)

• S. Derrien: computer architecture, 12h, ENS Cachan (L3)

• S. Derrien: introduction to operating systems, 8h, ISTIC (M1)

• F. Charot: specification of applications with the signal synchronous language, 24h, Esir (M1)

• F. Charot: virtual prototyping of multiprocessor system-on-chip, 24h, Esir (M1)

• F. Charot: design of embedded systems, 28h, Esir (M1)

• A.Courtay: Processor Architecture, 24h, Enssat (L3)

• A.Courtay: Digital Electronics, 32h, Enssat (L3)

• A.Courtay: Digital System Design, 12h, Enssat (L3)

• A.Courtay: Digital Electronics Communication Interfaces, 68h, Enssat (M1)

• A.Courtay: Processor Architecture, 25h, USTH (M1)

• D.Chillet: Basic processor architecture, 20h, Enssat (L1)

• D.Chillet: Design methodology of real-time systems, 32h, Enssat (L2)

• D.Chillet: Advanced processor architectures, 24h, Enssat (M2)

• D.Chillet: Multimedia processor architectures, 24h, Enssat (M2)

• D.Chillet: Multi-processor systems, 20h, Enssat (M2)

• D. Chillet: advanced processors architectures, 24h, Master by Research and Enssat (M2)

• D. Chillet: low-power digital CMOS circuits, 6h, Telecom Bretagne and University of Occidental Brittany (UBO) (M2)

• D. Chillet: Digital system design, 25h, University of Science and Technology of Hanoi (M1)

• D. Chillet: Advanced Multiprocessor system , 25h, University of Science and Technology of Hanoi (M2)

• M.Gautier, electronics, 42h, IUT Lannion (L1)

• M.Gautier, telecommunications, 114h, IUT Lannion (L1)

• M.Gautier, digital communications, 28h, IUT Lannion (L2)

• C. Killian, digital electronics, 74h, IUT Lannion (L1)

• C. Killian, digital electronics, 28h, IUT Lannion (L2)

• C. Killian, electricity, 60h, IUT Lannion (L1)

• C. Killian, signal processing, 40h, IUT Lannion (L2)

• R. Rocher: electricity, 16h, IUT Lannion (L1)

• R. Rocher: electronics, 44h, IUT Lannion (L1)

• R. Rocher: telecommunications, 82h, IUT Lannion (L1)

• R. Rocher: signal processing, 12h, IUT Lannion (L2)

• R. Rocher: digital communications, 48h, IUT Lannion (L2)

• P. Scalart: non-linear optimisation, 18h, Master by Research and Enssat (M2)

• P. Scalart: Parametric modelisation, optimal and adaptive Filters, 24h, Master by Research and Enssat (M2)

• P. Scalart: source coding, 14h, Master by Research and Enssat (M2)

• P. Scalart: cellular networks, 24h, Enssat (M2)

• P. Scalart: digital communication systems, 32h, Enssat (M1)

• P. Scalart: random signals and systems, 12h, Enssat (M1)

• O. Sentieys: digital signal processing, 40h, Enssat (M1)

• O. Sentieys: VLSI integrated circuit design, 40h, Enssat (M1)

• A. Tisserand: multiprocessor architectures and programming, 20h, Enssat and Master by Research, Univ. Rennes 1(M2)

• A. Tisserand: hardware computer arithmetic operators, 6h, Master by Research, Univ. Rennes 1 (M2)

• C. Wolinski: architecture 1, 64h, Esir (L3)

• C. Wolinski: architecture 2, 28h, Esir (L3)

• C. Wolinski: design of embedded systems, 48h, Esir (M1)

• C. Wolinski: signal, image, architecture, 26h, Esir (M1)

• C. Wolinski: programmable architectures, 10h, Esir (M1)

• C. Wolinski: component and system synthesis, 10h, Master by Research (MRI ISTIC) (M2)

Supervision

• PhD: Mahtab Alam, Power Aware Adaptive Techniques for Wireless Sensor Networks, Univ. Rennes 1, Jan. 2013, O. Sentieys, O. Berder, D. Menard.

• PhD: Robin Bonamy, Power Consumption Modelling and Optimisation for Heterogeneous Reconfigurable Platform, Univ. Rennes 1, Jul. 2013, D. Chillet.

• PhD: Thomas Chabrier, Arithmetic recodings for ECC cryptoprocessors with protections against side-channel attacks, Univ. Rennes 1, Jun. 2013, A. Tisserand, E. Casseau.

• PhD: Hervé Yviquel, From dataflow-based video coding tools to dedicated embedded multi-core platforms, Univ. Rennes 1, Oct. 2013, E. Casseau.

• PhD: Antoine Morvan, Polyhedral Model for High-Level Synthesis of Pipelined Architectures, Univ. Rennes 1, Jun. 2013, P. Quinton, S. Derrien.

• PhD: Vivek D. Tovinakere, Ultra-Low Power Reconfigurable Controllers for Wireless Sensor Networks, Univ. Rennes 1, Feb. 2013, O. Sentieys.

• PhD in progress: Florent Berthier, Study and Design of an Ultra Low Power Asynchronous Core for Sensor Networks, Oct. 2013, O. Sentieys, P. Vivet, E. Beigne.

• PhD in progress: Karim Bigou, RNS Hardware Units for ECC, Oct. 2011, A. Tisserand.

• PhD in progress: Franck Bucheron, Secure Virtualization for Embedded Systems, Oct. 2011, A. Tisserand.

• PhD in progress: Aymen Chakhari, Analytical approach for decision errors in fixed-point digital communication systems, Oct. 2010, R. Rocher, P. Scalart.

• PhD in progress: Gaël Deest, Computing with Errors: Error-Tolerant Machine Code Generation for Unreliable Embedded Hardware, Oct. 2013, S. Derrien, O. Sentieys.

• PhD in progress: Amine Didioui, Reconfigurable Radio Front-End for Energy-Harvesting Wireless Sensor Networks, Nov. 2010, O. Sentieys, C. Bernier.

• PhD in progress: Ali Hassan El-Moussawi, Performance/Accuracy Trade-Off in Automatic Parallelization for Embedded Many-Core Platforms, Nov. 2012, S. Derrien.

• PhD in progress: Christophe Huriaux, Embedded reconfigurable hardware accelerators with efficient dynamic reconfiguration management, Oct. 2012, O. Sentieys, A. Courtay.

• PhD in progress: Quang-Hai Khuat, Real-Time Spatio-Temporal Task Scheduling on 3D Architectures, Oct. 2011, D. Chillet.

• PhD in progress: Trong-Nhan Le, Global power management system for self-powered autonomous wireless sensor nodes, Jan. 2011, O. Sentieys, O. Berder.

• PhD in progress: Quang-Hoa Le, Virtualized dynamic reconfiguration for 3D SoC, Oct. 2012, E. Casseau, A. Courtay.

• PhD in progress: Xuan Chien Le, Indirect Monitoring in Self-Powered Wireless Sensor Networks for Smart Grid and Building Automation, Oct. 2013, O. Sentieys, O. Berder.

• PhD in progress: Jérémie Métairie, Reconfigurable Arithmetic Units for Secure Cryptoprocessors, Oct. 2012, A. Tisserand, E. Casseau.

• PhD in progress: Van Thiep Nguyen, Energy-efficient MAC protocols for cooperative strategies in Wireless Sensor Networks, Oct. 2013, O. Berder, M. Gautier.

• PhD in progress: Viet-Hoa Nguyen, Energy-efficient cooperative techniques for Wireless Body Area Sensor Networks, Nov. 2012, O. Berder, jointly with C. Langlais from Telecom Bretagne.

• Ganda-Stéphane Ouedraogo, Automatic synthesis of hardware accalerator from high-level specifications in flexible radios, Oct. 2011, M. Gautier, O. Sentieys.

• PhD in progress: Rengarajan Ragavan, Ultra-Low Power Reconfigurable Architectures for Computing and Control in Wireless Sensor Networks, Oct. 2013, O. Sentieys, C. Killian.

• PhD in progress: Mai-Thanh Tran, Hardware Synthesis of Flexible and Reconfigurable Radio from High-Level Language Dedicated to Physical Layer of Wireless Systems, Oct. 2013, E. Casseau, M. Gautier.

• PhD in progress: Pramod P. Udupa, Sampling, synchronising, digital processing and FPGA implementation of 100Gbps optical OFDM signals, Jan. 2011, O. Sentieys.

• PhD in progress: Zhongwei Zheng, Short-range geolocation algorithms based on distributed multi-sensor processing, Nov. 2012, P. Scalart, jointly with C. Roland from Lab-STICC.