Section: Partnerships and Cooperations

International Initiatives

Inria International Labs

EPFL-Inria

Associate Team involved in the International Lab:

IoTA

• Title: Ultra-Low Power Computing Platform for IoT leveraging Controlled Approximation

• International Partner (Institution - Laboratory - Researcher):

  • Ecole Polytechnique Fédérale de Lausanne (Switzerland) - Christian Enz

• Start year: 2017

• See also: https://team.inria.fr/cairn/IOTA

• Energy issues are central to the evolution of the Internet of Things (IoT), and more generally to the ICT industry. Current low-power design techniques cannot support the estimated growth in number of IoT objects and at the same time keep the energy consumption within sustainable bounds, both on the IoT node side and on cloud/edge-cloud side. This project aims to build on the preliminary results on inexact and exact sub/near-threshold circuit design to achieve major energy consumption reductions by enabling adaptive accuracy control of applications. IoTA proposes to address, in a consistent fashion, the entire design stack, from hardware design, up to software application analysis, compiler optimizations, and dynamic energy management. The main scientific challenge is twofold: (1) to add adaptive accuracy to hardware blocks built in near/sub threshold technology and (2) to provide the tools and methods to program and make efficient use of these hardware blocks for applications in the IoT domain. This entails developing approximate computing units, on one side, and methods and tools, on the other side, to rigorously explore trade-offs between accuracy and energy consumption in IoT systems. The expertise of the members of the two teams is complementary and covers all required technical knowledge necessary to reach our objectives, i.e., ultra low power hardware design (EPFL), approximate operators and functions (Inria, EPFL), formal analysis of precision in algorithms (Inria), and static and dynamic energy management (Inria, EPFL). Finally, the proof of concept will consist of results on (1) an adaptive, inexact or exact, ultra-low power microprocessor in 28 nm process and (2) a real prototype implemented in an FPGA platform combining processors and hardware accelerators. Several software use-cases relevant for the IoT domain will be considered, e.g., embedded vision, IoT sensors data fusion, to practically demonstrate the benefits of our approach.

Inria International Partners

LRS

• Title: Loop unRolling Stones: compiling in the polyhedral model

• International Partner (Institution - Laboratory - Researcher):

  • Colorado State University (United States) - Department of Computer Science - Prof. Sanjay Rajopadhye

HARAMCOP

• Title: Hardware accelerators modeling using constraint-based programming

• International Partner (Institution - Laboratory - Researcher):

  • Lund University (Sweden) - Department of Computer Science - Prof. Krzysztof Kuchcinski

SPINACH

• Title: Secure and low-Power sensor Networks Circuits for Healthcare embedded applications

• International Partner (Institution - Laboratory - Researcher):

  • University College Cork (Ireland) - Department of Electrical and Electronic Engineering - Prof. Liam Marnane and Prof. Emanuel Popovici

• Arithmetic operators for cryptography, side channel attacks for security evaluation, energy-harvesting sensor networks, and sensor networks for health monitoring.

DARE

• Title: Design space exploration Approaches for Reliable Embedded systems

• International Partner (Institution - Laboratory - Researcher):

  • IMEC (Belgium) - Francky Catthoor

• Methodologies to design low cost and efficient techniques for safety-critical embedded systems, Design Space Exploration (DSE), run-time dynamic control mechanisms.

Informal International Partners

• LSSI laboratory, Québec University in Trois-Rivières (Canada), Design of architectures for digital filters and mobile communications.

• Department of Electrical and Computer Engineering, University of Patras (Greece), Wireless Sensor Networks, Worst-Case Execution Time, Priority Scheduling.

• Karlsruhe Institute of Technology - KIT (Germany), Loop parallelization and compilation techniques for embedded multicores.

• Ruhr - University of Bochum - RUB (Germany), Reconfigurable architectures.

• University of Science and Technology of Hanoi (Vietnam), Participation of several Cairn 's members in the Master ICT / Embedded Systems.