3.1 Worst case execution time estimation of a program

The temporal study of real-time systems is based on the estimation of the bounds for their temporal parameters and more precisely the WCET of a program executed on a given processor. The main analyses for estimating WCETs are static analyses  38, dynamic analyses  21, also called measurement-based analyses, and finally hybrid analyses that combine the two previous ones  38.

The Kopernic approach for solving the WCET estimation problem is based on (i) the identification of the impact of variability factors on the execution of a program on a processor and (ii) the proposition of compositional rules allowing to integrate the impact of each factor within a WCET estimation. More precisely, we propose to identify classes of programs and classes of processors features for which we may provide compositional rules. By such identification, we restrain our WCET estimation problem to instances of programs and processors for which compositional rules may be proposed. We say that a rule $\circ$ is compositional for any two sets of measured execution times ${𝒞}_1$ and ${𝒞}_2$ of a program $A$, and a WCET statistical estimator $p$, if we obtain a safe WCET estimation for $A$ from $p({𝒞}_1\circ {𝒞}_2)$. For instance, ${𝒞}_1$ may be the set of measured execution times of the program $A$ while all processor features except the local cache L1 are deactivated, while ${𝒞}_2$ is obtained, similarly, with a shared L2 cache activated. We consider that the variation of all input variables of the program $A$ follows the same sequence of values, when measuring the execution time of the program $p$. For instance, our preliminary results indicate that the branch predictors do not allow such compositional rule $\circ$ to exist for the case of single core processors. We identify the following open research problems related to the first research axis:

1. the generalization of statistical modes analysis to multi-dimensional, each dimension representing a program when several programs cooperate;
2. the proposition of a rules set for building programs that are time predictable for the internal architecture of a given unicore and, then, of a multicore processor;
3. modeling the impact of processor features on the energy consumption to better consider both worst case execution time and schedulability analyses.

3.2 Building measurement-based benchmarks

The real-time community is facing the lack of benchmarks adapted to measurement-based analyses. Existing benchmarks for the estimation of WCET  34, 25, 22 have been used to estimate WCETs mainly for static analyses. They contain very simple programs and are not accompanied by a measurement protocol. They do not take into account functional dependencies between programs, mainly due to shared global variables which, of course, influence their execution times. Furthermore, current benchmarks do not take into account interferences due to the competition for resources, e.g., the memory shared by the different cores in a multicore. On the other hand, measurement-based analyses require execution times measured while executing programs on embedded processors, similar to those used in the embedded systems industry. For example, the mobile phone industry uses multicore based on non predictable cores with complex internal architecture, such as those of the ARM Cortex-A family. In a near future, these multicore will be found in critical embedded systems found in application domains such as avionics, autonomous cars, railway, etc., in which the team is deeply involved. This increases dramatically the complexity of measurement-based analyses compared to analyses performed on general purpose personal computers as they are currently performed.

Proposing reproducibility and representativity properties that measurement-based benchmarks should follow is the strength of this research axis. We understand by measurement-based benchmarks a 3-uple composed by a program, a processor and a measurement protocol. The associated measurement protocols should detail the variation of the input variables (associated to sensors) of these benchmarks and their impact on the output variables (associated to actuators), as well as the variation of the processor states. We understand by the reproducibility, the property of a measurement protocol to provide the same ordered set of execution times for a fixed pair (program, processor). We understand by the representativity, the existence of a (sufficiently small) number of values for the input variables allowing a measurement protocol to provide an ordered set of execution times that ensure a convergence for the Extreme Value Index estimators.

Within this research axis we identify the following open problems:

1. proving reproducibility and representativity properties while extending current benchmarks from predictable unicore processors (e.g., ARM Cortex-M4) to non predictable ones (e.g., ARM Cortex-A53 or Cortex-A7);
2. proving reproducibility and representativity properties while extending unicore benchmarks to multicore processors. In this context, we face the supplementary difficulty of defining the principles that an operating system should satisfy in order to ensure a real-time behaviour.

3.3 Scheduling of graph tasks on different resources

As stressed in the previous sections, the utilisation of multicore processors is the current trend of the CPS industry. On the other hand, following the model-driven approach, the functional description of the cyber part of the CPS, is performed as a graph of dependent functions, e.g., a block diagram of functions in Simulink, the most widely used modeling/simulation tool in industry. Of course, a program is associated to every function. Since the graph of dependent programs becomes a set of dependent tasks when real-time constraints must be taken into account, we are facing the problem of verifying the schedulability of such dependent task sets when it is executed on a multicore processor.

Directed Acyclic Graphs (DAG) are widely used to model different types of dependent task sets. The typical model consists of a set of independent tasks where every task is described by a DAG of dependent sub-tasks with the same period inherited from the period of each task  17. In such DAG, the sub-tasks are vertices and edges are dependencies between sub-tasks. This model is well suited to represent, for example, the engine controller of a car described with Simulink. The multicore schedulability analysis may be of two types, global or partitionned. To reduce interference and interactions between sub-tasks, we focus on partitioned scheduling where each sub-task is assigned to a given core  23.

In order to propose a general DAG task model, we identify the following open research problems:

1. a general schedulability problem where tasks are executed on predictable and non predictable processors, and such that some tasks communicate through predictable networks, e.g., inside a multicore or a manycore processor, and non-predictable networks, e.g., between these processors through internet. Within this general schedulability problem we mix probabilistic and non-probabilistic approaches;
2. the validation of the proposed framework on a multicore drone case study. By combining both multicore systems and distributed systems we have the challenging objective to propose time predictable platforms for drones, inspired by avionics design.

4.1 Avionics

The time critical solutions in this context are based on temporal and spatial isolation of the programs and the understanding of multicore interferences is crucial. Our contributions belong mainly to the solutions space for the objective [O1] identified previously.

4.2 Railway

The time critical solutions in this context concern both the proposition of an appropriate scheduler and associated schedulability analyses. Our contributions belong to the solutions space of problems dealt within objectives [O1] and [O2] identified previously.

4.3 Autonomous cars

Autonomous cars - the time critical solutions in this context concern the interaction between programs executed on multicore processors and messages transmitted through wireless communication channels. Our contributions belong to the solutions space of all three classes of problems dealt within all three Kopernic objectives identified previously.

4.4 Drones

As it is the case of autonomous cars, there is an interaction between programs and messages, suggesting that our contributions in this context belong to the solutions space of all three classes of problems dealt within the objectives identified previously.

5.1 Impact of research results

The Kopernic members provide theoretical means to improve the processor utilization. Such gain is estimated within $30\%$ to $60\%$ utilization gain for existing architectures or energy consumption for new architectures by decreasing the number of necessary cores.

7.1 New software

8.1 Worst case execution time estimation of a program

We consider WCET statistical estimators that are based on the utilization of the Extreme Value Theory  24. Compared to existing methods  38, our results require the execution of the program under study on the targeted processor or at least a cycle-accurate simulator of this processor. The originality of considering such WCET statistical estimators consists in the proposition of a black box solution with respect to the program structure. Such solution is obtained by (i) comparing different Generalized Extreme Values estimators 12 and (ii) separating the impact of the processor features from those of the program structure and of the execution environment, as variability factors for the CPS time properties.

Understanding the impact of the processor features and of the program structure is widely studied in the static analysis literature. In our context, we take into account also the execution environment and one may start by identifying this environment with respect to its impact on the paths of a program, which are, in our case, exposed by clusters of execution times. In Figure 3, the horizontal axis represents the order of execution, while the vertical axis the execution time values. Once the paths identified, identically distributed tests indicate if each path is sufficiently observed, while independence tests are used to identify the input variables that do have an impact on the execution time.

Last, but not least, execution scenarios for the identified input variables are fixed and they allow to observe the weight of each variability factor. In Figure 4, the horizontal axis represents the order of execution, while the vertical axis the execution time values. The lowest curve (blue) represents the values of an input variable, while the other curves are obtained by activating a new variability factor for exactly the same execution scenario, i.e., variation of the input variables and of the processor features. For instance, the lowest (yellow style) are obtained when the program is executed alone on one core and the highest curves are obtained for executions with all cores active, two activated levels of caches, etc.

These preliminary results 10 confirm that the input variables and the cache memories are the most important variability factors and, most importantly, that the impact of some variability factors are composable. As dependencies are related to the order of execution between consecutive instances of a program, we exploit them to understand the inter-execution relations. To illustrate our preliminary results, we use execution time measurements made on programs performing the PX4-RT autopilot. To our best knowledge there are no equivalent results because the authors of existing work had never access to real programs of an industrial application.

Our first results confirm the existence, for each program, of execution modes 13. For example in the case of one program of the drone autopilot, we can identify three modes as three concentrations of response times, shown in the left part of Figure 5. The response time of a program corresponds to its execution time when the operating system is taken into account. The modes are estimated with statistical methods by the red curve shown in the right part of Figure 5.

In order to restrain our WCET estimation problem with respect to the program structure, we propose a new modeling semantic allowing the characterization of programs that are "time predictable". Indeed, the problem of time unpredictability 15 increases the complexity of the WCET estimation. We consider programs executed on general purpose processors that are not predictable. The time unpredictability of a program is underlined by an important execution time variability.

Compared to static analysis-based WCET estimation methods, that mainly estimate the WCET of a program on a processor, our goal is to propose rules for the design of time predictable programs with respect to a multicore processor, while reducing the design time. The first step consists in identifying the different time unpredictability factors of a program (internal and external architecture, the structure of the program, the scheduling algorithm used by the operating system executing the program) and then propose a formalization of the relations between time unpredictability factors and the execution time of a program. This formalization could strengthen the statistical analysis proposed by the measurement-based analyses presented above. The second step consists in deducing from the first step some programming rules reducing and controlling the time unpredictability. Our preliminary work consists in measuring the impact of the internal architecture on execution times of programs executed on a multicore processor based on ARM Cortex-A53 widely used in embedded devices. Presently, these programs are executed without using an operating system (bare-metal) to focus on the impact of the internal architecture. The internal architecture of the ARM Cortex-A53 processor has been studied in depth and we proposed simple programs allowing to deduce first relations between the execution times of these programs and the internal architecture of the processor.

8.2 Multicore processor graph tasks scheduling

Due to widespread of multicore processors on embedded and real-time systems, we concentrate our work on the study of the schedulability of real-time tasks with precedence constraints on such processors.

As stressed in the previous sections, the utilisation of multicore processors is the current trend of the CPS industry, while model-driven approaches are considered. Within such models, the functional description of the cyber part of the CPS, is performed, often, as a graph of dependent functions, e.g., a block diagram of functions in Simulink, the most widely used modeling/simulation tool in industry. Of course, a program is associated to every function. Since the graph of dependent programs becomes a set of dependent tasks when real-time constraints must be taken into account, we are facing the problem of verifying the schedulability of such dependent task sets when it is executed on a multicore processor.

Directed Acyclic Graphs (DAG) are widely used to model different types of dependent task sets. The typical model consists of a set of independent tasks where every task is described by a DAG of dependent sub-tasks with the same period inherited from the period of each task  17. In such DAG, the sub-tasks are vertices and edges are dependencies between sub-tasks. This model is well suited to represent, for example, the engine controller of a car described with Simulink. The multicore schedulability analysis may be of two types, global or partitionned. To reduce interference and interactions between sub-tasks, we focus on partitioned scheduling where each sub-task is assigned to a given core  23.

Our preliminary results 8, 9, 14 make use of the potential parallelism between the sub-tasks to decrease the response time of each DAG. The schedulability analysis performs a partition of the sub-tasks on the cores and for every core performs a schedulability analysis. For instance, in Figure 6, each of the two tasks is described by a DAG, where identical colour indicates that these sub-tasks are executed on the same core.

Furthermore, in order to reduce the pessimism and its associated over-dimensioning of the hardware architectures, the proposed schedulability analysis is probabilistic considering the variability of execution times of tasks, that is, several execution times are associated to each task with a probability to occur  18. This multicore probabilistic schedulability analysis is based on fixed-point equations instead of mixed integer linear programming (MILP) formulation used by existing results. Indeed, the MILP formulation has an important complexity that probabilistic analyses cannot afford. We assign priorities at the sub-task level to define the execution order between different vertices from the same graph, which reduces the response time of the entire DAG task. Our priority assignment is performing well for both non-probabilistic and for probabilistic bounds on the execution times of sub-tasks. It performs significantly better than existing work, when compared to the case of non-probabilistic WCET. This is due to a better utilization of the possible parallelism in a DAG structure that decreases the response time. We extend the previous partitioning algorithm by considering the communication times corresponding to dependencies between sub-tasks when they are assigned to different cores. Our solution improves significantly the schedulability ratio compared to existing work. The current limitation of our first results is the unique period for all sub-tasks of a task and, to overcome it, we need the generalize the DAG model to the tasks. This generalization leads to a unique DAG where vertices are tasks that may have different periods and edges are describing dependencies between tasks. Such general model is more suited to new model-driven models used in industry for designing complex CPS, e.g., an autonomous vehicle system, merging inside each vehicle numerous control loops, some of them including artificial intelligence algorithms, and navigation planning algorithms involving communication between vehicles, and between vehicles and infrastructures.

8.3 Data-oriented scheduling approaches

Following our existing results confirmed by a journal publication 7, we consider the scheduling problem of tasks using an inter-task communication model based on a circular buffer, easing the data consistency between tasks 36, 35. The tasks are scheduled on one processor by a fixed priority preemptive scheduling algorithm and they have implicit deadlines. Previously, we have provided a formal method calculating the optimal size for each of the buffers while ensuring data consistency and an analytical characterization of the temporal validity and reachability properties of the data flowing in between communicating tasks. These two properties are characterized by considering both tasks execution and data propagation orders. Moreover, we propose protocols to ensure such properties highly depend on the considered communication model (shared registers or large buffers) and the data access policy (directly or via local copies). In order to overcome this limitation, we provide in 11 the means for managing the FIFO buffers to guarantee these data properties in a way that communication dependencies do not impact the tasks system scheduling order. We do so while considering the communication model presented in 36. We provide, also, an algorithm implementing the last reader tags mechanism together with the corresponding data temporal matching.

9.1 CIFRE Grant funded by StatInf

A CIFRE agreement between the Kopernic team and the start-up StatInf has started on October 1st, 2020. Its funding is related to study of WCET models taking into account the energy consumption according to the fourth research objective of our team.

10.1 International initiatives

10.2 European initiatives

10.3 National initiatives

11.1 Promoting scientific activities

11.2 Teaching - Supervision - Juries

11.3 Popularization

• Liliana Cucu-Grosjean and Adriana Gogonel have participated to the Agoranov action on promoting start-ups and female investissement in schools, the video is available at https://www.youtube.com/watch?v=FlUvnXSQqJs.

12.1 Major publications

• 1 patentLilianaL. Cucu-Grosjean and AdrianaA. Gogonel. Simulation DeviceFR2016/050504FranceMarch 2016, URL: https://hal.archives-ouvertes.fr/hal-01666599
• 2 inproceedingsLilianaL. Cucu-Grosjean, LucaL. Santinelli, MichaelM. Houston, CodeC. Lo, TullioT. Vardanega, LeonidasL. Kosmidis, JaumeJ. Abella, EnricoE. Mezzetti, EduardoE. Quiñones and Francisco J.F. Cazorla. Measurement-Based Probabilistic Timing Analysis for Multi-path Programsthe 24th Euromicro Conference on Real-Time Systems, ECRTS2012, 91--101
• 3 patentAdrianaA. Gogonel and LilianaL. Cucu-Grosjean. Dispositif de caractérisation et/ou de modélisation de temps d'exécution pire-cas1000408053FranceJune 2017, URL: https://hal.archives-ouvertes.fr/hal-01666535
• 4 inproceedings T. Kloda, A. Bertout and Y. Sorel. Latency analysis for data chains of real-time periodic tasks the 23rd IEEE International Conference on Emerging Technologies and Factory Automation, ETFA'18 September 2018
• 5 articleCristianC. Maxim, AdrianaA. Gogonel, Irina MariucaI. Asavoae, MihailM. Asavoae and LilianaL. Cucu-Grosjean. Reproducibility and representativity: mandatory properties for the compositionality of measurement-based WCET estimation approachesSIGBED Review1432017, 24--31
• 6 inproceedings S. E.S. Saidi, N. Pernet and Y. Sorel. Scheduling Real-time HiL Co-simulation of Cyber-Physical Systems on Multi-core Architectures the 24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications August 2018

12.2 Publications of the year

12.3 Cited publications

• 15 articleP. Axer, R. Ernst, H. Falk, A. Girault, D. Grund, NanN. Guan, B. Jonsson, P. Marwedel, J. Reineke, C. Rochange, M. Sebastian, R. von Hanxleden, R. Wilhelm and WangW. Yi. Building timing predictable embedded systemsACM Trans. Embedded Comput. Syst.1342014, 82:1--82:37
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• 16 book R. Baheti and H. Gill. Cyber-physical systems IEEE 2011
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• 17 inproceedingsS. Baruah, V. Bonifaci, A. Marchetti-Spaccamela, L. Stougie and A. Wiese. A Generalized Parallel Task Model for Recurrent Real-time Processes2012 IEEE 33rd Real-Time Systems Symposium (RTSS)2012, 63-72
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• 18 inproceedings S. Ben-Amor, D. Maxim and L. Cucu-Grosjean. Schedulability analysis of dependent probabilistic real-time tasks the 24th International Conference on Real-Time Networks and Systems (RTNS) 2016
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• 19 inproceedingsT. Bourke, J.-L. Colaço, B. Pagano, C. Pasteur and M. Pouzet. A Synchronous-Based Code Generator for Explicit Hybrid Systems LanguagesCompiler Construction - 24th International Conference, CC, Joint with ETAPS2015, 69--88
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• 20 inproceedings L. Cucu. Preliminary results for introducing dependent random variables in stochastic feasiblity analysis on CAN the WIP session of the 7th IEEE International Workshop on Factory Communication Systems (WFCS) 2008
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• 21 articleR. I.R. Davis and L. Cucu-Grosjean. A Survey of Probabilistic Timing Analysis Techniques for Real-Time SystemsLITES612019, 03:1--03:60
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• 22 inproceedingsH. Falk, S. Altmeyer, P. Hellinckx, B. Lisper, W. Puffitsch, C. Rochange, M. Schoeberl, R. B.R. Sorensen, P. Wägemann and S. Wegener. TACLeBench: A Benchmark Collection to Support Worst-Case Execution Time Research16th International Workshop on Worst-Case Execution Time Analysis (WCET)55OASICS2016, 2:1--2:10
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• 23 inproceedingsJoseJ. Fonseca, GeoffreyG. Nelissen, VincentV. Nelis and LuísL. Pinho. Response time analysis of sporadic DAG tasks under partitioned scheduling11th IEEE Symposium on Industrial Embedded Systems (SIES)05 2016, 1-10
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• 24 articleS. J.S. Gil, I. Bate, G. Lima, L. Santinelli, A. Gogonel and L. Cucu-Grosjean. Open Challenges for Probabilistic Measurement-Based Worst-Case Execution TimeEmbedded Systems Letters932017, 69--72
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• 25 inproceedingsJ. Gustafsson, A. Betts, A. Ermedahl and B. Lisper. The Mälardalen WCET Benchmarks: Past, Present And Future10th International Workshop on Worst-Case Execution Time Analysis (WCET)15OASICS2010, 136--146
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• 26 article E. Lee. Computing Needs Time Communications of ACM 52 5 2009
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• 27 book E. Lee and S. Seshia. Introduction to embedded systems - a cyber-physical systems approach MIT Press 2017
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• 28 inproceedings J.P.J. Lehoczky. Real-Time Queueing Theory the 10th IEEE Real-Time Systems Symposium (RTSS) 1996
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• 29 book S. BaruahS. M. Bertogna and G. Buttazzo. Multiprocessor Scheduling for Real-Time Systems Springer 2015
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• 30 inproceedings D. Maxim, O. Buffet, L. Santinelli, L. Cucu-Grosjean and R. I.R. Davis. Optimal Priority Assignment Algorithms for Probabilistic Real-Time Systems the 19th International Conference on Real-Time and Network Systems (RTNS) 2011
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• 31 inproceedings D. Maxim and L. Cucu-Grosjean. Response Time Analysis for Fixed-Priority Tasks with Multiple Probabilistic Parameters the IEEE Real-Time Systems Symposium (RTSS) 2013
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• 32 inproceedingsR. Medina and L. Cucu-Grosjean. Work-in-Progress: Probabilistic System-Wide DVFS for Real-Time Embedded SystemsIEEE Real-Time Systems Symposium (RTSS)IEEE2019, 508--511
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• 33 inproceedings F. Ndoye and Y. Sorel. Monoprocessor Real-Time Scheduling of Data Dependent Tasks with Exact Preemption Cost for Embedded Systems the 16th IEEE International Conference on Computational Science and Engieering (CSE) 2013
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• 34 inproceedings F. Nemer, H. Cassé, P. Sainrat, J. P.J. Bahsoun and M. D.M. Michiel. PapaBench: a Free Real-Time Benchmark 6th Intl. Workshop on Worst-Case Execution Time (WCET) Analysis 4 OASICS 2006
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• 35 inproceedingsEvaristeE. Ntaryamira, CristianC. Maxim and LilianaL. Cucu-Grosjean. Data consistency and temporal validity under the circular buffer communication paradigmRACS '19 - Conference on Research in Adaptive and Convergent SystemsChongqing, ChinaACM Press2019, 51-56URL: https://hal.inria.fr/hal-02409672
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• 36 inproceedingsEvaristeE. Ntaryamira, CristianC. Maxim and LilianaL. Cucu-Grosjean. The temporal correlation of data in a multirate systemRTNS'2019 - 27th International Conference on Real-Time Networks and SystemsToulouse, France2019, URL: https://hal.archives-ouvertes.fr/hal-02362858
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• 37 inproceedings S. E.S. Saidi, N. Pernet and Y. Sorel. Automatic Parallelization of Multi-Rate FMI-based Co-Simulation On Multi-core the Symposium on Theory of Modeling & Simulation: DEVS Integrative M&S Symposium 2017
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• 38 articleR. Wilhelm, J. Engblom, A. Ermedahl, N. Holsti, S. Thesing, D. Whalley, G.Bernat, C. Ferdinand, R.Heckmann, T. Mitra, F. Mueller, I. Puaut, P. Puschner, G. Staschulat and P. Stenströem. The worst-case execution time problem: overview of methods and survey of toolsTrans. on Embedded Computing Systems732008, 1-53
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