Activity report
RNSR: 201221017X
Research center
In partnership with:
Institut national des sciences appliquées de Lyon
Team name:
Software and Cognitive radio for telecommunications
In collaboration with:
Centre of Innovation in Telecommunications and Integration of services
Networks, Systems and Services, Distributed Computing
Networks and Telecommunications
Creation of the Project-Team: 2013 July 01


Computer Science and Digital Science

  • A1.1.2. Hardware accelerators (GPGPU, FPGA, etc.)
  • A1.1.10. Reconfigurable architectures
  • A1.1.12. Non-conventional architectures
  • A1.2.5. Internet of things
  • A1.2.6. Sensor networks
  • A1.5.2. Communicating systems
  • A2.3.1. Embedded systems
  • A2.6.1. Operating systems
  • A5.9. Signal processing
  • A8.6. Information theory

Other Research Topics and Application Domains

  • B6.2. Network technologies
  • B6.2.2. Radio technology
  • B6.4. Internet of things
  • B6.6. Embedded systems

1 Team members, visitors, external collaborators

Research Scientists

  • Luc Forget [Xilinx, Researcher, from Feb 2021]
  • Romain Michon [Inria, from Oct 2021, Starting Faculty Position]

Faculty Members

  • Tanguy Risset [Team leader, INSA Lyon, Professor, HDR]
  • Florent Dupont de Dinechin [INSA Lyon, Professor, HDR]
  • Florin Hutu [INSA Lyon, Associate Professor]
  • Kevin Marquet [INSA Lyon, Associate Professor]
  • Guillaume Salagnac [INSA Lyon, Associate Professor]
  • Guillaume Villemaud [INSA Lyon, Associate Professor, HDR]

PhD Students

  • Jesus Argote Aguilar [Univ de Rennes I, from Oct 2021]
  • Gautier Berthou [Inria, until Mar 2021]
  • Maxime Christ [Univ Grenoble Alpes]
  • Luc Forget [INSA Lyon, Jan 2021]
  • Tarik Lassouaoui [INSA Lyon]
  • Maxime Popoff [INSA Lyon, from Sep 2021]
  • Yanni Zhou [INSA Lyon]

Technical Staff

  • Maxime Popoff [Inria, Engineer, until Sep 2021]
  • Régis Rousseau [INSA Lyon]

Interns and Apprentices

  • Romain Borgna [INSA Lyon, from Jun 2021 until Aug 2021]
  • Oussama Bouksim [Inria, from Mar 2021 until Aug 2021]
  • Thomas Delmas [Inria, from Apr 2021 until Jul 2021]
  • Antonin Dudermel [École Normale Supérieure de Lyon, from Feb 2021 until Jun 2021]
  • Haddou Mazoz [Inria, from May 2021 until Aug 2021]
  • Adam Mezaber [Inria, Jan 2021]

Administrative Assistant

  • Anouchka Ronceray [Inria]

2 Overall objectives

2.1 Introduction

The success of radio networking relies on a small set of rules: i) protocols are completely defined beforehand, ii) resource allocation policies are mainly designed in a static manner and iii) access network architectures are planned and controlled. Such a model obviously lacks adaptability and also suffers from a suboptimal behavior and performance.

Because of the growing demand for radio resources, several heterogeneous standards and technologies have been introduced by the standard organizations or industry by different workgroups within the IEEE (802 family), ETSI (GSM), 3GPP (3G, 4G) or the Internet Society (IETF standards) leading to the almost saturated usage of several frequency bands (see Fig. 1).

Figure 1
Figure 1: The most recent standards for wireless communications are developed in the UHF and VHF bands. These bands are mostly saturated (source: WPAN/WLAN/WWAN Multi-Radio Coexistence, IEEE 802 Plenary, Atlanta, USA, Nov.2007)

These two facts, obsolescence of current radio networking rules on one hand, and saturation of the radio frequency band on the other hand, are the main premises for the advent of a new era of radio networking that will be characterized by self-adaptive mechanisms. These mechanisms will rely on software radio technologies, distributed algorithms, end-to-end dynamic routing protocols and therefore require a cross-layer vision of “cognitive wireless networking”: Getting to the meet of Cognition and Cooperation, beyond the inherent communication aspects: cognition is more than cognitive radio and cooperation is not just relaying. Cognition and cooperation have truly the potential to break new ground for mobile communication systems and to offer new business models.30

From a social perspective, pervasive communications and ambient networking are becoming part of more and more facets of our daily life. Probably the most popular usage is mobile Internet access, which is made possible by numerous access technologies, e.g. cellular mobile networks, WiFi, Bluetooth, etc. The access technology itself is becoming transparent for the end user, who does not care about how to access the network but is only interested in the services available and in the quality of this service.

Beyond simple Internet access, many other applications and services are built on the basis of pervasive connectivity, for which the communication is just a mean, and not a finality. Thus, the wireless link is expected to even be invisible to the end user and constitutes the first element of the Future Internet of Things 29, to develop a complete twin virtual world fully connected to the real one.

The way radio technologies have been developed until now is far from offering a real wireless convergence 17. The current development of the wireless industry is surely slowed down by the lack of radio resources and the lack of systems flexibility.

One can get rid of this technological bottleneck by solving three complementary problems: terminal flexibility, agile radio resource management and autonomous networking. These three objectives are subsumed by the concept of Software Radio, a term coined by J. Mitola in his seminal work during the early 90's 25, 24. While implementing everything in software nodes is still an utopia, many architectures now hitting the market include some degree of programmability; this is called Software-Defined Radio. The word “defined” has been added to distinguish from the ideal software radio. A software defined radio is a software radio which is defined for a given frequency range and a maximal bandwidth.

In parallel, the development of new standards is threatened by the radio spectrum scarcity. As illustrated in Fig. 1, the increasing number of standards already causes partial saturation of the UHF band, and will probably lead to its full saturation in the long run. However, this saturation is only “virtual” because all equipments are fortunately not emitting all the time 17. A good illustration is the so-called “white spaces”, i.e. frequency bands that are liberated by analog television disappearing and can be re-used for other purposes, different rules are set up in different countries. In this example, a solution for increasing the real capacity of the band originates from self-adaptive behavior. In this case, flexible terminals will have to implement agile algorithms to share the radio spectrum and to avoid interference. In this context, cooperative approaches are even more promising than simple resource sharing algorithms.

With Software-Defined Radio technology, terminal flexibility is at hand, many questions arise that are related to the software layer of a software radio machine: how will this kind of platform be programmed? How can we write programs that are portable from one terminal to another? Autonomous networking will only be reached after a deep understanding of network information theory. Thus, given that there will be many ways for transmitting data from one point to another, what is the most efficient way in terms of throughput? power consumption? etc. Last but not least, agile Radio Resource sharing is addressed by studying mimo (multiple-input and multiple-output) and multi-standard radio front-end. This new technology is offering a wide range of research problems. These three topics: software programming of a software radio machine, distributed algorithms for radio resource management and multi-standard radio front-end have constituted the research directions of Socrate at its creation.

2.2 Technological State of the Art

A Software-Defined Radio (sdr) system is a radio communication system in which computations that in the past were typically implemented in hardware (e.g. mixers, filters, amplifiers, modulators/demodulators, detectors, etc.) are instead implemented as software programs  25, 20.

SDR Technology
Figure 2
Figure 2: Radio Block Diagram, highlighting separation between digital and analog parts, as well as programmable, configurable and fixed hardware parts.

The different components of a radio system are illustrated in Fig. 2. Of course, all of the digital components may not be programmable, but the bigger the programmable part (dsp/fpga part on Fig. 2), the more software the radio. Dedicated ips1 are needed, for these ip it is more suitable to use the term configurable than programmable. In a typical sdr, the analog part is limited to a frequency translation down to an intermediate band which is sampled and all the signal processing is done digitally.

SDR Forum Classification

To encourage a common meaning for the term “sdr” the sdr Forum (renamed Wireless Innovation Forum proposes to distinguish five tiers:

  • Tier 0 – Hardware Radio: The radio parameters cannot be changed, radio is implemented only with hardware components.
  • Tier 1 – Software Controlled Radio: A radio where only the control functions are implemented in software, baseband processing is still performed in hardware, the radio is able to switch between different hardware.
  • Tier 2 – Software-Defined Radio: The most popularly understood definition of sdr: the radio includes software control of modulation, bandwidth, frequency range and frequency bands. Conversion to digital domain still occurs after frequency conversion. It is currently implemented using a wide range of technologies: Asics, fpgas, dsps, etc.
  • Tier 3 – Ideal Software Radio: Digital conversion occurs directly at the antenna, programmability extends to the whole system.
  • Tier 4 – Ultimate Software Radio: Same reconfigurability capabilities as in Tier 3, but with a switching between two configurations in less than one millisecond.

The main restriction to build an ideal software radio is sampling rate: sampling at a high rate is not an easy task. Following the Shannon-Nyquist theorem, sampling the rf signal at a rate greater than twice the frequency of the signal is sufficient to reconstruct the signal. Sampling can be done at lower rate (decimation), but errors can be introduced (aliasing) that can be corrected by filtering (dirty radio concept). Building an sdr terminal implies a trade-of between sampling frequency and terminal complexity. For instance, sampling at 4.9 GHz would require a 12-bit resolution adc with at least 10GHz sample rate which is today not available with reasonable power consumption (several hundreds Watt).

Cognitive Radio

sdr technology enables over the air programming (Otap) which consists in describing methods for distributing new software updates through the radio interface. However, as sdr architectures are heterogeneous, a standard distribution method has not emerged yet.

Cognitive Radio is a wireless communication system that can sense the air, and decide to configure itself in a given mode, following a local or distributed decision algorithm. Although Tier 3 sdr would be an ideal platform for cognitive radio implementation, cognitive radios do not have to be sdr.

Cognitive Radio is currently a very hot research topic as show the dozens of sessions in research conferences dedicated to it. In 2009, the American National Science Foundation (nsf) held a workshop on “Future Directions in Cognitive Radio Network Research”  28. The purpose of the workshop was to explore how the transition from cognitive radios to cognitive radio networks can be made. The resulting report indicated the following: 

  • Emerging cognitive radio technology has been identified as a high impact disruptive technology innovation, that could provide solutions to the radio traffic jam problem and provide a path to scaling wireless systems for the next 25 years.
  • Significant new research is required to address the many technical challenges of cognitive radio networking. These include dynamic spectrum allocation methods, spectrum sensing, cooperative communications, incentive mechanisms, cognitive network architecture and protocol design, cognitive network security, cognitive system adaptation algorithms and emergent system behavior.

The report also mentioned the lack of cognitive radio testbeds and urged “The development of a set of cognitive networking test-beds that can be used to evaluate cognitive networks at various stages of their development”, which, in some sense strengthens the creation of the Socrate team and its involvement in the FIT project  23.

3 Research program

3.1 Flexible Radio Front-End

This axis mainly deals with the radio front-end of software radio terminals. In order to ensure a high flexibility in a global wireless network, each node is expected to offer as many degrees of freedom as possible. For instance, the choice of the most appropriate communication resource (frequency channel, spreading code, time slot,...), the interface standard or the type of antenna are possible degrees of freedom. The multi-* paradigm denotes a highly flexible terminal composed of several antennas providing mimo features to enhance the radio link quality, which is able to deal with several radio standards to offer interoperability and efficient relaying, and can provide multi-channel capability to optimize spectral reuse. On the other hand, increasing degrees of freedom can also increase the global energy consumption, therefore for energy-limited terminals a different approach has to be defined.

In this research axis, we expect to demonstrate optimization of flexible radio front-end by fine grain simulations, and also by the design of home made prototypes. Of course, studying all the components deeply would not be possible given the size of the team, we are currently not working in new technologies for dac/adc and power amplifiers which are currently studied by hardware oriented teams. The purpose of this axis is to build system level simulation taking into account the state of the art of each key component.

3.2 Software Radio Programming Model

This research research axis is concerned with embedded software aspect for low power embedded systems: how can they be adapted to integrate some reconfigurability.

The expected contributions of Socrate in this research axis are :

  • The design and implementation of a software tools for embedded systems and ultra-low power sensor.
  • Prototype implementations of novel transiently powered devices.
  • Development of smart nodes: a low-power wireless sensor adapted to wsn (Wireless Sensor Network) applications and possibly without battery.
  • Methodology clues and programming tools to program all these prototypes.

3.3 Evolution of the Socrate team

In 2018 the Socrate team which was originaly conceived to develop software defined radio has decided to split in two teams: the Maracas Team was created with what consisted former Socrate Axis 2 : "Multi-User Communications and Agile Radio Ressource Sharing". Maracas is directed by Jean-Marie Gorce, and the Socrate team now consists in two research axis (described above) which were the Axis 1 and 3 previous version of Socrate.

The advent of non-volatile memory technologies (NVRAM) is causing a major evolution in all software layers. On the one hand, the non-volatility of data is a nice solution to memory inconsistencies that occur, for instance, on a power outage. On the other hand, these memories have very different performances from the usual DRAM, which tends to the appearance of hybrid and complex memory hierarchies. Many technological and scientific challenges are to be faced in all software layers to deal with these two sets of issues.

During two years, Socrate worked within the framework of very low consumption sensors and devices either on the radio side or on the embedded systems side, trying to study what could be next generation sensors powered by harvesting energy from their environnement. The Socrate team proposed, with Sytare  18, a software solution allowing to develop embedded applications on platforms supporting an intermittent power supply and integrating NVRAM. The IPL ZEP was also launched by Socrate in 2018 to respond to various scientific challenges related to this issue.

However this research direction seems too fragile to really build a complete Inria project on it. The banckrupty of start-up eVaderis with which Socrate had a PhD defended  22, together with the small energy quantities gathered by non-solar energy harvesting are signs of this weakness. It is probably to early to start, as we wished, a research team on battery-free next generation sensors. We finally decided to stop Socrate and to continue on various research team projects.

The evolution predicted for the Socrate team is represented on Fig. 3. As mentioned before, we do not plan to ask for the renewal of Socrate as an Inria project team, so Socrate should probably be ended by the end of 2021. In addition to the creation of the Maracas Inria project team headed by Jean-Marie Gorce (1st July 2018), two members (Tanguy Risset and Florent de Dinechin) are involved in the creation of a project-team, named Emeraude, focused on a new topic: embedded programmable audio systems in collaboration with Grame-CNCM. The other members are involved in teams that will not give rise to new Inria teams: Kevin Marquet and Guillaume Salagnac are involved in the creation of a Team called Phenix targeting digital ecological transition, and Florin Hutu and Guillaume Villemaud will continue to study low power radio tansceiver in close collaboration with Ampere laboratory in Lyon.

Figure 3
Figure 3: Evolution of the Socrate team members

4 Application domains

Here are the relevant research domains where Socrate efforts are useful:

  • Antennas and RF Front-Ends: This is a key issue for reducing interference, increasing capacity and reusing frequency. Hot topics such as wake-up radio or multi protocol parallel radio receivers are directly impacted by research on Antennas. Socrate has research work going on in this area.
  • Wake-up radio. In the context of transiently powered systems, wake-up radio is still a hot topic rather studied by micro-electronics laboratories (CEA Leti for instance). Socrate have been studied a particular prototype for many years.
  • Software stack for transiently powered sensor. Battery-free sensor are foreseen as a major technological evolution for next IoT generation. Surviving power outage is a new challenge for sensors. Socrate has been one of the first team to work on that topic.
  • High level tools for FPGA programming. With the end of Moore low, FPGA are seen as the opportunity to continue performance growth. The acquisition of Altera by Intel and, more recently, of Xilinx by AMD is a clear sign of it. Socrate is studying arithmetic operator on FPGA as well as high level compilation flow for FPGA.

5 Social and environmental responsibility

Because of the evolution of the socrate team mentionned in section 3.3, Socrate member are increasingly involved in topic related to numerical ecological transition. Kevin Marquet took the co-direction of GDS EcoInfo (CNRS) since September 2019. He is also collaborating with the Inria Spades team, first by co-supervising a PhD student on the environmental issues of digital technology, then by participating in reading workshops, once a month, on related themes. He is also participating in the creation of an Inria Challenge on digital sobriety, coordinated by Sophie Quinton and Peter Sturm.

Training in environmental issues is of growing importance. In this context, we have, with several colleagues, developed a knowledge repository intended to help teachers to set up courses on this subject  21.

6 Highlights of the year

2021 will be the last year of the Socrate Project team. Socrate has successefully built the FIT/CorteXlab platform which is now handled by the Maracas Team.

Following Socrate the Emeraude will start in 2022, taking advantage of Socrate skill in signal processing for Audio, embedded system design, FPGA programming and arithmetic.

7 New software and platforms

7.1 New software

7.1.1 FloPoCo

  • Name:
    Floating-Point Cores, but not only
  • Keyword:
    Synthesizable VHDL generator
  • Functional Description:
    The purpose of the open-source FloPoCo project is to explore the many ways in which the flexibility of the FPGA target can be exploited in the arithmetic realm.
  • URL:
  • Contact:
    Florent de Dinechin
  • Participants:
    Florent de Dinechin, Luc Forget
  • Partners:
    ENS Lyon, Insa de Lyon, Inria, Fulda University of Applied Science

7.1.2 Sytare

  • Keywords:
    Embedded systems, Operating system, Non volatile memory
  • Functional Description:
    Sytare is an embedded operating system targeting tiny platforms with intermittent power. In order to make power failures transparent for the application, the system detects imminent failures and saves a checkpoint of program state to non-volatile memory. Hardware peripherals are also made persistent without requiring developer attention.
  • URL:
  • Publication:
  • Authors:
    Tristan Delizy, Gautier Berthou, Guillaume Salagnac, Kevin Marquet, Tanguy Risset
  • Contact:
    Guillaume Salagnac

7.1.3 NanoTracer

  • Name:
  • Keywords:
    Embedded systems, Power monitoring, Low power consumption
  • Functional Description:
    NanoTracer is a high performance ammeter dedicated to power measurements for small devices. The system measures currents between 100nA and 100mA (gain is audo-adjusted dynamically) with a sampling frequency of 2Msps. Data is streamed to a PC over USB which enables long-running experiments, or just real-time visualization of data.
  • URL:
  • Contact:
    Guillaume Salagnac

7.1.4 marto

  • Name:
    Modern Arithmetic Tools
  • Keywords:
    High-level synthesis, Arithmetic, FPGA
  • Functional Description:

    Marto provides C++ headers to implement custom sized arithmetic operators such as:

    Custom sized posits and their environment (including the quire) Custom sized IEEE-754 numbers Custom sized Kulisch accumulators (and sums of products)

  • URL:
  • Publication:
  • Contact:
    Yohann Uguen
  • Participants:
    Yohann Uguen, Florent de Dinechin, Luc Forget

7.1.5 hint

  • Name:
    High-level synthesis Integer Library
  • Keyword:
    High-level synthesis
  • Functional Description:
    Hint is an header-only arbitrary size integer API with strong semantics for C++. Multiple backends are provided using various HLS libraries, allowing a user to write one operator and synthetize it using the main vendor tools.
  • URL:
  • Publication:
  • Contact:
    Luc Forget
  • Participants:
    Yohann Uguen, Florent de Dinechin, Luc Forget

7.1.6 Syfala

  • Name:
    Low-Latency Synthesizer on FPGA
  • Keywords:
    FPGA, Compilers, High-level synthesis, Audio signal processing
  • Functional Description:

    The goal of Syfala is to design an FPGA-based platform for multichannel ultra-low-latency audio Digital Signal Processing programmable at a high-level with Faust and usable for various applications ranging from sound synthesis and processing to active sound control and artificial sound field/room acoustics.

    A series of tools are currently being developed around SyFaLa. While none of them has been officially released yet, you can follow their development/evolution on the project Git repository: https://gitlab.inria.fr/risset/syfala

  • URL:
  • Contact:
    Tanguy Risset

8 New results

8.1 Flexible Radio Front-End

Activities in this axis could globally be divided in three main topics: wake-up radio and wireless power transfer, RFID systems and combination of spatial modulation and full-duplex, but also some other related topics.

8.1.1 Wake-Up radio and wireless power transfer

A large survey on Energy Harvesting architectures and used diodes with a large set of simulations to evaluate the impact of the chosen frequency band was published 7. This survey was used to develop a new solution to build a completely autonomous Wake-Up radio device using Energy Harvesting to feed the Wake-Up circuit 6. In parallel, we have started the ANR project U-Wake, dedicated to build an autonomous Wake-Up device based on artificial neural networks. We also have continued our work on optimizing the waveform for optimal Wireless Power Transfer (WPT).

8.1.2 RFID

To integrate RFID capabilities in textiles, we proposed an alternative to the current RFID yarn solution with the use of an antenna having a helical geometry that answers to the mechanical issues and keeps quite similar electrical and radiative properties with respect to the present solution. The RFID helical tag was designed and simulated taking into consideration the constraints of the manufacturing process. The helical RFID tag was then fabricated using the E-Thread® technology and experimental characterization showed that the obtained structure exhibited good performance with 10.6 m of read range in the ultra high frequency (UHF) RFID band and 10 percents of tolerance in terms of elongation 38. For tag-to-tag communications, we proposed a source orientation optimization to increase the modulation depth and therefore to reduce the bit-error-rate between two tags 12.

8.1.3 Combination of spatial modulation and full-duplex

To increase the realism of our proposed combination of Spatial Modulation and Full-Duplex techniques 16, we have studied the impact of RF non-idealities, and particularly the impact of the Power Amplifier nonlinearities 13. A solution to reduce this impact was proposed.

8.1.4 Other related works

Several works have been performed focusing on the FM RDS technology 4, 11, 14. More precisely, by employing the Radio Data System (RDS) protocol of a local Frequency Modulation (FM) transmission, road traffic's dangerous areas (rail crossing, unmarked crossroads, etc.) could be announced. The code of a warning message is broadcasted in the close vicinity of the dangerous area and, at the receiver side, a corresponding image is displayed on the car's tablet PC.

8.2 Transiently powered systems and Non-Volatile Memory

Socrate has been studying the new NVRAM (Non-Volatile Radom Access Memory) technology and its use in ultra-low power context. Many emerging technologies are forseen for Non-Volatile RAM to replace current RAM  26.

Socrate has studied the applicability of NVRAM for transiently powered systems, i.e. systems which may undergo power outage at any time. This study resulted in the Sytare software  19 which was mainly developped by Gautier Berthou during its PhD 15

Another important outcome was the Inria Project Lab ZEP. The final meeting of ZEP hold on 21th October 2021 and was judged as "very successful" by Inria. Socrate members however have decided to orient their research towards other directions. Kevin Marquet and Guillaume Salagnac are involved in the creation of a team called Phenix focussed on Frugal IT and emancipatory security for a digital transition.

8.3 Creation of the Emeraude Team

Part of the Socrate team is involved in the creation of a new Inria project focussed on Embedded Programmable Audio Systems (Emeraude team proposal) in association with the the researchers of the GRAME group. GRAME is a “Centre National de Création Musicale” (CNCM) organized in three departments: music production, transmission/mediation, and computer music research. Four GRAME researchers have expertise in computer science (compilation), audio DSP, digital lutherie, and human-computer interaction in general. GRAME has been leading the development of the Faust2 programming language since its creation in 2004.

8.3.1 Ultra-low latency audio on FPGA

Figure 4

The complete faust2FPGA studied in future FAST ANR project. The central flow has been prototyped and presented in .

Figure 4: The complete faust2FPGA studied in future FAST ANR project. The central flow has been prototyped and presented in 27.

Socrate and GRAME have started a collaboration through the Syfala(synthèse audio faible latence). whose goal is to design an FPGA-based platform for multichannel ultra-low-latency audio Digital Signal Processing, programmable at high-level with Faust and using Socrate's software FloPoCo. A first very preliminary version of this compiler was presented at IFC2020  27 (see Fig. 4). Then an ANR project was launched in March 2021 (FAST: Fast Audio Signal-processing Technologies on FPGA). This topic became the first research axis of the new Emeraude Team.

8.3.2 Administrative creation of Emeraude

At time of writing, the creation of the Emeraude team has been validated by the Scientific Committee of Inria Lyon. It is already started as an Insa Team, a convention between Grame, Insa-Lyon and Inria has been signed. Emeraude should become the first Inria team created in the new Inria Lyon Center. In June, Romain Michon, researcher at Grame was hired as ISFP at Inria to reinforce the Emeraude project.

The emeraude team proposes to study embedded programmable audio systems. In particular, it is involved in the developpement and distribution of the Faust Language. The four research axis proposed by Emeraude are:

  • Ultra-Low Audio Latency on FPGA
  • Advanced Arithmetics for Digital Audio
  • Digital Audio Signal Processing
  • Language, Compilation, Deployment, and Interfaces for Audio Signal Processing

8.4 Computer arithmetic

8.4.1 Towards Arithmetic-Centered Filter Design

Linear-time invariant (LTI) digital filters are usually specified in the frequency domain. Linearity is at the core of Fourier transforms and other techniques allow us to design time-domain implementions from a frequency-domain specification. However, actual (finite-precision) implementations of LTI filters, in particular recursive ones, are necessarily no longer linear due to rounding errors. This leads to unwanted effects such as limit cycle oscillations. As a nice side effect of this definition, filter design and implementation become a single well-founded global optimisation problem. Existing tools to solve this problem are reviewed and the missing ones are framed.

8.4.2 Lossless Differential Table Compression for Hardware Function Evaluation

Hsiao et al. recently introduced, in the context of multipartite table methods, a lossless compression technique that replaces a table of numerical values with two smaller tables and one addition. 5 shows that this technique has many more applications than originally published, and that in many of these applications the addition is for free in practice. It also improves this technique and the resulting architecture by exposing a wider implementation space, and an exhaustive but fast algorithm exploring this space. These contributions are implemented in the open-source FloPoCo core generator and evaluated on FPGA and ASIC, reducing area up to a factor 2.

8.4.3 Resource Optimal Truncated Multipliers for FPGAs

In contrast to application specific integrated circuits (ASICs), FPGAs impose some distinct challenges in multiplier design due to many possibilities of computing the partial products using logic-based or DSP-based sub-multipliers. To tackle this, 9 extends to truncated multipliers a previously proposed tiling methodology which translates the multiplier design into a geometrical tiling problem. The tiling with the least resources guaranteeing last-bit accuracy can be found with integer linear programming (ILP). Compared to previous approaches that use a fixed number of guard bits or optimize at the level of the dot diagrams, this allows a much better use of sub-multipliers resulting in significant area savings without sacrificing the timing.

9 Bilateral contracts and grants with industry

9.1 Bilateral contracts with industry

Research Contract with Bosch 2021

In collaboration with Aric, Socrate worked with Bosch on the implementation of the square root function the context of an embedded processor.

10 Partnerships and cooperations

10.1 National initiatives

Insa-Spie IoT Chair

The Insa-Spie IoT Chair  relies on the expertise of the CITI Lab. The skills developed within the different teams of the lab integrate the study, modelling, conception and evaluation of technologies for communicating objects and dedicated network architectures. It deals with network, telecom and software matters as well as societal issues such as privacy. The chair will also lean on the skills developed at INSA Lyon or in IMU LabEx.

Inria Project Lab: ZEP

The ZEP project addresses the issue of designing tiny computing objects with no battery by combining non-volatile memory (NVRAM), energy harvesting, micro-architecture innovations, compiler optimizations, and static analysis. The main application target is Internet of Things (IoT) where small communicating objects will be composed of this computing part associated to a low-power wake-up radio system. The ZEP project gathers four INRIA teams that have a scientific background in architecture, compilation, operating system and low power together with the CEA Lialp and Lisan laboratories of CEA LETI & LIST.

Figure 5.a
Figure 5.b
Figure 5: Example of system targeted by the ZEP project on the left, and on the right: the ZEP research program.

The scientific work (in progress) is organized around three fields :

  • specific NVRAM-based architecture
  • dedicated compiler pass that computes a worst-case energy consumption
  • operating system managing NVRAM and energy, ensuring memory consistency across power outages

The project is illustrated by the figure 5, where PACAP, SOCRATE, CORSE, and CAIRN are the teams involved in the project.

ANR - Imprenum

The objective of this project (INSA-Lyon, École Normale Supérieure de Lyon, CEA LETI) is to promote accuracy as a first class concern in all the levels of a computing system:

  • at the hardware level, with better support for lower-than-standard and higher-than-standard precisions;
  • at the level of run-time support software, in particular answering the memory management challenges entailed by adaptive precision;
  • at the lower level of mathematical libraries (kernel level), for instance BLAS for linear algebra, enhancing well established libraries with precision and accuracy control;
  • at the higher level of mathematical libraries (solver level, including algebraic linear solvers such as LAPACK, ad hoc steppers for Ordinary Differential Equation, eigenvalues kernels, triangularization problems for computational geometry, etc.) Here, accuracy and precision control of the lower levels should enable higher-level properties such as convergence and stability;
  • at the compiler level, enhancing optimising compilers with novel optimisations related to precision and accuracy;
  • at the language level, embedding accuracy specification and control in existing languages, and possibly defining domain-specific languages with accuracy-aware semantics for some classes of applications.


The main objective of The FAST ANR project started in March 2021 is to develop a new Faust architecture backend for FPGA-based platforms. One of the challenges here is the optimization of the module generated by Faust. The real breakthrough will be obtained with the use of two recent technologies in the Faust compilation workflow:

  • High Level Synthesis (HLS) for compiling Faust program to VHDL
  • fixed-point support in the code generated by the Faust compiler, building on the expertise developed at CITI around the FloPoCo project. Eventually, we aim at generating VHDL code directly from the Faust compiler.

This type of system has a wide range of applications in multiple domains. As mentioned earlier, music technology is in high demand for low latency because it helps increasing the playability of musical instruments on stage. Hence, the platform developed as part of FAST will be used to design programmable digital musical instruments and effect processors. In that context, the computational power of the FPGA will be exploited to run complex algorithms (e.g., physics-based models of musical instruments, modal reverbs, etc.) that are too costly to run on a traditional platform (i.e., laptop, etc.).



The objective of this ADT is to continue the engineering support for the development of the Syfala tools for the compilation from high level languages (C, Faust) to FPGA for audio signal processing applications.

This work will be done in the forthcoming Emeraude Inria team and the engineer will be a very important support for the tool development in the team (Syfala of course but also FloPoCo or Faust for instance).

Digital Hardware AI Architectures


Florent de Dinechin participates to the chair Digital Hardware AI Architectures held by Prof. Frédéric Pétrot at the Multidisciplinary Institute in Artificial Intelligence (MIAI) of Grenoble. The other participants are François Duhem (Spintec/CEA) and Fabrice Rastello (LIG/Inria), with industrial partners Google France, Kalray, STMicroelectronics, and Upmem.

This chair funds the PhD of Maxime Christ, which studies how very low-precision arithmetic formats may improve the efficiency of the learning phase of neural networks.



Our U-Wake project aims to achieve a breakthrough in the field of IoT by developing a disruptive wake-up receiver solution based on (1) a bioinspired architecture achieved with an industrial CMOS technology (with transistors operating in deep sub-threshold regime) and (2) ElectroMagnetic energy harvesting. The originality lies in the association of a Radio Frequency (RF) demodulator to a neuro-inspired detector [2] [3] and data-processing through a spiking neural network (SNN), resulting in a complete ultra-low power wake-up radio supplied with a voltage of a few 100 mV.

CIG Project IMMUNet


The IMMUNet (Industrial Machine Monitoring Unplugged Network) innovation allows to effectively sense the current condition and track the activities of the industrial machines in real time. IMMUNet comprises miniature (1-2 cm2) tags and one or several gateways (GWs) controlling the network and collecting the data. The tags can be powered with a battery, by collecting the energy from the environment or through delivering the energy wirelessly. A tag is equipped with one or multiple sensors (acceleration, temperature, etc.) and has memory to store the relevant technical information about the machine, its activities, and environment. The dependable connectivity between the tags and the GWs is automatically established and maintained through the ultra energy-efficient wireless connectivity protocol based on a combination of time and frequency multiple access (TDMA and FDMA) schemes implemented by GWs and tags firmware. The protocol operates on top of LoRa-modulated radio-signals transmitted in the 2.4 GHz frequency band, allowing the solution to be used anywhere around the globe. In case of poor connectivity, multi-hop transmissions can also be enabled.

11 Dissemination

Chair of conference program committees
  • Florin Hutu and Guillaume Villemaud were session chairs during the 11th IEEE international Conference on RFID Technology and Applications (IEEE RFID-TA 2021).
Member of the conference program committees
  • Florin Hutu was member of the TPC for the 2021 International Conference on Advanced Technologies for Communications, October 2021.
  • Florin Hutu is member of the technical program committee for the joint EuCNC (European Conference on Networks and Communications) and 6G Summit, June 2022.
  • Guillaume Villemaud was a member of the technical program committee for the joint EuCNC (European Conference on Networks and Communications) and 6G Summit, June 2021.
  • Guillaume Villemaud was a member of the technical program committee for IEEE PIMRC 2021.
  • Tanguy Risset was a member of the program committee for DATE 2021 (Design Automation and Test in Europe), on track " Architectural and Microarchitectural Design".
  • Florent de Dinechin was a member of the program committee for ARITH (International Symposium on Computer Arithmetic), FCCM (FPGA-based custom-computing machines), and FPT (Field-Programmable Technologies).

11.0.1 Journal

Member of the editorial boards
  • Florin Hutu and Guillaume Villemaud are Topical Advisory Panel Members of the MDPI Sensors.
Reviewer - reviewing activities
  • Florin Hutu was a reviewer for the following journals: IEEE Transactions on Green Communications and Networking, IEEE Journal of RFID, IEEE Sensor Letters, MDPI Energies, MDPI Sensors, MDPI Signals.
  • Florent de Dinechin was a reviewer for the following journals: ACM Transactions on Reconfigurable Technology and Systems, IEEE Transactions on Computers, IEEE Transactions on Emerging Topics in Computing, AEÜ - International Journal of Electronics and Communications.

11.0.2 Invited talks

Florent de Dinechin gave a keynote at the Mathematical modeling and supercomputer technologies conference (Nizhniy Novgorod, november 2021) and an invited lecture at the joint ICTP-IAEA School FPGA-based SoC and its Applications for Nuclear and Related Instrumentation (Trieste, january 2021)

11.0.3 Leadership within the scientific community

Guillaume Villemaud is vice-president of Commission C for URSI-France.

11.1 Teaching - Supervision - Juries

11.1.1 Teaching

  • Tanguy Risset is professor at the Telecommunications Department of Insa Lyon.
  • Florent de Dinechin is a professor at the Computer Science Department of Insa Lyon. He also teaches computer architecture at ENS-Lyon.
  • Guillaume Salagnac and Kevin Marquet are associate professors at the Computer Science Department of Insa Lyon.
  • Guillaume Villemaud and Florin Hutu are associate professors at the Electrical Engineering Department of Insa Lyon.

11.1.2 Supervision

  • PhD defended in 2021: Gautier Berthou : Operating system for transiently powered systems, Inria, (IPL ZEP) since 01/2018.
  • PhD defended in 2021 :Yanni Zhou : Full Duplex and spatial modulation since 10/2018
  • PhD in progress : Luc Forget : Algèbre linéaire calculant au plus juste, ANR Imprenum, since 10/2018.
  • PhD in progress : Tarik Lassouaoui : Tag 2 Tag communication since 10/2018
  • PhD in progress : Regis Rousseau : Wireless Power Transfer since 10/2018
  • PhD in progress : Maxime Christ : Learning in Very Low Precision since 10/2018
  • PhD starting : Maxime Popoff : Compilation of Audio Program on FPGA since 10/2020

11.1.3 Juries

  • Tanguy Risset was a member of the jury of the following theses:
    • Thomas Baumela (reviewer, U. Grenoble)
    • Arash Shafiei (reviewer and jury president, U. Grenoble)

12 Scientific production

12.1 Major publications

  • 1 articleR. G.Radu Gabriel Bozomitu, F. D.Florin Doru Hutu and N.Nicolas De Pinho Ferreira. Drivers’ Warning Application Through Image Notifications on the FM Radio Broadcasting Infrastructure.IEEE Access9January 2021, 13553 - 13572
  • 2 articleM.Maxime Christ, L.Luc Forget and F.Florent de Dinechin. Lossless Differential Table Compression for Hardware Function Evaluation.IEEE Transactions on Circuits and Systems II: Express BriefsNovember 2021

12.2 Publications of the year

International journals

International peer-reviewed conferences

  • 8 inproceedingsS.Sofia Benouakta, F.Florin Hutu and Y.Yvan Duroc. Passive UHF RFID Yarn For Temperature Sensing Applications.RFID-TA 2021 - 11th IEEE international Conference on RFID Technology and ApplicationsDehli, IndiaIEEEOctober 2021, 1-3
  • 9 inproceedingsA.Andreas Böttcher, M.Martin Kumm and F.Florent De Dinechin. Resource Optimal Truncated Multipliers for FPGAs.ARITH 2021 - 28th IEEE International Symposium on Computer ArithmeticTorino, ItalyIEEEJune 2021, 1-8
  • 10 inproceedingsF.Florent De Dinechin, S.-I.Silviu-Ioan Filip, M.Martin Kumm and A.Anastasia Volkova. Towards Arithmetic-Centered Filter Design.ARITH 2021 - 28th IEEE Symposium on Computer ArithmeticTorino, ItalyJune 2021, 1-4
  • 11 inproceedingsF. D.Florin Doru Hutu and R. G.Radu Gabriel Bozomitu. Driver's warning notifications by using FM RDS technology.ISSCS 2021 - International Symposium on Signals, Circuits and SystemsIasi, RomaniaJuly 2021, 1-4
  • 12 inproceedingsT.Tarik LASSOUAOUI, F.Florin Hutu, G.Guillaume Villemaud and Y.Yvan Duroc. Modulation Depth Enhancement for Randomly Arranged Tags in Passive RFID Tag to Tag Communications.RFID-TA 2021 - 11th IEEE International Conference on RFID Technology and ApplicationsDelhi, IndiaIEEEOctober 2021, 1-4
  • 13 inproceedingsY.Yanni Zhou, F.Florin Hutu, G.Guillaume Villemaud and T.Taneli Riihonen. Nonlinear Power Amplifier Effects on a Full Duplex Spatial Modulation System.PIMRC 2021 - IEEE 32nd Annual International Symposium on Personal, Indoor and Mobile Radio CommunicationsOulu / Virtual, FinlandIEEESeptember 2021, 1-5

Conferences without proceedings

Doctoral dissertations and habilitation theses

  • 15 thesisG.Gautier Berthou. Operating system dedicated to NVRAM-based low power embedded systems.Université de LyonMarch 2021
  • 16 thesisY.Yanni Zhou. On the performance of spatial modulation and full Duplex radio architectures.Université de LyonDecember 2021

12.3 Cited publications

  • 17 articleI.I.F. Akyildiz, W.-Y.Won-Yeol Lee, M.M.C. Vuran and S.S. Mohanty. A survey on spectrum management in cognitive radio networks.Communications Magazine, IEEE464April 2008, 40 -48
  • 18 techreportG.Gautier Berthou, T.Tristan Delizy, K.Kevin Marquet, T.Tanguy Risset and G.Guillaume Salagnac. Peripheral State Persistence For Transiently Powered Systems.RR-9018INRIA02 2017
  • 19 articleG.Gautier Berthou, T.Tristan Delizy, K.Kevin Marquet, T.Tanguy Risset and G.Guillaume Salagnac. Sytare: a Lightweight Kernel for NVRAM-Based Transiently-Powered Systems.IEEE Transactions on Computers689September 2019, 1390 - 1403
  • 20 miscK.K. Biesecker, J.J. Dobiac, N.N. Fekadu, M.M. Jones, C.C. Kain and K.K. Raman. Software Defined Radio Roadmap.Noblis Technical Report, for National Institute of Justice, USA2008
  • 21 techreportP.Pierre Boulet, S.S Bouveret, A.A Bugeau, E.E Frenoux, J.Julien Lefevre, A.-L.Anne-Laure Ligozat, K.Kevin Marquet, P.Philippe Marquet, O.Olivier Michel and O.O Ridoux. Référentiel de connaissances pour un numérique éco-responsable.EcoInfoSeptember 2020
  • 22 phdthesisT.Tristan Delizy. Gestion de la mémoire dynamique pour les systèmes embarqués avec mémoire hétérogène.PhD thesisUniversité de LyonDecember 2019
  • 23 miscEquipex. Future internet of things.2011, URL: http://fit-equipex.fr/
  • 24 articleJ. M.Joseph Mitola III. Software radios: Survey, critical evaluation and future directions.Aerospace and Electronic Systems Magazine, IEEE84Apr 1993, 25-36
  • 25 inproceedingsJ. M.Joseph Mitola III. The software radio.IEEE National Telesystems Conference1992
  • 26 articleJ. S.Jagan Singh Meena, S. M.Simon Min Sze, U.Umesh Chand and T.-Y.Tseung-Yuen Tseng. Overview of emerging nonvolatile memory technologies.Nanoscale Research Letters92014, 526
  • 27 inproceedingsT.Tanguy Risset, R.Romain Michon, Y.Yann Orlarey, S.Stéphane Letz, G.Gero Müller and A.Adeyemi Gbadamosi. Faust2FPGA for Ultra-Low Audio Latency: Preliminary work in the Syfala project.IFC 2020 - Second International Faust ConferenceInternationnal Faust ConferenceParis, FranceDecember 2020, 1-9
  • 28 miscP.Peter Steenkiste, D.Douglas Sicker, G.Gary Minden and D.Dipankar Raychaudhuri. Future Directions in Cognitive Radio Network Research.NSF Workshop Report2009
  • 29 articleM.M. Weiser. The computer for the 21st Century.Pervasive Computing, IEEE991January 2002, 19 -25
  • 30 inproceedingsQ.Qi Zhang, F. H.Frank H. P. Fitzek and V. B.Villy B\aek Iversen. Cognitive radio MAC protocol for WLAN.Proceedings of the IEEE 19th International Symposium on Personal, Indoor and Mobile Radio Communications, PIMRC2008, 1-6
  1. 1In this context, ip stand for Intellectual Properties, this term is widely used to designated dedicated special-purpose circuit blocks implemented in various technologies: Asic, fpga, dsp, etc.
  2. 2Faust is a domain specific language for real-time audio signal processing primarily developed at GRAME-CNCM and by a worldwide community. Faust is based on a compiler “translating” DSP specifications written in Faust into a wide range of lower-level languages (e.g., C, C++, Rust, Java, WASM, LLVM bitcode, etc.). Thanks to its “architecture” system, generated DSP objects can be embedded into template programs (wrappers) used to turn a Faust program into a specific ready-to-use object (e.g., standalone, plug-in, smartphone app, webpage, etc.).