2023Activity reportProject-TeamSPADES

6.1.1 CertiCAN

• Name:
  Certifier of CAN bus analysis results
• Keywords:
  Certification, CAN bus, Real time, Static analysis
• Functional Description:
  CertiCAN is a tool, produced using the Coq proof assistant, allowing the formal certification of the correctness of CAN bus analysis results. Result certification is a process that is light-weight and flexible compared to tool certification, which makes it a practical choice for industrial purposes. The analysis underlying CertiCAN, which is based on a combined use of two well-known CAN analysis techniques, is computationally efficient. Experiments demonstrate that CertiCAN is able to certify the results of RTaW-Pegase, an industrial CAN analysis tool, even for large systems. Furthermore, CertiCAN can certify the results of any other RTA tool for the same analysis and system model (periodic tasks with offsets in transactions).
• URL:
  https://­team.­inria.­fr/­spades/­certican/
• Authors:
  Xiaojie Guo, Pascal Fradet, Sophie Quinton
• Contact:
  Xiaojie Guo

6.1.2 cloudnet

• Name:
  Cloudnet
• Keywords:
  Cloud configuration, Tosca, Docker Compose, Heat Orchestration Template, Alloy
• Scientific Description:

  The multiplication of models, languages, APIs and tools for cloud and network configuration management raises heterogeneity issues that can be tackled by introducing a reference model. A reference model provides a common basis for interpretation for various models and languages, and for bridging different APIs and tools. The Cloudnet Computational Model formally specifies, in the Alloy specification language, a reference model for cloud configuration management. The Cloudnet software formally interprets several configuration languages in it, including the TOSCA configuration language, the OpenStack Heat Orchestration Template and the Docker Compose configuration language.

  The use of the software shoes, for examples, how the Alloy formalization allowed us to discover several classes of errors in the OpenStack HOT specification.

• Functional Description:

  Application of the Cloudnet model developed by Inria to software network deployment and reconfiguration description languages.

  The Cloudnet model allows syntax and type checking for cloud configuration templates as well as their visualization (network diagram, UML deployment diagram). Three languages are addressed for the moment with the modules:

  * Cloudnet TOSCA toolbox for TOSCA inncluding NFV description * cloudnet-hot for HOT (Heat Orchestration Template) from OpenStack * cloudnet-compose for Docker Compose

  We can use directly the software from an Orange web portal: https://toscatoolbox.orange.com

• URL:
  https://­github.­com/­Orange-OpenSource/­Cloudnet-TOSCA-toolbox
• Publication:
  hal-02940938v1
• Contact:
  Philippe Merle
• Participants:
  Philippe Merle, Jean-bernard Stefani, Roger Pissard-Gibollet, Souha Ben Rayana, Karine Guillouard, Meryem Ouzzif, Frédéric Klamm, Jean-Luc Coulin
• Partner:
  Orange Labs

6.1.3 LDDL

• Name:
  Coq proofs of circuit transformations for fault-tolerance
• Keywords:
  Fault-tolerance, Transformation, Coq, Semantics
• Functional Description:

  We have developied a Coq-based framework to formally verify the functional and fault-tolerance properties of circuit transformations. Circuits are described at the gate level using LDDL, a Low-level Dependent Description Language inspired from muFP. Our combinator language, equipped with dependent types, ensures that circuits are well-formed by construction (gates correctly plugged, no dangling wires, no combinational loops, ...). Fault-tolerance techniques can be described as transformations of LDDL circuits.

  The framework has been used to prove the correctness of three fault-tolerance techniques for SETs (Single Event Transients): TMR (the classic triple modular redundancy) and two new time redundancy techniques developped within the Spades team: TTR and DTR. More recently, LDDL has been used to prove the correctness of TMR+, a modified TMR able to tolerate SEMTs (Single Event Multiple Transients) a more involved type of faults.

  The specifications of the framework (LDDL syntax and semantics, libraries, tactics) are made of 5000 lines of Coq (excluding comments and blank lines). The correctness proofs of fault-tolerance techniques are made of 700 lines of Coq for TMR, 700 for TMR+, 3500 for TTR and 7000 for DTR.

• URL:
  https://­team.­inria.­fr/­spades/­fthwproofs/
• Authors:
  Pascal Fradet, Dmitry Burlyaev, Vincent Bonczak
• Contact:
  Pascal Fradet

6.1.4 MASTAG

• Name:
  Memory Analyzer and Scheduler for Task Graphs
• Keyword:
  Task scheduling
• Functional Description:

  The MASTAG software computes sequential schedules of a task graph or an SDF graph in order to minimize its memory peak.

  MASTAG is made of several components: (1) a set of local transformations that compress a task graph while preserving its optimal memory peak, (2) an optimized branch and bound algorithm able to find optimal schedules for medium sized (30-50 nodes) task graphs, (3) support to accommodate SDF graphs in particular, their conversion into task graphs and a suboptimal technique to reduce their size.

  MASTAG finds optimal schedules in polynomial time for a wide range of directed acyclic task graphs (DAG), including trees and series-parallel DAG. On classic benchmarks, MASTAG always outperforms the state-of-the-art.

• URL:
  https://­gitlab.­inria.­fr/­spades-pub/­mastag
• Authors:
  Alexandre Honorat, Pascal Fradet, Alain Girault
• Contact:
  Alexandre Honorat

7.1.1 Dynamicity in dataflow models

Dataflow Models of Computation (MoCs) are widely used in embedded systems, including multimedia processing, digital signal processing, telecommunications, and automatic control. One of the first and most popular dataflow MoCs, Synchronous Dataflow (SDF), provides static analyses to guarantee boundedness and liveness, which are key properties for embedded systems. However, SDF and most of its variants lack the capability to express the dynamism needed by modern streaming applications.

For many years, the Spades team has been working on more expressive and dynamic models that nevertheless allow the static analyses of boundedness and liveness. We have proposed several parametric dataflow models of computation (MoCs) (SPDF  39 and BPDF  31), we have written a survey providing a comprehensive description of the existing parametric dataflow MoCs  34, we have studied symbolic analyses of dataflow graphs  35 and an original method to deal with lossy communication channels in dataflow graphs  38. We have also proposed the RDF (Reconfigurable Dataflow) MoC  3 which allows dynamic reconfigurations of the topology of the dataflow graphs. RDF extends SDF with transformation rules that specify how the topology and actors of the graph may be dynamically reconfigured. The major feature and advantage of RDF is that it can be statically analyzed to guarantee that all possible graphs generated at runtime will be connected, consistent, and live, which in turn guarantees that they can be executed in bounded time and bounded memory. To the best of our knowledge, RDF is the only dataflow MoC allowing an arbitrary number of topological reconfigurations while remaining statically analyzable.

In 2022, we started an exploratory action (see Section 9.2) to study the potential of dataflow MoCs for the implementation of neural networks. We started by working on the reduction of the memory footprint of tasks graphs scheduled on unicore processors. This is motivated by the fact that some recent neural networks such as GPT-3, seen as tasks graphs, use too much memory and cannot fit on a single GPU.

We have proposed graph transformations that compress the given task graph while preserving its optimal memory peak. We have proved that these transformations always compress Series-Parallel Directed Acyclic Graphs (SP-DAGs) to a single node representing their optimal schedule 18. For graphs that cannot be compressed to a single node, we have designed an optimized branch and bound algorithm able to find optimal schedules for medium sized (30-50 nodes) task graphs. Our approach also applies to SDF graphs after converting them to task graphs. However, since that conversion may produce very large graphs, we also propose a new suboptimal method, similar to Partial Expansion Graphs, to reduce the problem size. We evaluated our approach on classic benchmarks, on which we always outperform the state-of-the-art.

Another technique used by memory greedy neural networks is activity and gradient checkpointing (a.k.a. rematerialization), which recomputes intermediate values rather than keeping them in memory. We are currently studying rematerialization in the more general dataflow framework.

We have published a comprehensive paper about the Affine DataFlow Graph (ADFG) theory and software 13. ADFG synthesizes task periods of real-time embedded applications modeled by SDF graphs. This paper concludes 10 years of work on the ADFG open-source software.

We have applied the ADFG theory to the domain of reconfigurable processors (FPGA) 12. With the help of a few new equations, the theory of ADFG is adapted to minimize the buffer sizes of dataflow applications modeled by SDF graphs and executed on FPGA. This is particularly important for FPGAs which have a limited embedded memory. The corresponding open-source software PREESM is developped at INSA Rennes.

7.1.2 The ForeC time-predictable programming language

Embedded real-time systems are tightly integrated with their physical environment. Their correctness depends both on the outputs and timeliness of their computations. The increasing use of multi-core processors in such systems is pushing embedded programmers to be parallel programming experts. However, parallel programming is challenging because of the skills, experiences, and knowledge needed to avoid common parallel programming traps and pitfalls. We have proposed the ForeC synchronous multi-threaded programming language for the deterministic, parallel, and reactive programming of embedded multi-cores. The synchronous semantics of ForeC is designed to greatly simplify the understanding and debugging of parallel programs. ForeC ensures that ForeC programs can be compiled efficiently for parallel execution and be amenable to static timing analysis. ForeC's main innovation is its shared variable semantics that provides thread isolation and deterministic thread communication. All ForeC programs are correct by construction and deadlock free because no non-deterministic constructs are needed. We have benchmarked our ForeC compiler with several medium-sized programs (e.g., a $2.274$-line ForeC program with up to 26 threads and distributed on up to 10 cores, which was based on a $2.155$-line non-multi-threaded C program). These benchmark programs show that ForeC can achieve better parallel performance than Esterel, a widely used imperative synchronous language for concurrent safety-critical systems, and is competitive in performance to OpenMP, a popular desktop solution for parallel programming (which implements classical multi-threading, hence is intrinsically non-deterministic). We also demonstrate that the worst-case execution time of ForeC programs can be estimated to a high degree of precision 15.

This topic has been a long-run effort, since we started working on ForeC in 2013 in the context of the PhD of Eugene Yip  61. It took time to finalize this work, with the ultimate contribution in 2019 on multi-clock ForeC programs  45, paving the way for the long version article published in 2023 15.

7.2.1 A Markov Decision Process approach for energy minimization policies

Since 2017 we have been working on a very general model of real-time systems, made of a single-core processor equipped with DVFS and an infinite sequence of preemptive real-time jobs. Each job $J_i$ is characterized by the triplet $({\tau }_i,w_i,d_i)$, where ${\tau }_i$ is the inter-arrival time between $J_i$ and $J_{i-1}$, $w_i$ is the actual size of $J_i$, upper-bounded by the maximal size $W$, and $d_i$ is the relative deadline of $J_i$, upper-bounded by $\Delta$. The key point is that the system is non-clairvoyant, meaning that, at release time, $w_i$ is not known until the job $J_i$ actually terminates. What is available to the processor are the statistical information on the jobs' characteristics: release time, AET, and relative deadline. In this context, we have proposed a Markov Decision Process (MDP) solution to compute the optimal online speed policy guaranteeing that each job completes before its deadline and minimizing the energy consumption. To the best of our knowledge, our MDP solution is the first to be optimal. We have also provided counter examples to prove that the two previous state of the art algorithms, namely OA  60 and PACE  52, are both sub-optimal. Finally, we have proposed a new heuristic online speed policy called Expected Load (EL) that incorporates an aggregated term representing the future expected jobs into a speed equation similar to that of OA. A journal paper is currently under review.

Simulations show that our MDP solution outperforms the existing online solutions (OA, PACE, and EL), and can be very attractive in particular when the mean value of the execution time distribution is far from the WCET.

This was the topic of Stephan Plassart's PhD  5741, 43, 42, funded by the Caserm Persyval project, who defended his PhD in June 2020.

7.2.2 Formal proofs for schedulability analysis of real-time systems

We contribute to Prosa 27, a Coq library of reusable concepts and proofs for real-time systems analysis. A key scientific challenge is to achieve a modular structure of proofs, e.g., for response time analysis. Our goal is to use this library for:

1. the formal specification of real-time concepts;
2. a better understanding of the role played by some assumptions in existing proofs;
3. a formal verification and comparison of different analysis techniques; and

4. the certification of (results of) existing analysis techniques or tools.

We have developed CertiCAN, a tool produced using the Coq proof assistant, allowing the formal certification of CAN bus analysis results. CertiCAN is able to certify the results of industrial CAN analysis tools, even for large systems. We have described this work in a long journal article 11.

The work on the formalization in Prosa of Compositional Performance Analysis is still ongoing.

7.3.1 Causal Explanations for Embedded Systems

Model-Based Diagnosis of discrete event systems (DES) usually aims at detecting failures and isolating faulty event occurrences based on a behavioural model of the system and an observable execution log. The strength of a diagnostic process is to determine what happened that is consistent with the observations. In order to go a step further and explain why the observed outcome occurred, we borrow techniques from causal analysis. We are currently exploring techniques that are able to extract, from an execution trace, the causally relevant part for a property violation.

In particular, as part of the SEC project, we are investigating how such techniques can be extended to classes of hybrid systems. As a first result we have studied the problem of explaining faults in real-time systems  53. We have provided a formal definition of causal explanations on dense-time models, based on the well-studied formalisms of timed automata and zone-based abstractions. We have proposed a symbolic formalization to effectively construct such explanations, which we have implemented in a prototype tool. Basically, our explanations identify the parts of a run that move the system closer to the violation of an expected safety property, where safe alternative moves would have been possible.

We have recently generalized the work of  53 and defined robustness functions as a family of mappings from system states to a scalar that, intuitively, associate with each state its distance to the violation of a given safety requirement, e.g., in terms of the remaining number of bad system moves or of the time remaining to react. An explanation then summarizes the portions of the execution on which robustness decreases. However, as our instantiation of robustness in  53 is defined on a discrete abstraction, robustness may decrease in discrete steps once some timing threshold is crossed, thus exonerating the preceding absence of action. We are currently working on a truly hybrid definition of robustness functions that “anticipate” such thresholds, hence ensuring a smooth decrease indicating early when a dangerous event is approaching.

7.3.2 Causal Explanations in Concurrent Programs

As part of the DCore project on causal debugging of concurrent programs, the goal of Aurélie Kong Win Chang's PhD thesis is to investigate the use of abstractions to construct causal explanations for Erlang programs. We are interested in developing abstractions that "compose well" with causal analyses, and understanding precisely how explanations found on the abstraction relate to explanations on the concrete system. It is worth noting that the presence of abstraction, which inherently comes with some induction and extrapolation processes, completely recasts the issue of reasoning about causality. Causal traces do no longer describe only potential scenarios in the concrete semantics, but also mix some approximation steps coming from the computation of the abstraction itself. Therefore, not all explanations are replayable counter-examples: they may contain some steps witnessing some lack of accuracy in the analysis. Vice versa, a research question to be addressed is how to define causal analyses that have a well understood behavior under abstraction.

In 19 we have formalized a small step semantics for a subset of Core Erlang that models, in particular, its monitoring and signal systems. Having a precise representation of these aspects is crucial to explain unexpected behaviors such as concurrency bugs stemming from non-determinism in the handling of messages.

We are currently working on a formalization of an abstract Erlang semantics that allows for a finite abstraction while still accounting for the exchanges of messages and signals between processes.

7.3.3 Reversibility for concurrent and distributed debugging

Concurrent and distributed debugging is a promising application of the notion of reversible computation  44. As part of the ANR DCore project we contribute to the theory behind, and the developoment of the CauDEr reversible debugger for the Erlang programming language and system.

We have continued this year our work on two main themes: studying reversibility for distributed programs in presence of node and link failures with recovery, and studying reversibility for concurrent programs using a shared memory concurrency model.

Concerning reversibility for distributed programs, we have developed a novel process calculus, called D$\pi$FR 26. D$\pi$FR provides a good basis for formally modeling Erlang distribution, including the behaviour of Erlang systems in presence of crash failure and recovery for nodes and links. We have developed a full behavioral theory for D$\pi$FR, in the form of a weak observational equivalence, which we have proved fully abstract with respect to the contextual equivalence for the calculus. This work is under submission for publication. We have also started studying reversibility in D$\pi$FR, considering in particular the difficult case where node failures imply the loss of causality information in the reversible operational semantics.

Concerning reversibility for shared memory concurrency, we have developed a modular operational semantics framework for defining different shared memory concurrency models, including various lock-based weak memory models and transactional memory models. We have proved strong equivalence results between the original formal operational semantics of these different memory models and the operational semantics obtained using our framework. We have also started working on a general theory for reversing synchronization products of transition systems with independence with the hope to directly apply it to our shared memory framework.

7.3.4 A certified fault-tolerance technique for SEMTs

Digital circuits are subject to transient faults caused by high-energy particles. As technology scales down, a single particle becomes likely to induce transients faults in several adjacent components. These single-event multiple transients (SEMTs) are becoming a major issue for modern digital circuits.

We have studied how to formalize SEMTs and how the standard triple modular redundancy (TMR) technique can be modified so that, along with some placement constraints, it completely masks SEMTs 25. We specified this technique, denoted by TMR+, as a circuit transformation on the LDDL syntax (see 6.1.3) and the fault models for SEMTs as particular semantics of LDDL. We show that, for any circuit, its transformation by TMR+ masks all faults of the considered SEMT fault model. All this development was formalized in the Coq proof assistant where fault-tolerance properties are expressed and formally proved.

9.1.1 ANR

9.1.2 Défi Inria

DF4DL

Participants: Pascal Fradet, Alain Girault, Alexandre Honorat.

The DF4DL action is funded by Inria's DGDS. It aims at exploring the use of the dataflow model of computation to better program deep neural networks.

As a first step, we have studied the problem of minimizing the peak memory requirement for the execution of a dataflow graph. This is of paramount importance for deep neural networks since the largest ones cannot fit on a single core due to their very high memory requirement. We have proposed different techniques in order to find a sequential schedule minimizing the memory peak (see 7.1.1).

Another technique used by memory greedy neural networks is rematerialization which recomputes intermediate values rather than keeping them in memory. We are currently studying rematerialization in the dataflow framework.

SIA

Participants: Baptiste De Goer De Herve, Sophie Quinton.

The SIA Exploratory Research project, supported by INRIA's DGDS, funds the PhD work of Baptiste de Goër and provides funding for an upcoming postdoctoral fellow in Sciences and Technology Studies.

The goal of the project is to provide interdisciplinary foundations for studying the complex relationship between computer science, information and communication technologies (ICT), society and the environment. We approach the problem from three complementary perspectives: 1) by contributing to an interdisciplinary overview of the state of knowledge on the environmental impacts of ICT; 2) by studying the complex connection between computer science and the Anthropocene through the way it is and could be taught in secondary schools; 3) by exploring, at a local scale, the possibility to deploy frugal or low tech alternatives to existing digital systems, following a participatory approach.

10.1.1 Scientific events: organisation

10.1.2 Scientific events: selection

10.1.3 Journal

10.1.4 Invited talks

• Sophie Quinton gave invited talks at the DATE 2023 conference, at the SICT summer school as well as at the EEATS doctoral school PhD day and at the Institut Néel in Grenoble.

10.1.5 Leadership within the scientific community

• Sophie Quinton is a member of the ECRTS Advisory Board.
• Sophie Quinton co-chairs a working group of the GDR CIS associated with the Center for Internet and Society focused on environmental issues.

10.1.6 Research administration

• Pascal Fradet is head of the committee for doctoral studies (“Responsable du comité des études doctorale”) of the Inria Grenoble research center. He is the local correspondent for the young researchers Inria mission (“Mission jeunes chercheurs”) and serve as the substitute of the director of the Inria Grenoble research center at the doctoral school council (MSTII).
• Alain Girault is Deputy Scientific Director at Inria for the domain“Algorithmics,Programming,Software and Architecture” (since 2019).
• Alain Girault was president of the Inria Senior Researchers Admission 2023 jury (DR2).
• Gregor Gössler is member of the “commission of scientific jobs” of the Inria Grenoble research center.
• Jean-Bernard Stefani was member of the Inria Grenoble Junior Researches Admissibility 2023 jury (CRCN).
• Sophie Quinton leads the SEnS-GRA group which hosts discussions and proposes actions regarding the environmental and societal impact of our research at Inria Grenoble.
• Sophie Quinton was a member of the CRCN 2023 hiring committee in Rennes.

10.2.1 Teaching

• Licence : Pascal Fradet, Théorie des Langages 1, 18 HeqTD, niveau L3, Grenoble INP (Ensimag), France
• Licence : Pascal Fradet, Modèles de Calcul : $\lambda$-calcul, CM & TD, 30 HeqTD, niveau L3, Univ. Grenoble Alpes, France
• Licence : Xavier Nicollin, Théorie des Langages 1, 40,5 HeqTD, niveau L3. Grenoble INP (Ensimag), France
• Licence : Xavier Nicollin, Théorie des Langages 2, 37,5 HeqTD, niveau L3, Grenoble INP (Ensimag), France
• Licence : Xavier Nicollin, Modèles de Calcul : Machines de Turing, 30 HeqTD, niveau L3, Univ. Grenoble Alpes, France
• Master : Xavier Nicollin, Analyse de Code pour la Sûreté et la Sécurité, 45 HeqTD, niveau M1, Grenoble INP (Ensimag), France
• Master : Xavier Nicollin, Algorithimque et Optimisation Discrète, 18 HeqTD, niveau M1, Grenoble INP (Ensimag), France
• Master : Xavier Nicollin, Fondements Logiques pour l'Informatique, 19,5 HeqTD, niveau M1, Grenoble INP (Ensimag), France
• Licence : Martin Bodin, Modèles de Calcul : $\lambda$-calcul, 12 HeqTD, niveau L3, Univ. Grenoble Alpes, France
• Licence : Martin Bodin, Théorie des Langages 2, 18 HeqTD, niveau L3, Grenoble INP (Ensimag), France
• Licence : Alain Girault, Modèles de Calcul : $\lambda$-calcul, 12 HeqTD, niveau L3, Univ. Grenoble Alpes, France
• Licence : Sophie Quinton contributed to two 3h workshops for first-year students at the Ensimag Engineering School to introduced them to the environmental impacts of ICT.
• École doctorale: Sophie Quinton gave a 3h course "Sciences, environnements, sociétés" at the College des Écoles Doctorales.
• Sophie Quinton co-supervized a one-week sociological study by students from the École des Mines de Paris on water management in the Grenoble area, with a focus on ICT related aspects.

10.2.2 Supervision

• Alain Girault and Sophie Quinton: PhD in progress: Aina Rasoldier, ICT in the Anthropocene: Technical and social challenges at the local scale.
• Gregor Gössler: PhD completed: Thomas Mari, “Construction of Safe Explainable Cyber-physical systems”; Grenoble INP; defended in November 2023; co-advised by Gregor Gössler and Thao Dang.
• Gregor Gössler: PhD in progress: Aurélie Kong Win Chang, "Abstractions for causal analysis and explanations in concurrent programs"; since January 2021; co-advised by Gregor Gössler and Jérôme Feret.
• Gregor Gössler: pre-thesis contract: Alexander Obeid Guzman, "Inference of causal models for networks from single observations"; since November 2023.
• Jean-Bernard Stefani: PhD in progress: Giovanni Fabbretti on reversibility for distributed programs (UGA), Pietro Lami on reversibility for shared memory concurrent programs (UGA and U. Bologna), Boubacar Diarra on verification of Kubernetes configurations (U. Lille).
• Sophie Quinton: PhD in progress: Baptiste de Goër, “Teaching ICT-related sustainability issues in computer science courses”.

10.2.3 Juries

• Alain Girault, President of the PhD jury of Kevin Zagalo, Sorbonne Université; 2023.
• Alain Girault, Invited to the PhD jury of Baptiste Pauget, ENS-PSL; 2023.
• Alain Girault, Examinator in the PhD jury of Lou Grimal, UTT; 2023.

10.3.1 Education

• Martin Bodin and Alain Girault, “Le théorème des quatre couleurs”, Lecture Maths C$2+$ for high-school pupils, Grenoble, June 2023.

10.3.2 Interventions

• Martin Bodin was interviewed on the Twitch channel Chercheur·es de montagne.
• Martin Bodin with Emmanuel Beffara: creation and experimentation of an activity about Logic for the Fête de la science.
• Sophie Quinton was a member of the scientific committee of the GAES (groupe artistique d’exploration scientifique) 2024.
• Sophie Quinton and Baptiste de Goër collaborate with two teachers of the Lycée Stendhal on their project teaching about the environmental impacts of ICT.

International journals

• 11 articleP.Pascal Fradet, X.Xiaojie Guo and S.Sophie Quinton. CertiCAN : Certifying CAN Analyses and Their Results.Real-Time Systems592March 2023, 160-198HALDOIback to text
• 12 articleA.Alexandre Honorat, M.Mickaël Dardaillon, H.Hugo Miomandre and J.-F.Jean-François Nezan. Automated Buffer Sizing of Dataflow Applications in a High-Level Synthesis Workflow.ACM Transactions on Reconfigurable Technology and Systems (TRETS)September 2023, 1-26HALDOIback to text
• 13 articleA.Alexandre Honorat, H. N.Hai Nam Tran, T.Thierry Gautier, L.Loïc Besnard, S. S.Shuvra S. Bhattacharyya and J.-P.Jean-Pierre Talpin. Real-Time Fixed Priority Scheduling Synthesis using Affine DataFlow Graphs: from Theory to Practice.ACM Transactions on Embedded Computing Systems (TECS)August 2023, 1-30HALDOIback to text
• 14 articleG.Gauthier Roussilhe, A.-L.Anne-Laure Ligozat and S.Sophie Quinton. A long road ahead: a review of the state of knowledge of the environmental effects of digitization.Current Opinion in Environmental Sustainability62June 2023, 101296HALDOIback to text
• 15 articleE.Eugene Yip, A.Alain Girault, P. S.Partha S Roop and M.Morteza Biglari-Abhari. Synchronous Deterministic Parallel Programming for Multi-Cores with ForeC.ACM Transactions on Programming Languages and Systems (TOPLAS)452June 2023, 1-74HALDOIback to textback to text

International peer-reviewed conferences

• 16 inproceedingsE.Emmanuel Beffara, M.Martin Bodin, N.Nadine Mandran and R.Rémi Molinier. Instrumentation de l'association de registres sémiotiques dans un assistant de preuve.EIAH2023 - 11ème Conférence sur les Environnements Informatiques pour l'Apprentissage HumainBrest, FranceJune 2023, 1-5HAL
• 17 inproceedingsB.Boubacar Diarra, K.Karine Guillouard, M.Meryem Ouzzif, P.Philippe Merle and J.-B.Jean-Bernard Stefani. In-depth analysis of Kubernetes manifest verification tools for robust CNF deployment.ICIN 2024 - Conference on Innovation in Clouds, Internet and NetworksParis, France2024, 1-8HAL
• 18 inproceedingsP.Pascal Fradet, A.Alain Girault and A.Alexandre Honorat. Sequential Scheduling of Dataflow Graphs for Memory Peak Minimization.Proceedings of the 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES ’23)LCTES 2023 - 24th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, and Tools for Embedded SystemsOrlando (FL), United StatesACMJune 2023, 76-86HALDOIback to text
• 19 inproceedingsA.Aurélie Kong Win Chang, J.Jerome Feret and G.Gregor Gössler. A Semantics of Core Erlang with Handling of Signals.ACM Digital LibraryErlang 2023 - 22nd ACM SIGPLAN International Workshop on ErlangSeattle WA, United StatesACM2023, 31-38HALDOIback to text
• 20 inproceedingsA.Aina Rasoldier, A.Alain Girault, S.Sophie Quinton, J.Jacques Combaz and K.Kevin Marquet. Assessing the Potential of Carpooling for Reducing Vehicle Kilometers Traveled.ICT4S 2023 - 9th International Conference on Information and Communications Technology for SustainabilityRennes, FranceIEEE2023, 120-131HALDOIback to text

National peer-reviewed Conferences

• 21 inproceedingsJ.Jean Abou-Samra, Y.Yannick Zakowski and M.Martin Bodin. Effectful Programming across Heterogeneous Computations -Work in Progress.Journées Francophones des Langages ApplicatifsJFLA 2023 - 34èmes Journées Francophones des Langages ApplicatifsPraz-sur-Arly, France2023, 7-23HAL

Conferences without proceedings

• 22 inproceedingsB.Baptiste de Goër, M.Micha Hersch and S.Sophie Quinton. Informatique et durabilité, une difficile transposition didactique.Didapro 10 - Didactique de l'informatique et des STICLouvain-la-Neuve, BelgiumJanuary 2024HALback to text
• 23 inproceedingsS.Sophie Quinton and J.-B.Jean-Bernard Stefani. Taking conviviality seriously (extended abstract).Undone Computer Science 2024Nantes, FranceFebruary 2024HALback to text

Reports & preprints

• 24 miscC. K.Charles K. Assaad, E.Emilie Devijver, E.Eric Gaussier, G.Gregor Gössler and A.Anouar Meynaoui. Identifiability of total effects from abstractions of time series causal graphs.October 2023HAL
• 25 reportV.Vincent Bonczak and P.Pascal Fradet. A formally verified circuit transformation to tolerate SEMTs.RR-9523Inria Grenoble - Rhône-AlpesOctober 2023, 1-25HALback to text
• 26 reportG.Giovanni Fabbretti, I.Ivan Lanese and J.-B.Jean-Bernard Stefani. A Behavioral Theory For Crash Failures and Erlang-style Recoveries In Distributed Systems.RR-9511InriaJune 2023HALback to text