2023Activity reportProject-TeamPACAP

3.1.1 Technological constraints

Until recently, binary compatibility guaranteed portability of programs, while increased clock frequency and improved micro-architecture provided increased performance. However, in the last decade, advances in technology and micro-architecture started translating into more parallelism instead. Technology roadmaps even predicted the feasibility of thousands of cores on a chip by the 2020's. Hundreds are already commercially available. Since the vast majority of applications are still sequential, or contain significant sequential sections, such a trend puts an end to the automatic performance improvement enjoyed by developers and users. Many research groups consequently focused on parallel architectures and compiling for parallelism.

Still, the performance of applications will ultimately be driven by the performance of the sequential part. Despite a number of advances (some of them contributed by members of the team), sequential tasks are still a major performance bottleneck. Addressing it is still on the agenda of the PACAP project-team.

In addition, due to power constraints, only part of the billions of transistors of a microprocessor can be operated at any given time (the dark silicon paradigm). A sensible approach consists in specializing parts of the silicon area to provide dedicated accelerators (not run simultaneously). This results in diverse and heterogeneous processor cores. Application and compiler designers are thus confronted with a moving target, challenging portability and jeopardizing performance.

Note on technology.

Technology also progresses at a fast pace. We do not propose to pursue any research on technology per se. Recently proposed paradigms (non-Silicon, brain-inspired) have received lots of attention from the research community. We do not intend to invest in those paradigms, but we will continue to investigate compilation and architecture for more conventional programming paradigms. Still, several technological shifts may have consequences for us, and we will closely monitor their developments. They include for example non-volatile memory (impacts security, makes writes longer than loads), 3D-stacking (impacts bandwidth), and photonics (impacts latencies and connection network), quantum computing (impacts the entire software stack).

3.1.2 Evolving community

The PACAP project-team tackles performance-related issues, for conventional programming paradigms. In fact, programming complex environments is no longer the exclusive domain of experts in compilation and architecture. A large community now develops applications for a wide range of targets, including mobile “apps”, cloud, multicore or heterogeneous processors.

This also includes domain scientists (in biology, medicine, but also social sciences) who started relying heavily on computational resources, gathering huge amounts of data, and requiring a considerable amount of processing to analyze them. Our research is motivated by the growing discrepancy between on the one hand, the complexity of the workloads and the computing systems, and on the other hand, the expanding community of developers at large, with limited expertise to optimize and to map efficiently computations to compute nodes.

3.1.3 Domain constraints

Mobile, embedded systems have become ubiquitous. Many of them have real-time constraints. For this class of systems, correctness implies not only producing the correct result, but also doing so within specified deadlines. In the presence of heterogeneous, complex and highly dynamic systems, producing a tight (i.e., useful) upper bound to the worst-case execution time has become extremely challenging. Our research will aim at improving the tightness as well as enlarging the set of features that can be safely analyzed.

The ever growing dependence of our economy on computing systems also implies that security has become of utmost importance. Many systems are under constant attacks from intruders. Protection has a cost also in terms of performance. We plan to leverage our background to contribute solutions that minimize this impact.

Note on Applications Domains.

PACAP works on fundamental technologies for computer science: processor architecture, performance-oriented compilation and guaranteed response time for real-time. The research results may have impact on any application domain that requires high performance execution (telecommunication, multimedia, biology, health, engineering, environment...), but also on many embedded applications that exhibit other constraints such as power consumption, code size and guaranteed response time.

We strive to extract from active domains the fundamental characteristics that are relevant to our research. For example, big data is of interest to PACAP because it relates to the study of hardware/software mechanisms to efficiently transfer huge amounts of data to the computing nodes. Similarly, the Internet of Things is of interest because it has implications in terms of ultra low-power consumption.

3.2.1 Static Compilation

Static compilation techniques continue to be relevant in addressing the characteristics of emerging hardware technologies, such as non-volatile memories, 3D-stacking, or novel communication technologies. These techniques expose new characteristics to the software layers. As an example, non-volatile memories typically have asymmetric read-write latencies (writes are much longer than reads) and different power consumption profiles. PACAP studies new optimization opportunities and develops tailored compilation techniques for upcoming compute nodes. New technologies may also be coupled with traditional solutions to offer new trade-offs. We study how programs can adequately exploit the specific features of the proposed heterogeneous compute nodes.

We propose to build upon iterative compilation 1 to explore how applications perform on different configurations. When possible, Pareto points are related to application characteristics. The best configuration, however, may actually depend on runtime information, such as input data, dynamic events, or properties that are available only at runtime. Unfortunately a runtime system has little time and means to determine the best configuration. For these reasons, we also leverage split-compilation 27: the idea consists in pre-computing alternatives, and embedding in the program enough information to assist and drive a runtime system towards to the best solution.

3.2.2 Software Adaptation

More than ever, software needs to adapt to its environment. In most cases, this environment remains unknown until runtime. This is already the case when one deploys an application to a cloud, or an “app” to mobile devices. The dilemma is the following: for maximum portability, developers should target the most general device; but for performance they would like to exploit the most recent and advanced hardware features. JIT compilers can handle the situation to some extent, but binary deployment requires dynamic binary rewriting. Our work has shown how SIMD instructions can be upgraded from SSE to AVX transparently 2. Many more opportunities will appear with diverse and heterogeneous processors, featuring various kinds of accelerators.

On shared hardware, the environment is also defined by other applications competing for the same computational resources. It becomes increasingly important to adapt to changing runtime conditions, such as the contention of the cache memories, available bandwidth, or hardware faults. Fortunately, optimizing at runtime is also an opportunity, because this is the first time the program is visible as a whole: executable and libraries (including library versions). Optimizers may also rely on dynamic information, such as actual input data, parameter values, etc. We have already developed software platforms 37, 33 to analyze and optimize programs at runtime, and we started working on automatic dynamic parallelization of sequential code, and dynamic specialization.

We addressed some of these challenges in previous projects such as Nano2017 PSAIC Collaborative research program with STMicroelectronics, as well as within the Inria Project Lab MULTICORE. The H2020 FET HPC project ANTAREX also addressed these challenges from the energy perspective, while the ANR Continuum project and the Inria Challenge ZEP focused on opportunities brought by non-volatile memories. We further leverage our platform and initial results to address other adaptation opportunities. Efficient software adaptation requires expertise from all domains tackled by PACAP, and strong interaction between all team members is expected.

3.2.3 Research directions in uniprocessor micro-architecture

Achieving high single-thread performance remains a major challenge even in the multicore era (Amdahl's law). The members of the PACAP project-team have been conducting research in uniprocessor micro-architecture research for about 25 years covering major topics including caches, instruction front-end, branch prediction, out-of-order core pipeline, and value prediction. In particular, in recent years they have been recognized as world leaders in branch prediction 4134 and in cache prefetching 5 and they have revived the forgotten concept of value prediction 87. This research was supported by the ERC Advanced grant DAL (2011-2016) and also by Intel. We pursue research on achieving ultimate unicore performance. Below are several non-orthogonal directions that we have identified for mid-term research:

1. management of the memory hierarchy (particularly the hardware prefetching);
2. practical design of very wide issue execution cores;
3. speculative execution.

Memory design issues:

Performance of many applications is highly impacted by the memory hierarchy behavior. The interactions between the different components in the memory hierarchy and the out-of-order execution engine have high impact on performance.

The Data Prefetching Contest held with ISCA 2015 has illustrated that achieving high prefetching efficiency is still a challenge for wide-issue superscalar processors, particularly those featuring a very large instruction window. The large instruction window enables an implicit data prefetcher. The interaction between this implicit hardware prefetcher and the explicit hardware prefetcher is still relatively mysterious as illustrated by Pierre Michaud's BO prefetcher (winner of DPC2) 5. The first research objective is to better understand how the implicit prefetching enabled by the large instruction window interacts with the L2 prefetcher and then to understand how explicit prefetching on the L1 also interacts with the L2 prefetcher.

The second research objective is related to the interaction of prefetching and virtual/physical memory. On real hardware, prefetching is stopped by page frontiers. The interaction between TLB prefetching (and on which level) and cache prefetching must be analyzed.

The prefetcher is not the only actor in the hierarchy that must be carefully controlled. Significant benefits can also be achieved through careful management of memory access bandwidth, particularly the management of spatial locality on memory accesses, both for reads and writes. The exploitation of this locality is traditionally handled in the memory controller. However, it could be better handled if larger temporal granularity was available. Finally, we also intend to continue to explore the promising avenue of compressed caches. In particular we proposed the skewed compressed cache 11. It offers new possibilities for efficient compression schemes.

Ultra wide-issue superscalar.

To effectively leverage memory level parallelism, one requires huge out-of-order execution structures as well as very wide issue superscalar processors. For the two past decades, implementing ever wider issue superscalar processors has been challenging. The objective of our research on the execution core is to explore (and revisit) directions that allow the design of a very wide-issue (8-to-16 way) out-of-order execution core while mastering its complexity (silicon area, hardware logic complexity, power/energy consumption).

The first direction that we are exploring is the use of clustered architectures 6. Symmetric clustered organization allows to benefit from a simpler bypass network, but induce large complexity on the issue queue. One remarkable finding of our study 6 is that, when considering two large clusters (e.g. 8-wide), steering large groups of consecutive instructions (e.g. 64 $\mu$ops) to the same cluster is quite efficient. This opens opportunities to limit the complexity of the issue queues (monitoring fewer buses) and register files (fewer ports and physical registers) in the clusters, since not all results have to be forwarded to the other cluster.

The second direction that we are exploring is associated with the approach that we developed with Sembrant et al. 38. It reduces the number of instructions waiting in the instruction queues for the applications benefiting from very large instruction windows. Instructions are dynamically classified as ready (independent from any long latency instruction) or non-ready, and as urgent (part of a dependency chain leading to a long latency instruction) or non-urgent. Non-ready non-urgent instructions can be delayed until the long latency instruction has been executed; this allows to reduce the pressure on the issue queue. This proposition opens the opportunity to consider an asymmetric micro-architecture with a cluster dedicated to the execution of urgent instructions and a second cluster executing the non-urgent instructions. The micro-architecture of this second cluster could be optimized to reduce complexity and power consumption (smaller instruction queue, less aggressive scheduling...)

Speculative execution.

Out-of-order (OoO) execution relies on speculative execution that requires predictions of all sorts: branch, memory dependency, value...

The PACAP members have been major actors of branch prediction research for the last 25 years; and their proposals have influenced the design of most of the hardware branch predictors in current microprocessors. We will continue to steadily explore new branch predictor designs, as for instance 39.

In speculative execution, we have recently revisited value prediction (VP) which was a hot research topic between 1996 and 2002. However it was considered until recently that value prediction would lead to a huge increase in complexity and power consumption in every stage of the pipeline. Fortunately, we have recently shown that complexity usually introduced by value prediction in the OoO engine can be overcome 874134. First, very high accuracy can be enforced at reasonable cost in coverage and minimal complexity 8. Thus, both prediction validation and recovery by squashing can be done outside the out-of-order engine, at commit time. Furthermore, we propose a new pipeline organization, EOLE ({Early | Out-of-order | Late} Execution), that leverages VP with validation at commit to execute many instructions outside the OoO core, in-order 7. With EOLE, the issue-width in OoO core can be reduced without sacrificing performance, thus benefiting the performance of VP without a significant cost in silicon area and/or energy. In the near future, we will explore new avenues related to value prediction. These directions include register equality prediction and compatibility of value prediction with weak memory models in multiprocessors.

3.2.4 Towards heterogeneous single-ISA CPU-GPU architectures

Heterogeneous single-ISA architectures have been proposed in the literature during the 2000's 32 and are now widely used in the industry (Arm big.LITTLE, NVIDIA 4+1, Intel Alder Lake...) as a way to improve power-efficiency in mobile processors. These architectures include multiple cores whose respective micro-architectures offer different trade-offs between performance and energy efficiency, or between latency and throughput, while offering the same interface to software. Dynamic task migration policies leverage the heterogeneity of the platform by using the most suitable core for each application, or even each phase of processing. However, these works only tune cores by changing their complexity. Energy-optimized cores are either identical cores implemented in a low-power process technology, or simplified in-order superscalar cores, which are far from state-of-the-art throughput-oriented architectures such as GPUs.

We investigate the convergence of CPU and GPU at both architecture and compiler levels.

Architecture.

The architecture convergence between Single Instruction Multiple Threads (SIMT) GPUs and multicore processors that we have been pursuing  15 opens the way for heterogeneous architectures including latency-optimized superscalar cores and throughput-optimized GPU-style cores, which all share the same instruction set. Using SIMT cores in place of superscalar cores will enable the highest energy efficiency on regular sections of applications. As with existing single-ISA heterogeneous architectures, task migration will not necessitate any software rewrite and will accelerate existing applications.

Compilers for emerging heterogeneous architectures.

Single-ISA CPU+GPU architectures will provide the necessary substrate to enable efficient heterogeneous processing. However, it will also introduce substantial challenges at the software and firmware level. Task placement and migration will require advanced policies that leverage both static information at compile time and dynamic information at run-time. We are tackling the heterogeneous task scheduling problem at the compiler level.

3.2.5 Real-time systems

Safety-critical systems (e.g. avionics, medical devices, automotive...) have so far used simple unicore hardware systems as a way to control their predictability, in order to meet timing constraints. Still, many critical embedded systems have increasing demand in computing power, and simple unicore processors are not sufficient anymore. General-purpose multicore processors are not suitable for safety-critical real-time systems, because they include complex micro-architectural elements (cache hierarchies, branch, stride and value predictors) meant to improve average-case performance, and for which worst-case performance is difficult to predict. The prerequisite for calculating tight WCET is a deterministic hardware system that avoids dynamic, time-unpredictable calculations at run-time.

Even for multi and manycore systems designed with time-predictability in mind (Kalray MPPA manycore architecture or the Recore manycore hardware) calculating WCETs is still challenging. The following two challenges will be addressed in the mid-term:

1. definition of methods to estimate WCETs tightly on manycores, that smartly analyze and/or control shared resources such as buses, NoCs or caches;
2. methods to improve the programmability of real-time applications through automatic parallelization and optimizations from model-based designs.

3.2.6 Power efficiency

PACAP addresses power-efficiency at several levels. First, we design static and split compilation techniques to contribute to the race for Exascale computing (the general goal is to reach ${10}^{18}$ FLOP/s at less than 20 MW). Second, we focus on high-performance low-power embedded compute nodes. Within the ANR project Continuum, in collaboration with architecture and technology experts from LIRMM and the SME Cortus, we researched new static and dynamic compilation techniques that fully exploit emerging memory and NoC technologies. Finally, in collaboration with the TARAN project-team, we investigate the synergy of reconfigurable computing and dynamic code generation.

Green and heterogeneous high-performance computing.

Concerning HPC systems, our approach consists in mapping, runtime managing and autotuning applications for green and heterogeneous High-Performance Computing systems up to the Exascale level. One key innovation of the proposed approach consists in introducing a separation of concerns (where self-adaptivity and energy efficient strategies are specified aside to application functionalities) promoted by the definition of a Domain Specific Language (DSL) inspired by aspect-oriented programming concepts for heterogeneous systems. The new DSL will be introduced for expressing adaptivity/energy/performance strategies and to enforce at runtime application autotuning and resource and power management. The goal is to support the parallelism, scalability and adaptability of a dynamic workload by exploiting the full system capabilities (including energy management) for emerging large-scale and extreme-scale systems, while reducing the Total Cost of Ownership (TCO) for companies and public organizations.

High-performance low-power embedded compute nodes.

We will address the design of next generation energy-efficient high-performance embedded compute nodes. We focus at the same time on software, architecture and emerging memory and communication technologies in order to synergistically exploit their corresponding features. The approach of the project is organized around three complementary topics: 1) compilation techniques; 2) multicore architectures; 3) emerging memory and communication technologies. PACAP will focus on the compilation aspects, taking as input the software-visible characteristics of the proposed emerging technology, and making the best possible use of the new features (non-volatility, density, endurance, low-power).

Hardware Accelerated JIT Compilation.

Reconfigurable hardware offers the opportunity to limit power consumption by dynamically adjusting the number of available resources to the requirements of the running software. In particular, VLIW processors can adjust the number of available issue lanes. Unfortunately, changing the processor width often requires recompiling the application, and VLIW processors are highly dependent of the quality of the compilation, mainly because of the instruction scheduling phase performed by the compiler. Another challenge lies in the high constraints of the embedded system: the energy and execution time overhead due to the JIT compilation must be carefully kept under control.

We started exploring ways to reduce the cost of JIT compilation targeting VLIW-based heterogeneous manycore systems. Our approach relies on a hardware/software JIT compiler framework. While basic optimizations and JIT management are performed in software, the compilation back-end is implemented by means of specialized hardware. This back-end involves both instruction scheduling and register allocation, which are known to be the most time-consuming stages of such a compiler.

3.2.7 Security

Security is a mandatory concern of any modern computing system. Various threat models have led to a multitude of protection solutions. Members of PACAP already contributed in the past, thanks to the HAVEGE 40 random number generator, and code obfuscating techniques (the obfuscating just-in-time compiler 30, or thread-based control flow mangling 35). Still, security is not core competence of PACAP members.

Our strategy consists in partnering with security experts who can provide intuition, know-how and expertise, in particular in defining threat models, and assessing the quality of the solutions. Our expertise in compilation and architecture helps design more efficient and less expensive protection mechanisms.

Examples of collaborations so far include the following:

• Compilation:
  We partnered with experts in security and codes to prototype a platform that demonstrates resilient software. They designed and proposed advanced masking techniques to hide sensitive data in application memory. PACAP's expertise is key to select and tune the protection mechanisms developed within the project, and to propose safe, yet cost-effective solutions from an implementation point of view.
• Dynamic Binary Rewriting:
  Our expertise in dynamic binary rewriting combines well with the expertise of the CIDRE team in protecting application. Security has a high cost in terms of performance, and static insertion of countermeasures cannot take into account the current threat level. In collaboration with CIDRE, we proposed an adaptive insertion/removal of countermeasures in a running application based of dynamic assessment of the threat level.
• WCET Analysis:
  Designing real-time systems requires computing an upper bound of the worst-case execution time. Knowledge of this timing information opens an opportunity to detect attacks on the control flow of programs. In collaboration with CIDRE, we developed a technique to detect such attacks thanks to a hardware monitor that makes sure that statically computed time information is preserved (TARAN is also involved in the definition of the hardware component).

6.1.1 ATMI

• Keywords:
  Analytic model, Chip design, Temperature
• Scientific Description:

  Research on temperature-aware computer architecture requires a chip temperature model. General-purpose models based on classical numerical methods like finite differences or finite elements are not appropriate for such research, because they are generally too slow for modeling the time-varying thermal behavior of a processing chip.

  ATMI (Analytical model of Temperature in MIcroprocessors) is an ad hoc temperature model for studying thermal behaviors over a time scale ranging from microseconds to several minutes. ATMI is based on an explicit solution to the heat equation and on the principle of superposition. ATMI can model any power density map that can be described as a superposition of rectangle sources, which is appropriate for modeling the microarchitectural units of a microprocessor.

• Functional Description:
  ATMI is a library for modelling steady-state and time-varying temperature in microprocessors. ATMI uses a simplified representation of microprocessor packaging.
• URL:
  https://­team.­inria.­fr/­pacap/­software/­atmi/
• Contact:
  Pierre Michaud
• Participant:
  Pierre Michaud

6.1.2 HEPTANE

• Keywords:
  IPET, WCET, Performance, Real time, Static analysis, Worst Case Execution Time
• Scientific Description:

  WCET estimation

  The aim of Heptane is to produce upper bounds of the execution times of applications. It is targeted at applications with hard real-time requirements (automotive, railway, aerospace domains). Heptane computes WCETs using static analysis at the binary code level. It includes static analyses of microarchitectural elements such as caches and cache hierarchies.

• Functional Description:
  In a hard real-time system, it is essential to comply with timing constraints, and Worst Case Execution Time (WCET) in particular. Timing analysis is performed at two levels: analysis of the WCET for each task in isolation taking account of the hardware architecture, and schedulability analysis of all the tasks in the system. Heptane is a static WCET analyser designed to address the first issue.
• URL:
  https://­team.­inria.­fr/­pacap/­software/­heptane/
• Contact:
  Isabelle Puaut
• Participants:
  Benjamin Lesage, Loïc Besnard, Damien Hardy, François Joulaud, Isabelle Puaut, Thomas Piquet
• Partner:
  Université de Rennes 1

6.1.3 tiptop

• Keywords:
  Instructions, Cycles, Cache, CPU, Performance, HPC, Branch predictor
• Scientific Description:

  Tiptop is a simple and flexible user-level tool that collects hardware counter data on Linux platforms (version 2.6.31+) and displays them in a way simple to the Linux "top" utility. The goal is to make the collection of performance and bottleneck data as simple as possible, including simple installation and usage. Unless the system administrator has restricted access to performance counters, no privilege is required, any user can run tiptop.

  Tiptop is written in C. It can take advantage of libncurses when available for pseudo-graphic display. Installation is only a matter of compiling the source code. No patching of the Linux kernel is needed, and no special-purpose module needs to be loaded.

  Current version is 2.3.2, released December 2023. Tiptop has been integrated in major Linux distributions, such as Fedora, Debian, Ubuntu, CentOS.

• Functional Description:
  Today's microprocessors have become extremely complex. To better understand the multitude of internal events, manufacturers have integrated many monitoring counters. Tiptop can be used to collect and display the values from these performance counters very easily. Tiptop may be of interest to anyone who wants to optimize the performance of their HPC applications.
• URL:
  https://­team.­inria.­fr/­pacap/­software/­tiptop/
• Contact:
  Erven Rohou
• Participant:
  Erven Rohou

6.1.4 GATO3D

• Keywords:
  Code optimisation, 3D printing
• Functional Description:
  GATO3D stands for "G-code Analysis Transformation and Optimization". It is a library that provides an abstraction of the G-code, the language interpreted by 3D printers, as well as an API to manipulate it easily. First, GATO3D reads a file in G-code format and builds its representation in memory. This representation can be transcribed into a G-code file at the end of the manipulation. The software also contains client codes for the computation of G-code properties, the optimization of displacements, and a graphical rendering.
• Authors:
  Damien Hardy, Erven Rohou
• Contact:
  Erven Rohou

6.1.5 OptiPrint

• Keywords:
  3D printing, Planning, Optimization
• Functional Description:
  OptiPrint is a software library dedicated to print time optimization for fused filament deposition (FDM) printers. This library is integrated to the Gato3D compiler. Its role is to allow the optimization of the printing time by reordering / filtering the G-code sent to a 3D printer. The optimization is fully configurable. It adapts to the characteristics of the printers (type of nozzle, speed of movement of the nozzle). It also allows to describe scheduling constraints allowing to make a compromise between printing quality and optimization.
• Contact:
  Fabrice Lamarche

6.1.6 SAMVA

• Keywords:
  Static analysis, Fault injection
• Functional Description:
  SAMVA is a software package for determining attack paths in the context of precise, multiple fault injection attacks. It is framework for efficiently searching vulnerabilities of applications in presence of multiple instruction-skip faults with various widths. SAMVA relies solely on static analysis to determine attack paths in a binary code. It is configurable with the fault injection capacity of the attacker and the attacker's objective
• Authors:
  Antoine Gicquel, Erven Rohou, Karine Heydemann, Damien Hardy
• Contact:
  Erven Rohou

6.1.7 TimeKlip

• Keywords:
  Simulator, 3D printing
• Functional Description:

  3D printing simulator calculating the printing time of a G-code file. It is able to give timing information for each instruction in the file. The simulator does not require a printer to run, only configuration files. It is also slicer agnostic.

  The simulator takes the form of a module integrated into the Klipper firmware.

• Authors:
  Damien Hardy, Camille Le Bon
• Contact:
  Damien Hardy

Pre-training and fine-tuning dataset for transformers consisting of basic blocks and their execution times (average, minimum, and maximum) along with the execution context of these blocks, for various Cortex processors M7, M4, A53, and A72

We are releasing the dataset used for training CAWET 16, a tool for estimating the Worst-Case Execution Time (WCET) of basic blocks using the Transformer XL model. CAWET leverages the Transformer architecture for accurate WCET predictions, and its training involves two main phases: self-supervised pre-training and fine-tuning.

CAWET undergoes a pre-training process on a substantial corpus of basic blocks to enable the Transformer to grasp the intricacies of the assembly language in focus. For this, we utilized CodeNet 36, a comprehensive collection of publicly submitted solutions to competitive programming challenges, comprising roughly 900,000 C programs. These programs were cross-compiled to the target architecture and subsequently disassembled using GNU binary utilities with objdump. The textual output from objdump, after a series of basic parsing operations (e.g., address extraction, separation of basic blocks), serves as the foundation for an extensive pre-training dataset. We employed this dataset to develop a vocabulary model utilizing sentence piece 31. Following the completion of the sentence piece model's training, it becomes ready for use in tokenizing any binary programs written in the target instruction set.

The fine-tuning phase of CAWET involves its adaptation to basic blocks along with their contextual information. Here, we used a varied and openly accessible collection of programs, namely, The Algorithms (accessible at: https://­github.­com/­TheAlgorithms/­C), MiBench 28, and Polybench 42.

Data is available at: https://­zenodo.­org/­records/­10043908.

A dataset of synthetically generated code blocks for the learning of WCET on Cortex A53

We are releasing the data related to our RTCSA publication 26: WE-HML Dataset WCET code block with different pollution factors on data cache for Cortex A53.

Data is available at: https://­zenodo.­org/­records/­10043653.

7.1.1 Compilation for Intermittent Systems

Participants: Isabelle Puaut, Hugo Reymond, Erven Rohou

Context: CominLabs project NOP

External collaborators: Sébastien Faucou, Mikaël Briday, Jean-Luc Béchennec, LS2N Nantes

Battery-free devices enable sensing in hard-to-access locations, opening up new opportunities in various fields such as healthcare, space, or civil engineering. Such devices harvest ambient energy and store it in a capacitor. Due to the unpredictable nature of the harvested energy, a power failure can occur at any time, resulting in a loss of all non-persistent information (e.g., processor registers, data stored in volatile memory). Checkpointing volatile data in non-volatile memory allows the system to recover after a power failure, but raises two issues: (i) spatial and temporal placement of checkpoints; (ii) memory allocation of variables between volatile and non-volatile memory, with the overall objective of using energy as efficiently as possible. While many techniques rely on the developer to address these issues, we present SCHEMATIC 20, a compiler technique that automates checkpoint placement and memory allocation to minimize the overall energy consumption. SCHEMATIC ensures that programs will eventually terminate (forward progress property). Moreover, checkpoint placement and memory allocation adapt to the size of the energy buffer and the capacity of volatile memory. SCHEMATIC takes advantage of volatile memory (VM) to reduce the energy consumed, by automatically placing the most used variables in VM. We tested SCHEMATIC for different experimental settings (size of volatile memory and capacitor) and results show an average energy reduction of 51 % compared to related techniques.

7.1.2 Dynamic Binary Analysis and Optimization

Participants: Aurore Poirier, Erven Rohou

Context: Exploratory Action AoT.js

External collaborators: Manuel Serrano, INDES/SPLiTS team (Sophia)

Since the creation of JavaScript, web browsers embedding it have been relying on JIT compilers or even interpreters to execute it, a choice that seems natural because of the dynamic aspect of the language. However, researchers have wondered whether it is possible to produce ahead-of-time compiled code that allows dynamic languages to be used in contexts that do not allow the use of JIT compilers (due to limited resources, security policies, response time...) In order to implement performance measurement methods that feed back information from the processor to the high-level languages and design new ways to compile JavaScript, we explored ways to exploit low-level performance measurement from hardware counters.

7.1.3 Accurate 3D printing time estimation

Participants: Pierre Bedell, Damien Hardy, Camille Le Bon, Mohammed Mehdi Merah

Context: Inria Exploratory Action Ofast3D

External collaborators: MimeTIC and MFX (Nancy) teams.

Fused deposition modeling 3D printing is a process that requires hours or even days to print a 3D model. To assess the benefits of optimizations, it is mandatory to have a fast 3D printing time estimator to avoid waste of materials and a very long validation process. Furthermore, the estimation must be accurate 29. To reach that goal, we have modified an existing 3D printer firmwares Klipper in simulation mode to determine the timing per G-code instruction (the language interpreted by 3D printers). This extension named TimeKlip 6.1.7 is printer and slicer agnostic. We conduct an extensive study to highlight the precision and versatility of our simulator on 3D printers with different kinematics, using different slicers. We show that our simulator can be up to 145 times faster than an actual print. Its average error, without requiring any calibration, is 0.04 % on a total of 66 printed models representing more than 133 hours of print.

See also GATO3D 6.1.4 and OptiPrint 6.1.5.

7.2.1 Automatic synthesis of multi-thread pipelines

Participants: Sara Sadat Hoseininasab, Caroline Collange

Context: ANR Project DYVE

External collaborator: Steven Derrien, TARAN team.

Register-Transfer Level (RTL) design has been a traditional approach in hardware design for several decades. However, with the growing complexity of designs and the need for fast time-to-market, the design and verification process at the RTL level can become impractical. This has motivated for raising the abstraction level in hardware design. High-Level Synthesis (HLS) provides higher-level abstraction by automatically transforming a behavioral specification of a circuit into a low-level RTL, making it easier to design, simulate and verify complex digital systems. HLS relies on statically scheduled data paths which can limit its effectiveness. This limitation makes it difficult to design the micro-architectural features of processors from an Instruction Set Architecture described in high-level languages.

This project aims to demonstrate how the available features of HLS can be deployed in designing various pipelined processors micro-architecture. Our approach takes advantage of the capabilities of HLS and employs multi-threading and dynamic scheduling techniques to overcome the limitation of HLS in pipelining a processor from an Instruction Set Simulator written in C 19.

7.2.2 Two-dimensional memory architecture

Participants: Pierre Michaud, Erven Rohou

Context: ANR Project Maplurinum.

The Maplurinum project revisits the foundations of computer architecture and operating systems for cloud computing and high-performance computing, to better manage the growing heterogeneneity of hardware components. A 128-bit address space is considered as one of the possible solutions to achieve this goal. As a participant of the Maplurinum project, the PACAP team explores some of the architectural implications of a 128-bit address space.

Most general-purpose computing systems today implement a virtual memory where the memory addresses seen by the programmer, called virtual addresses, are distinct from the physical memory addresses used by the hardware. During execution of a program, the hardware and the operating system collaborate to translate virtual addresses automatically into physical addresses. A virtual memory provides several advantages, in particular with respect to program portability and process isolation.

As memory needs keep growing, the 64-bit virtual address space of current architecture will eventually be insufficient, and the transition to 128-bit addresses will have to be considered 24, 25. 128-bit addresses will be beneficial to applications needing a huge amount of memory. However, doubling the virtual address length has a cost in hardware complexity. The transition from 32-bit to 64-bit architectures happened at a time when the hardware cost could be partially hidden by Dennard scaling, making the transition relatively smooth as far as the hardware is concerned, with little impact on clock frequency, silicon area and energy consumption. However, Dennard scaling stopped around 2005, and the hardware cost of transitioning to 128-bit will be a factor to take into account. If the applications that do not benefit from 128-bit addresses still consume more energy than on 64-bit architectures, this will be a problem. The transition will be easier if it benefits a large class of applications, not just the ones requiring a huge amount of memory, and if the hardware cost is small.

We consider the possibility to make the transition to 128-bit addresses coincide with a fundamental architectural change: instead of representing a virtual address as a single 128-bit value, we represent it as two independent 64-bit coordinates X and Y. In other words, we consider replacing the classical one-dimensional (1D) virtual address space with a two-dimensional (2D) one.

Conventional architectures have a 1D virtual address space because it is the simplest option and because the decisions made several decades ago, when simplicity was required, tend to last (e.g., backward binary compatibility). Besides these reasons, the choice of a 1D address space is somewhat arbitrary, as the data manipulated by programs are often inherently multi-dimensional.

We have proposed a 2D-VM architecture called XYA and a programming language called XYC, similar to the C language but exposing the 2D memory to the programmer. XYA partitions the address space into regions called books, each book corresponding to a different page aspect ratio. The compiler or the programmer can select the book where an array is mapped so as to maximize page locality. We have written a C++ library called MXY allowing to write programs in pseudo-XYC whose execution generates a 2D address trace. With MXY, we did a case study of a 2D fast Fourier transform and have shown that XYA offers new degrees of freedom to programmers for maximizing performance. Besides a variable page aspect ratio, XYA offers other advantages compared to a conventional 128-bit architecture: a 64-bit integer data path (registers, ALUs), efficient 2D array slicing, and efficient 2D array indexing (no multiplication needed). A paper describing XYA is under submission at the ISCA conference.

7.3.1 Using machine learning for timing analysis of complex processors

Participants: Abderaouf Nassim Amalou, Isabelle Puaut

External collaborators: Elisa Fromont, LACODAM team

Modern processors raise a challenge for timing estimation in general, and WCET estimation in particular, since detailed knowledge of the processor microarchitecture is not available. Our recent work has explored the use of the advanced language processing technique Transformer-XL to estimate the timing of machine code, running on embedded processors. The most recent results in 2023 have targeted worst-case performance (WCET estimation) and average-case performance.

Regarding worst-case performance, we have introduced CAWET, a hybrid worst-case program timing estimation technique 16. CAWET identifies the longest execution path using static techniques, whereas the worst-case execution time (WCET) of basic blocks is predicted using Transformer-XL. By employing Transformers-XL in CAWET, the execution context formed by previously executed basic blocks is taken into account, allowing for consideration of the micro-architecture of the processor pipeline without explicit modeling. Through a series of experiments on the TacleBench benchmarks, using different target processors (Arm Cortex M4, M7, and A53), our method is demonstrated to never underestimate WCETs and is shown to be less pessimistic than its competitors.

As far as average-case execution time is concerned, we have designed ORXESTRA, a context-aware execution time prediction model based on Transformers XL, specifically designed to accurately estimate performance in embedded system applications. Unlike traditional machine learning models that often overlook contextual information, resulting in biased predictions for individual basic blocks, ORXESTRA overcomes this limitation by incorporating execution context awareness. By doing so, ORXESTRA effectively accounts for the processor micro-architecture without explicitly modeling micro-architectural elements such as caches, pipelines, and branch predictors. Our evaluations demonstrate ORXESTRA's ability to provide precise timing estimations for different ARM targets (Cortex M4, M7, A53, and A72), surpassing existing machine learning-based approaches in both prediction accuracy and prediction speed 17.

This work is done in collaboration with Elisa Fromont, from the LACODAM team, who co-supervizes the PhD thesis of Abderaouf Nassim Amalou, defended in December 2023 22.

7.3.2 Static estimation of memory access profiles for real-time multi-core systems

Participants: Hector Chabot, Isabelle Puaut

External collaborators: Hugues Cassé, Thomas Carle, IRIT Toulouse

Real-time systems are defined by their need for guarantees of timing properties to ensure a correct behavior. These properties call for the computation of the upper-bound of the Worst-Case Execution Time (WCET) of tasks. The calculated upper-bound needs to be both safe and tight: the result must be an over-approximation without being too far off from the ground truth. WCET analysis for single-core systems have been well studied in the past thirty years. However, the spread of multi-core usage in real-time systems raises new issues.

In a multi-core context, resource sharing is often used to decrease the overall cost of the platform. This leads to conflicts on concurrent access to shared resource. These conflicts, named interferences, causes delays which increase the execution time of tasks. Accounting for interferences delay in WCET computation may rely on interference avoidance, through hardware or software-enforced policies, or on calculation of interference delays on an un-modified multi-core system. Both techniques rely on the knowledge of the shared resources accesses for a given task to find possible interferences. We propose a new technique that extracts memory access profiles for real-time software. In contrast to state-of-the-art studies, the constructed profiles are both fine-grain for a more precise calculation of interference delays and code-based to allow dynamic schedule reconfiguration for on-line interference reduction.

This work is part of the PhD thesis of Hector Chabot, who is co-supervized by Hugues Cassé and Thomas Carle from IRIT, Toulouse.

7.4.1 Verification of Data Flow Integrity for Real-Time Embedded Systems

Participants: Nicolas Bellec (former PhD student in PACAP), Isabelle Puaut

External collaborators: Guillaume Hiet, Frédéric Tronel, CIDRE team and Simon Rokicki, TARAN team

Real-time systems have more and more ways to communicate wirelessly with external users. These same means can be hijacked to attack these systems, breaking their guarantees and potentially causing accidents. To protect real-time systems against these new attacks, it is necessary to develop new protections taking into account the specificities of these systems. In this work, we seek to improve the security of real-time systems against so-called memory corruption attacks. These attacks use a bad memory management in a program to modify its behavior. We are particularly interested in a defense called Data Flow Integrity, which can protect against a large class of memory corruption attacks. We adapt this protection to the context of real-time systems by optimizing the worst-case execution time, a fundamental metric to ensure the correct execution of these systems.

This work is done in collaboration with the CIDRE and TARAN teams, who co-supervized the thesis of Nicolas Bellec, defended in May 2023 23.

7.4.2 Multi-nop fault injection attack

Participants: Antoine Gicquel, Damien Hardy, Erven Rohou

External collaborators: CIDRE and TARAN team.

Multi-fault injection attacks are powerful since they allow to bypass software security mechanisms of embedded devices. Assessing the vulnerability of an application while considering multiple faults with various effects is an open problem due to the size of the fault space to explore. We propose SAMVA 18 (see Section 6.1.6), a framework for efficiently searching vulnerabilities of applications in presence of multiple instruction-skip faults with various widths. SAMVA relies solely on static analysis to determine attack paths in a binary code. It is configurable with the fault injection capacity of the attacker and the attacker's objective. We evaluate the proposed approach on eight PIN verification programs containing various software countermeasures. Our framework finds numerous attack paths, even for the most hardened version, in very limited time.

7.4.3 Gadget chains synthesis driven by SMT Solving for Code-Reuse Attacks

Participants: Nicolas Bailluet, Isabelle Puaut, Erven Rohou

External collaborators: Emmanuel Fleury, LaBRI Bordeaux.

The final objective of this work is to develop compiler approaches, based on binary code modifications, to protect programs against attacks such as Return-Oriented Programming (ROP) or Jump-Oriented Programming (JOP).

As a first step towards this ambitious goal, we have designed a new technique for the automatic chaining of gadgets. Performing complex code-reuse attacks require discovering small code snippets (gadgets) and chaining them together to reach the attacker's goal. We have designed a new method to synthesize gadget chains using SMT solving. The proposed method addresses three challenges, yet not solved by other related works: (i) it is able to build gadget chains for arbitrary exploitation contexts (whether the stack is controlled or not); (ii) it guarantees that data that are out of attacker's control do not interfere with the generated gadget chains (robust reachability property); (iii) it is able to leverage multi-path gadgets to synthesize multi-behavior chains that contain conditions and can behave differently based on their execution context. Experiments show the benefit of the robust reachability property and thoroughly evaluate the quality of the approach in terms of expressivity and performance compared to other related chain synthesis techniques.

9.1.1 H2020 projects

10.1.1 Scientific events: selection

10.1.2 Journal

10.1.3 Invited talks

• A. Gicquel was invited to give at talk at the “École de Printemps Recherche” of the CyberSchool in Apr 2023.
• H. Reymond was invited to present our results entitled “Towards Sustainable IoT Nodes” 21 at GreenDays 2023 in Lyon, France, on Mar 27th, 2023. In collaboration with LS2N, Nantes.

10.1.4 Leadership within the scientific community

E. Rohou is a member of the organization committee of focused days within the GdR SoC2.

10.1.5 Research administration

• E. Rohou is the contact for international relations for Inria Rennes Bretagne Atlantique (for scientific matters). He co-organized the 2023 edition of the French-American Doctoral Exchange Seminar (FADEx).
• E. Rohou is a member of the steering committee of the high security research laboratory (LHS).
• E. Rohou is a member of the steering committee of the Inria Rennes computer grid “igrida”.
• I. Puaut is member of the Advisory board of the Euromicro Conference on Real Time Systems (ECRTS).
• I. Puaut is member of the steering committee of the WCET workshop, satellite workshop to ECRTS.
• Since Nov 2023, I. Puaut is elected member of section 27 of CNU (Conseil National des Universités – National Council of Universities). The CNU is a national consultative and decision-making body. It makes decisions regarding the career progression of assistant professors and professors in institutions under the jurisdiction of the Ministry of Higher Education and Research (MESR).
• Since Feb 2023, I. Puaut is a member of the thesis committee (comité des thèses) at the Matisse doctoral school. The committee is responsible for reviewing thesis registration applications and forming juries. The thesis committee oversees the 250 doctoral students hosted at IRISA.

10.2.1 Teaching

• Master: C. Collange, GPU programming, 20 hours, M1, Université de Rennes, France
• Licence: D. Hardy, Real-time systems, 95 hours, L3, Université de Rennes, France
• Master: D. Hardy, Operating systems, 59 hours, M1, Université de Rennes, France
• Master: D. Hardy, Students project, 30 hours, M1, Université de Rennes, France
• Master: I. Puaut, Advanced Operating Systems (SEA), 100 hours, M1, Université de Rennes
• Master: I. Puaut, Low Level Programming (LLP), 40 hours, Université de Rennes
• Master: I. Puaut, Writing of scientific publications, 9 hours, M2 and PhD students, Université de Rennes
• Licence: N. Bailluet, Programmation C et réseau, 20 hours, L3, ENS Rennes, France
• Licence: N. Bailluet, Programmation fonctionnelle, 20 hours, L1, Université de Rennes, France
• Master: N. Bailluet, Noyaux de systèmes d'exploitation, 24 hours, M1, Université de Rennes, France
• Licence: A. Poirier, ALG2 (Algorithmique 2), 18 hours, L2, Université de Rennes, France
• Master: A. Poirier, NFS (Network For Security), 15 hours, M1, Université de Rennes, France
• Master: H. Reymond, OS and Real-Time (SEL, ITR), 32 hours, M1, Université de Rennes, France
• Licence: H. Reymond, OS and Architecture (SIN), 30 hours, L3, Université de Rennes, France
• Licence: H. Chabot, PO (Programmation Objet), 15 hours, L2, Université de Rennes, France
• Licence: H. Chabot, SYRE (Base de système et réseaux), 18 hours, L3, Université de Rennes, France

10.2.2 Supervision

• PhD: Nicolas Bellec, Security in real-time embedded systems23, May 2023, advisors I. Puaut (50 %), G. Hiet from CIDRE (25 %), F. Tronel from CIDRE (25 %)
• PhD: Abderaouf Nassim Amalou, Machine learning for performance prediction22, Dec 2023, advisors I. Puaut (75 %), E. Fromont from LACODAM (25 %)
• PhD in progress: Hector Chabot, Fine grain software modeling and analysis for interference management in multi-core real-time systems, started Sep 2023, advisors I. Puaut (50 %), H. Cassé and T. Carle (IRIT, Toulouse, 25 % each)
• PhD in progress: Anis Peysieux, Towards simple and highly efficient execution cores, started Jan 2020, advisor since Jan 2021: P. Michaud (A. Seznec was advisor from Jan 2020 until Dec 2020)
• PhD in progress: Hugo Reymond, Energy-aware execution model in intermittent systems, started Oct 2021, advisors I. Puaut, E. Rohou, S. Faucou (LS2N Nantes), J.-L. Béchennec (LS2N Nantes)
• PhD in progress: Antoine Gicquel, Étude de vulnérabilité d’un programme au format binaire en présence de fautes précises et nombreuses : métriques et contremesures, started Sep 2021, advisors D. Hardy, E. Rohou, K. Heydemann (Sorbonne Université)
• PhD in progress: Sara Hoseininasab, Automatic synthesis of multi-thread pipelines, started Nov 2021, advisors C. Collange (70 %) and S. Derrien (30 %, TARAN)
• PhD in progress: Aurore Poirier, Profile-Guided optimization for Dynamic Languages, started Oct 2022, advisors E. Rohou (50 %) and M. Serrano (50 %, Inria Sophia)
• PhD in progress: Nicolas Bailluet, Approches par modification de code machine pour la défense contre les attaques ROP et JOP, started Sep 2022, advisors I. Puaut (50 %) and E. Rohou (50 %)

10.2.3 Juries

E. Rohou was member of the following hiring committees:

• Professor, ENS Lyon
• “commission moyens incitatifs”, Centre Inria de l'Université de Rennes
• “comité recrutement” for a team assistant, Centre Inria de l'Université de Rennes

I. Puaut was member of the hiring committee for a Junior Professor Position (CPJ) on Artificial Intelligence, University of Rennes, 2023

E. Rohou was a member of the following PhD thesis committees:

• Nicolas Derumigny, Throughput Optimization Techniques for Hetegogeneous Architectures, Dec 2023 (reviewer)

I. Puaut was a member of the following PhD thesis committees:

• Samira Ait Bensaid, Formal Semantics of Hardware Compilation Framework, Université Paris Saclay, Nov 2023 (examiner)
• Sandro Grebant, Efficient tree-based symbolic WCET computation, Université de Lille, Nov 2023, (reviewer)
• Mathieu Leonel Mba, génération automatique de plateformes matérielles distribuées pour des applications de traitement du signal, Sorbonne Université, Sep 2023, (examiner, president of committee)
• Jatin Arora, Shared resource contention-aware schedulability analysis of hard real-time systems, University of Porto, Portugal, Sep 2023 (external examiner)
• Zhenyu Bai, modélisation du comportement temporel du pipeline pour le calcul du WCET, Université de Toulouse 3 – Paul Sabatier, Toulouse, May 2023 (reviewer)
• Michael Platzer, predictable and performant computer architectures for time-critical systems, Technische Universität Wien, Vienna, Austria, Feb 2023 (reviewer)

C. Collange was a member of the following PhD thesis committees:

• Kevin Mambu, Modèle de programmation bas niveau pour architecture de calcul proche mémoire, CEA / Grenoble Université, Mar 2023 (examiner)
• Alexandre Clément, Graphical Languages for Quantum Control and Linear Optics, LORIA / Université de Lorraine, May 2023 (examine0)

E. Rohou was a member of the CSI of Bruno Mateu, Jean-Loup Hatchikian-Houdot, Aaron Randrianaina, Ikram Dendani. I. Puaut was member of the CSI of Jean-Michel Gorius and Constance Bocquillon.

10.3.1 Internal or external Inria responsibilities

E. Rohou is a member of the Inria Rennes working group on sustainable development.

10.3.2 Articles and contents

D. Hardy presented the Ofast3D Inria exploratory action in Émergences.

10.3.3 Education

E. Rohou was invited to present the job of a researcher to secondary-school students (classe de 4e) at Collège de Bourgchevreuil, Cesson-Sévigné.

10.3.4 Interventions

• E. Rohou contributed to the program “1 scientifique, 1 classe : Chiche !”, Lycée Sainte-Thérèse, Quimper.
• P. Bedell and D. Hardy presented and demonstrate the Ofast3D Inria exploratory action in the 3D Print Congress & Exhibition in Paris.

International peer-reviewed conferences

• 16 inproceedingsA. N.Abderaouf N Amalou, E.Elisa Fromont and I.Isabelle Puaut. CAWET: Context-Aware Worst-Case Execution Time Estimation Using Transformers.Leibniz International Proceedings in Informatics (LIPIcs), Volume 262, pp. 7:1-7:20, Schloss Dagstuhl - Leibniz-Zentrum für InformatikECRTS 2023 - 35th Euromicro Conference on Real-Time Systems262Vienne, AustriaSchloss Dagstuhl - Leibniz-Zentrum für InformatikJuly 2023, 7:1--7:20HALDOIback to textback to text
• 17 inproceedingsA. N.Abderaouf Nassim Amalou, E.Elisa Fromont and I.Isabelle Puaut. Fast and Accurate Context-Aware Basic Block Timing Prediction using Transformers.Proceedings of the ACM SIGPLAN 2024 International Conference on Compiler ConstructionACM SIGPLAN 2024 International Conference on Compiler ConstructionEdimbourg, United KingdomMarch 2024HALDOIback to text
• 18 inproceedingsA.Antoine Gicquel, D.Damien Hardy, K.Karine Heydemann and E.Erven Rohou. SAMVA: Static Analysis for Multi-Fault Attack Paths Determination.Constructive Side-Channel Analysis and Secure DesignCOSADE 2023 - 14th International Workshop on Constructive Side-Channel Analysis and Secure DesignMunich (Allemagne), GermanySpringerMarch 2023, 3-22HALDOIback to text
• 19 inproceedingsS. S.Sara Sadat Hoseininasab, C.Caroline Collange and S.Steven Derrien. Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis.Applied Reconfigurable ComputingARC 2023 - 19th International Symposium on Applied Reconfigurable Computing14251Lecture Notes in Computer ScienceCottbus, GermanySpringer Nature Switzerland2023, 19 - 34HALDOIback to text
• 20 inproceedingsH.Hugo Reymond, J.-L.Jean-Luc Béchennec, M.Mikaël Briday, S.Sébastien Faucou, I.Isabelle Puaut and E.Erven Rohou. SCHEMATIC: Compile-time checkpoint placement and memory allocation for intermittent systems.Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization (CGO'24)IEEE/ACM International Symposium on Code Generation and Optimization (CGO'24)Edinburgh, United KingdomMarch 2024HALback to textback to text

Conferences without proceedings

• 21 inproceedingsA.Antoine Bernabeu and H.Hugo Reymond. Towards Sustainable IoT Nodes.GreenDays 2023 - Efficacité énergétique, impacts environnementaux du numérique, sobriété et frugalité numérique : une vision décloisonnée !Lyon, France2023, 1-39HALback to textback to text

Doctoral dissertations and habilitation theses

• 22 thesisA. N.Abderaouf Nassim Amalou. Machine learning for timing estimation.Université de RennesDecember 2023HALback to textback to text
• 23 thesisN.Nicolas Bellec. Security enhancement in embedded hard real-time systems.Université de RennesMay 2023HALback to textback to text

Other scientific publications

• 24 inproceedingsM.Mathieu Bacou, A.Adam Chader, C. S.Chandana S. Deshpande, C.Christian Fabre, C.César Fuguet, P.Pierre Michaud, A.Arthur Perais, F.Frédéric Pétrot, G.Gaël Thomas and E.Eduardo Tomasi Ribeiro. 128-bit addresses for the masses (of memory and devices).HotInfra 2023 - Workshop on Hot Topics in System InfrastructureOrlando, United States2023HALback to text
• 25 inproceedings M.Mathieu Bacou, A.Adam Chader, C. S.Chandana S. Deshpande, C.Christian Fabre, C.César Fuguet, P.Pierre Michaud, A.Arthur Perais, F.Frédéric Pétrot, G.Gaël Thomas and E.Eduardo Tomasi Ribeiro. We had 64-bit, yes. What about second 64-bit? RISC-V Summit Europe 2023 Barcelona, Spain 2023 HAL back to text