Section: New Results

Compilation of Hardware Accelerators with Pipelined Arithmetic

Participants : Christophe Alias, Bogdan Pasca [PhD student, Arénaire Inria Team] , Alexandru Plesco.

By nature, source-level optimizations cannot perform fine optimizations of the datapath and the control, sometimes mandatory to obtain performances. In high-level synthesis, the circuit generated must be efficient and must produce quality results. This last point is the specialty of the Arénaire Inria-team, which develops the tool FloPoCo , an open-source FPGA-specific generator of pipelined floating-point arithmetic operators, from a functional description as $(x,y,z)\mapsto e^x+y*cos\left(z\right)$. The user can specify the precision (mantissa, exponent) and the maximum frequency, then FloPoCo generates the corresponding operator.

We have developed an algorithm to automatically generate, from a C program, an hardware accelerator that efficiently uses these pipelined operators. The main issue is to reschedule the initial program execution in order to keep the operator's pipeline as busy as possible, while minimizing memory access. Then, the new execution schedule is used to generate the VHDL code of finite state machines (FSM) controlling the data-flow through the arithmetic operator. This work has been published at the conference ARC'11 [4] .

We also showed how our method can be used as a tool to generate control FSMs of multiple parallel computing cores accelerating the same application [25] . This work has been submitted to the journal Microprocessors and Microsystems.

This is still a work in progress and many issues need to be addressed, for example how to extend the program model to general nested loops with more general dependences. These extensions will require to handle properly the communications between the operators and temporary buffers. We believe that the array contraction technique developed in Compsys can be helpful in this context too.