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Section: New Results

FPGA Optimized Table Maker's Dilemma Architecture

Participants : Alexandru Plesco, Florent De Dinechin [Assistant Prof., Arenaire Inria Team] , Jean-Michel Muller [Research Director, Arenaire Inria Team] , Bogdan Pasca [PhD student, Arenaire Inria Team] .

In this work, with some members of the Arénaire team, we developed an algorithm that enables to perform the table maker's dilemma on a very regular architecture such as an FPGA. The algorithm is crucially different from the algorithm implemented on a standard PC and exploits efficiently the FPGA optimized high-performance arithmetic operators.

The core component (TaMaDi core) of our design is the polynomial evaluator based on the tabulated differences method that uses Remez algorithm. We instantiated multiple TaMaDi cores that work on $2^m$ disjoint intervals obtained from the splitting of the input interval. The TaMaDi cores are connected using a pipelined communication architecture based on the credit communication methodology. We focused on the communication architectures internal to a FPGA that can scale with limited impact on the frequency of the generated data processing architecture. We defined a new pipelined credit based communication interface that leads to a full-rate pipeline data transmission with the cost of small transfer initialization latency. This design has been proven to be effective on parallel design of TaMaDi FPGA specific algorithms. This strategy can be reused in any parallel FPGA design.

This work has been published at ASAP'11 [14] where it received a best paper award.