Section: Scientific Foundations
Presentation and originality of the PARKAS team
Our project is founded on our expertise in three complementary domains: (1) synchronous functional programming and its extensions to deal with features such as communication with bounded buffers and dynamic process creation; (2) mathematical models for synchronous circuits; (3) compilation techniques for synchronous languages and optimizing/parallelizing compilers.
A strong point of the team is its experience and investment in the development of languages and compilers. Members of the team also have direct collaborations for several years with major industrial companies in the field and several of our results are integrated in successful products. Our main results are briefly summarized below.
Synchronous functional programming
In  , Paul Caspi and Marc Pouzet introduced synchronous Kahn networks as those Kahn networks that can be statically scheduled and executed with bounded buffers. This was the origin of the language Lucid Synchrone , (http://www.di.ens.fr/~pouzet/lucid-synchrone )(The name is a reference to Lustre which stands for “Lucid Synchrone et Temps réel”.) an ML extension of the synchronous language Lustre with higher-order features, dedicated type systems (clock calculus as a type system  ,  , initialization analysis  and causality analysis  ). The language integrates original features that are not found in other synchronous languages: such as combinations of data flow, control flow, hierarchical automata and signals  ,  , and modular code generation  ,  .
In 2000, Marc Pouzet started to collaborate with the SCADE team of Esterel-Technologies on the design of a new version of SCADE. (http://www.esterel-technologies.com/products/scade-suite/ ) Several features of Lucid Synchrone are now integrated into Scade 6, which has been distributed since 2008, including the programming constructs merge , reset , the clock calculus and the type system. Several results have been developed jointly with Jean-Louis Colaço and Bruno Pagano from Esterel-Technologies, such as ways of combining data-flow and hierarchical automata, and techniques for their compilation, initialization analysis, etc.
Dassault-Systèmes (Grenoble R&D center, part of Delmia-automation) developed the language LCM , a variant of Lucid Synchrone that is used for the simulation of factories. LCM follows closely the principles and programming constructs of Lucid Synchrone (higher-order, type inference, mix of data-flow and hierarchical automata). The team in Grenoble is integrating this development into a new compiler for the language Modelica. (http://www.3ds.com/products/catia/portfolio/dymola/overview/ )
In parallel, the goal of ReactiveML (http://rml.lri.fr/ ) was to integrate a synchronous concurrency model into an existing ML language, with no restrictions on expressiveness, so as to program a large class of reactive systems, including efficient simulations of millions of communicating processes (e.g., sensor networks), video games with many interactions, physical simulations, etc. For such applications, the synchronous model simplifies system design and implementation, but the expressiveness of the algorithmic part of the language is just as essential, as is the ability to create or stop a process dynamically.
The development of ReactiveML was started by Louis Mandel during his PhD thesis  ,  and is ongoing. The language extends Ocaml (More precisely a subset of Ocaml without objects or functors.) with Esterel-like synchronous primitives — synchronous composition, broadcast communication, pre-emption/suspension — applying the solution of Boussinot  to solve causality issues.
Several open problems have been solved by Louis Mandel: the interaction between ML features (higher-order) and reactive constructs with a proper type system; efficient simulation that avoids busy waiting. The latter problem is particularly difficult in synchronous languages because of possible reactions to the absence of a signal. In the ReactiveML implementation, there is no busy waiting: inactive processes have no impact on the overall performance. It turns out that this enables ReactiveML to simulate millions of (logical) parallel processes and to compete with the best event-driven simulators  .
ReactiveML has been used for simulating routing protocols in ad-hoc networks  and large scale sensor networks  . The designer benefits from a real programming language that gives precise control of the level of simulation (e.g., each network layer up to the MAC layer) and programs can be connected to models of the physical environment programmed with Lutin  . ReactiveML is used since 2006 by the synchronous team at VERIMAG, Grenoble (in collaboration with France-Telecom) for the development of low-consumption routing protocols in sensor networks.
Relaxing synchrony with buffer communication
In the data-flow synchronous model, the clock calculus is a static analysis that ensures execution in bounded memory. It checks that the values produced by a node are instantaneously consumed by connected nodes (synchronous constraint). To program Kahn process networks with bounded buffers (as in video applications), it is thus necessary to explicitly place nodes that implement buffers. The buffers sizes and the clocks at which data must be read or written have to be computed manually. In practice, it is done with simulation or successive tries and errors. This task is difficult and error prone. The aim of the n-synchronous model is to automatically compute at compile time these values while insuring the absence of deadlock.
Technically, it allows processes to be composed whenever they can be synchronized through a bounded buffer  ,  . The new flexibility is obtained by relaxing the clock calculus by replacing the equality of clocks by a sub-typing rule. The result is a more expressive language which still offers the same guarantees as the original. The first version of the model was based on clocks represented as ultimately periodic binary words  . It was algorithmically expensive and limited to periodic systems. In  , an abstraction mechanism is proposed which permits direct reasoning on sets of clocks that are defined as a rational slope and two shifts. An implementation of the n-synchronous model, named Lucy-n , was developed in 2009  , as was a formalization of the theory in Coq  . We also worked on low-level compiler and runtime support to parallelize the execution of relaxed synchronous systems, proposing a portable intermediate language and runtime library called Erbium  .
This work started as a collaboration between Marc Pouzet (LIP6, Paris, then LRI and INRIA Proval, Orsay), Marc Duranton (Philips Research then NXP, Eindhoven), Albert Cohen (INRIA Alchemy, Orsay) and Christine Eisenbeis (INRIA Alchemy, Orsay) on the real-time programming of video stream applications in set-top boxes. It was significantly extended by Louis Mandel and Florence Plateau during her PhD thesis  (supervised by Marc Pouzet and Louis Mandel). Low-level support has been investigated with Cupertino Miranda, Philippe Dumont (INRIA Alchemy, Orsay) and Antoniu Pop (Mines ParisTech).
Polyhedral compilation and optimizing compilers
Despite decades of progress, the best parallelizing and optimizing compilers still fail to extract parallelism and to perform the necessary optimizations to harness multi-core processors and their complex memory hierarchies. Polyhedral compilation aims at facilitating the construction of more effective optimization and parallelization algorithms. It captures the flow of data between individual instances of statements in a loop nest, allowing to accurately model the behavior of the program and represent complex parallelizing and optimizing transformations. Affine multidimensional scheduling is one of the main tools in polyhedral compilation  . Albert Cohen, in collaboration with Cédric Bastoul, Sylvain Girbal, Nicolas Vasilache, Louis-Noël Pouchet and Konrad Trifunovic (LRI and INRIA Alchemy, Orsay) has contributed to a large number of research, development and transfer activities in this area.
The relation between polyhedral compilation and data-flow synchrony has been identified through data-flow array languages  ,  ,  ,  and the study of the scheduling and mapping algorithms for these languages. We would like to deepen the exploration of this link, embedding polyhedral techniques into the compilation flow of data-flow, relaxed synchronous languages.
Our previous work led to the design of a theoretical and algorithmic framework rooted in the polyhedral model of compilation, and to the implementation of a set of tools based on production compilers (Open64, GCC) and source-to-source prototypes (PoCC, http://pocc.sourceforge.net ). We have shown that not only does this framework simplify the problem of building complex loop nest optimizations, but also that it scales to real-world benchmarks  ,  ,  ,  . The polyhedral model has finally evolved into a mature, production-ready approach to solve the challenges of maximizing the scalability and efficiency of loop-based computations on a variety of high performance and embedded targets.
After an initial experiment with Open64  ,  , we ported these techniques to the GCC compiler  ,  ,  , applying them to multi-level parallelization and optimization problems, including vectorization and exploitation of thread-level parallelism. Independently, we made significant progress in the design of effective optimization heuristics, working on the interactions between the semantics of the compiler's intermediate representation and the structure of the optimization space  ,  ,  ,  . These results open opportunities for complex optimizations that target larger problems, such as the scheduling and placement of process networks, or the offloading of computational kernels to hardware accelerators (such as GPUs).
Automatic compilation of high performance circuits
For both cost and performance reasons, computing systems tightly couple parts realized in hardware with parts realized in software. The boundary between hardware and software keeps moving with the underlying technology and the external economic pressure. Moreover, thanks to FPGA technology, hardware itself has become programmable. There is now a pressing need from industry for hardware/software co-design, and for tools which automatically turn software code into hardware circuits, or more usually, into hybrid code that simultaneously targets GPUs, multiple cores, encryption ASICs, and other specialized chips.
Departing from customary C-to-VHDL compilation, we trust that sharper results can be achieved from source programs that specify bit-wise time/space behavior in a rigorous synchronous language, rather than just the I/O behavior in some (ill-specified) subset of C. This specification allows the designer to also program the (asynchronous) environment in which to operate the entire system, and to profile/measure/control each variable of the design.
At any time, the designer can edit a single specification of the system, from which both the software and the hardware are automatically compiled, and guaranteed to be compatible. Once correct (functionally and with respect to the behavioral specification), the application can be automatically deployed (and tested) on a hard/soft hybrid co-design support.
Key aspects of the advocated methodology were validated by Jean Vuillemin in the design of a PAL2HDTV video sampler  ,  . The circuit was automatically compiled from a synchronous source specification, decorated and guided by a few key hints to the hardware back-end, that targetted an FPGA running at real-time video specifications: a tightly-packed highly-efficient design at 240MHz, generated 100% automatically from the application specification source code, and including all run-time/debug/test/validate ancillary software. It was subsequently commercialized on FPGA by LetItWave, and then on ASIC by Zoran. This successful experience underlines our research perspectives on parallel synchronous programming.