Section: Dissemination

Teaching - Supervision - PhD Committee

Teaching Responsibilities

There is a strong teaching activity in the Cairn team since most of the permanent members are Professors or Associate Professors.


C. Wolinski is the Director of Esir .

P. Quinton is the deputy-director of Ecole Normale Supérieure de Cachan, responsible of the Brittany branch of this school.

D. Chillet is the Director of Academic Studies of Enssat .

P. Scalart is the Head of the Electronics Engineering department of Enssat .

S. Derrien is the responsible of the first year of the master of computer science at ISTIC since Sep. 2012.

O. Sentieys is responsible of the ”Embedded Systems” branch of the SISEA Master of Research (M2R).


Enssat stands for ”École Nationale Supérieure des Sciences Appliquées et de Technologie” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Lannion.

ISTIC is the Electrical Engineering and Computer Science Department of the University of Rennes 1.

Esir stands for ”École supérieure d'ingénieur de Rennes” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Rennes.

M2R stands for Master by Research, second year.


D. Chillet is member of the French National University Council since 2009 in signal processing and electronics (Conseil National des Universités en 61e section).

D. Chillet is member of the Permanent Committee of the French National University Council since november 2011 in signal processing and electronics (Commission Permanente du Conseil National des Universités en 61e section).


  • O. Berder: introduction to signal processing, 38h, Enssat (L3)

  • O. Berder: microprocessors and digital systems, 19h, Enssat (L3)

  • O. Berder: wireless communications, 23h, Enssat (M2)

  • O. Berder: digital signal processing, 60h, Enssat (M1)

  • O. Berder: ad hoc networks, 58h, Enssat (M1-M2)

  • O. Berder: signal processing, 24h, IUT Lannion (L2)

  • E. Casseau: verification, 12h, Master by Research and Enssat (M2)

  • E. Casseau: hardware description language, 20h, Enssat (M1)

  • E. Casseau: low power design, 6h, Enssat (M1)

  • E. Casseau: real time design methodology, 24h, Enssat (M1)

  • E. Casseau: verification, 25h, USTH (M1)

  • E. Casseau: signal processing, 16h, Enssat (L3)

  • S. Derrien: component and system synthesis, 16h, Research Master (MRI ISTIC) (M2)

  • S. Derrien: computer architecture, 12h, ENS Cachan (L3)

  • S. Derrien: introduction to operating systems, 8h, ISTIC (M1)

  • F. Charot: specification of applications with the signal synchronous language, 24h, Esir (M1)

  • F. Charot: virtual prototyping of multiprocessor system-on-chip, 24h, Esir (M1)

  • F. Charot: design of embedded systems, 28h, Esir (M1)

  • D.Chillet: Basic processor architecture, 20h, Enssat (L1)

  • D.Chillet: Design methodology of real-time systems, 32h, Enssat (L2)

  • D.Chillet: Advanced processor architectures, 24h, Enssat (M2)

  • D.Chillet: Multimedia processor architectures, 24h, Enssat (M2)

  • D.Chillet: Multi-processor systems, 20h, Enssat (M2)

  • D. Chillet: advanced processors architectures, 24h, Master by Research and Enssat (M2)

  • D. Chillet: low-power digital CMOS circuits, 6h, Telecom Bretagne and University of Occidental Brittany (UBO) (M2)

  • D. Chillet: Digital system design, 25h, University of Science and Technology of Hanoi, (M1)

  • D. Chillet: Advanced Multiprocessor system , 25h, University of Science and Technology of Hanoi, (M2)

  • M.Gautier, electronics, 42h, IUT Lannion (L1)

  • M.Gautier, telecommunications, 114h, IUT Lannion (L1)

  • R. Rocher: electricity, 16h, IUT Lannion (L1)

  • R. Rocher: electronics, 44h, IUT Lannion (L1)

  • R. Rocher: telecommunications, 82h, IUT Lannion (L1)

  • R. Rocher: signal processing, 12h, IUT Lannion (L2)

  • R. Rocher: digital communications, 48h, IUT Lannion (L2)

  • P. Scalart: non-linear optimisation, 18h, Master by Research and ENSSAT (M2)

  • P. Scalart: Parametric modelisation, optimal and adaptive Filters, 24h, Master by Research and ENSSAT (M2)

  • P. Scalart: source coding, 14h, Master by Research and ENSSAT (M2)

  • P. Scalart: cellular networks, 24h, ENSSAT (M2)

  • P. Scalart: digital communication systems, 32h, ENSSAT (M1)

  • P. Scalart: random signals and systems, 12h, ENSSAT (M1)

  • O. Sentieys: methodologies for system-on-chip design, 6h, Master by Research and Enssat (M2)

  • O. Sentieys: VLSI integrated circuit design, 66h, Enssat (M1)

  • O. Sentieys: high-level synthesis of digital signal processors, 16h, Master by Research and Enssat (M2)

  • A. Tisserand: GPU programming, 8h, Enssat (M2)

  • A. Tisserand: hardware computer arithmetic operators, 6h, Master by Research, Univ. Rennes 1 (M2)

  • A. Tisserand: computer arithmetic, 12h, ENS Cachan, Antenne de Bretagne, Magister Computer Science and Telecommunications (L3)

  • A. Tisserand: computer arithmetic, 16h, ENSEIRB, (L3)

  • C. Wolinski: architecture 1, 64h, Esir (L3)

  • C. Wolinski: architecture 2, 28h, Esir (L3)

  • C. Wolinski: design of embedded systems, 48h, Esir (M1)

  • C. Wolinski: signal, image, architecture, 26h, Esir (M1)

  • C. Wolinski: programmable architectures, 10h, Esir (M1)

  • C. Wolinski: component and system synthesis, 10h, Master by Research (MRI ISTIC) (M2)


  • HDR: Olivier Berder, Systèmes multi-antennes et optimisation énergétique des réseaux de capteurs sans fil, Habilitation à Diriger des Recherches, University of Rennes 1, Dec. 2012.

  • PhD: Naeem Abbas, Acceleration of a Bioinformatics Application using High-Level Synthesis, May 2012, P. Quinton, S. Derrien.

  • PhD: Andrei Banciu, A Stochastic Approach for the Range Evaluation, Feb. 2012, E. Casseau.

  • PhD: Antoine Eiche, Real-Time Scheduling for Heterogeneous and Reconfigurable Architectures using Neural Network Structures, University of Rennes 1, Sep. 2012, D.Chillet.

  • PhD: Antoine Floc'h, Optimizing Compilation for Processor Instruction-Set Extension, Jun. 2012, C. Wolinski, F. Charot.

  • PhD: Quoc-Tuong Ngo, Generalized minimum Euclidean distance based precoders for MIMO spatial multiplexing systems, Jan. 2012, P. Scalart, O. Berder.

  • PhD: Danuta Pamula, Arithmetic operators on GF(2 m ) for cryptographic applications: performance - power consumption - security tradeoffs, University of Rennes 1 and Silesian University of Technology, Dec. 2012, A. Tisserand.

  • PhD: Le-Quang-Vinh Tran, Energy-efficient cooperative relay protocols for wireless sensor networks, Dec. 2012, O. Berder, O. Sentieys.

  • PhD: Karthick Parashar, System-level approaches for fixed-point refinement of signal processing algorithms, Dec. 2012, O. Sentieys, D. Menard.

  • PhD: Chenglong Xiao, Custom Operator Identification for High-level Synthesis, University of Rennes 1, Nov. 2012, E. Casseau.

  • PhD in progress: Mahtab Alam, Power Aware Signal Processing for Reconfigurable Radios in the context of Wireless Sensor Networks, Nov. 2009, O. Sentieys, O. Berder, D. Menard.

  • PhD in progress: Djamel Benfarhat, Design of disruption-tolerant communication protocols for mobile communicating objects in health applications, 2009, Patrice Quinton jointly with Frédéric Guidec, IRISA UBS.

  • PhD in progress: Karim Bigou, RNS Hardware Units for ECC, Oct. 2011, A. Tisserand.

  • PhD in progress: Robin Bonamy, Power Consumption Modelling and Optimisation for Reconfigurable Platform, Oct. 2009, D. Chillet.

  • PhD in progress: Franck Bucheron, Secure Virtualization for Embedded Systems, Oct. 2011, A. Tisserand.

  • PhD in progress: Thomas Chabrier, Reconfigurable Arithmetic Units for Cryptoprocessors with Protection against Side Channel Attacks, Oct. 2009, A. Tisserand, E. Casseau.

  • PhD in progress: Aymen Chakhari, Analytical approach for decision errors in fixed-point digital communication systems, Oct. 2010, R. Rocher, P. Scalart.

  • PhD in progress: Ali-Hassan El-Moussaw, Performance/Accuracy Trade-Off in Automatic Parallelization for Embedded Many-Core Platforms, Nov. 2012, S. Derrien.

  • PhD in progress: Clément Guy, Generic Definition of Domain Specific Analysis using MDE, Oct. 2010, S. Derrien, jointly with J.M. Jezequel and B. Combemale from Triskell EPI.

  • PhD in progress: Christophe Huriaux, Embedded reconfigurable hardware accelerators with efficient dynamic reconfiguration management, Oct. 2012, O. Sentieys, A. Courtay.

  • PhD in progress: Quang-Hai Khuat, Real-Time Spatio-Temporal Task Scheduling on 3D Architectures, Oct. 2011, D. Chillet.

  • PhD in progress: Trong-Nhan Le, Global power management system for self-powered autonomous wireless sensor nodes, Jan. 2011, O. Sentieys, O. Berder.

  • PhD in progress: Quang-Hoa Le, Virtualized dynamic reconfiguration for 3D SoC, Oct. 2012, E. Casseau, A. Courtay.

  • PhD in progress: Jérémie Métairie, Reconfigurable Arithmetic Units for Secure Cryptoprocessors, Oct. 2012, A. Tisserand, E. Casseau.

  • PhD in progress: Antoine Morvan, Loop Transformations for Design Space Exploration in High-Level Synthesis, Oct. 2009, P. Quinton, S. Derrien.

  • PhD in progress: Jean-Charles Naud, Source-to-Source Code Transformation for Fixed-Point Conversion, Oct. 2009, D. Menard, O. Sentieys.

  • PhD in progress: Viet-Hoa Nguyen, Energy-efficient cooperative techniques for Wireless Body Area Sensor Networks, Nov. 2012, O. Berder, jointly with C. Langlais from Telecom Bretagne.

  • PhD in progress: Matthieu Texier, Low-Power Embedded Multi-Core Architectures for Mobile Systems, Oct. 2009, O. Sentieys, jointly with R. David from CEA List.

  • PhD in progress: Michel Theriault, Transmit Beam-forming for Distributed Wireless Access with Centralized Signal Processing, Oct. 2007, O. Sentieys, jointly with S. Roy from U. Laval, Canada.

  • PhD in progress: Vivek D. Tovinakere, Ultra-Low Power Reconfigurable Controllers for Wireless Sensor Networks, Oct. 2009, O. Sentieys.

  • Ganda-Stéphane Ouedraogo, Automatic synthesis of hardware accalerator from high-level specifications in flexible radios, Oct. 2011, M. Gautier, O. Sentieys.

  • PhD in progress: Pramod P. Udupa, Sampling, synchronising, digital processing and FPGA implementation of 100Gbps optical OFDM signals, Jan. 2011, O. Sentieys.

  • PhD in progress: Hervé Yviquel, Video coding design framework based on SoC-based platforms, Oct. 2010, E. Casseau.

  • PhD in progress: Zhongwei Zheng, Short-range geolocation algorithms based on distributed multi-sensor processing, Nov. 2012, P. Scalart, jointly with C. Roland from Lab-STICC.