Section: New Results
Interaction Between Spilling and Scheduling
Participants : Quentin Colombet, Alain Darte, Fabrice Rastello.
As explained in Section
6.9 , it is
possible to decouple the register allocation problem in two successive phases:
a first spilling phase places load and store
instructions so that the register pressure at all program points is small
enough, a second assignment and coalescing phase maps the remaining
variables to physical registers and reduces the number of move
instructions among registers. At CASES'11 [18] , we presented
a new integer linear programming (ILP) formulation, for load-store
architectures, to capture “optimal” spilling in a more accurate and more
expressive way than previous approaches. Among other features, we can express
SSA
We used this ILP formulation to experimentally analyze the impact of the different heuristic strategies and compare them with optimal solutions. While “optimal” solutions show significant improvements for static spill costs, it turned out that runtime performances were disappointing (if not random). We conducted various experiments to understand this behavior and discovered that the interaction with scheduling is actually higher than expected. Micro-architectural features (e.g., memory latencies that can be hidden by prefetching, bundling that can hide cycles) have to be accounted for in the model, which is never done. These experiments and analysis are described in Chapter 4 of Quentin Colombet's PhD thesis [1] .