EN FR
EN FR
COMPSYS - 2012
COMPSYS - 2012




Project-Team Compsys
Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Bilateral Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography




Project-Team Compsys
Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Bilateral Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography


previous Previous | up Home


Bibliography

Publications of the year

Doctoral Dissertations and Habilitation Theses

  • 1Q. Colombet.

    Decoupled (SSA-based) Register Allocators: From Theory to Practice, Coping with Just-In-Time Compilation and Embedded Processors Constraints, École normale supérieure de Lyon, December 2012, 224 p.

    http://hal.inria.fr/hal-00761572
  • 2F. Rastello.

    On Sparse Intermediate Representations: Some Structural Properties and Applications to Just-In-Time Compilation, École normale supérieure de Lyon, December 2012, 154 p, Habilitation à Diriger des Recherches, Travaux universitaires.

    http://hal.inria.fr/hal-00761555

Articles in International Peer-Reviewed Journals

  • 3C. Alias, B. Pasca, A. Plesco.

    FPGA-Specific Synthesis of Loop Nests with Pipelined Computational Cores, in: Microprocessors and Microsystems - Embedded Hardware Design, 2012, vol. 36, no 8, p. 606-619.

    http://hal.inria.fr/hal-00761515
  • 4B. Boissinot, P. Brisk, A. Darte, F. Rastello.

    SSI Properties Revisited, in: ACM Transactions on Embedded Computing Systems, 2012, vol. 11S, no 1, Article 21, 23 pages.

    http://hal.inria.fr/hal-00761505
  • 5F. Brandner, Q. Colombet.

    Elimination of parallel copies using code motion on data dependence graphs, in: Computer Languages, Systems & Structures, April 2013, vol. 39, no 1, p. 25 - 47, To appear. [ DOI : 10.1016/j.cl.2012.09.001 ]

    http://hal.inria.fr/hal-00768781

International Conferences with Proceedings

  • 6C. Alias, A. Darte, A. Plesco.

    Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA, in: 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'12), New Orleans, United States, IEEE Computer Society, 2012, p. 285–286, Short paper.

    http://hal.inria.fr/hal-00761473
  • 7C. Alias, A. Darte, A. Plesco.

    Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA, in: 2nd International Workshop on Polyhedral Compilation Techniques (IMPACT'12), held with HIPEAC'12, Paris, France, 2012, PPoPP'12 extended version.

    http://hal.inria.fr/hal-00761477
  • 8C. Alias, A. Darte, A. Plesco.

    Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA, in: Design, Automation, and Test in Europe (DATE'13), Grenoble, France, 2013, To appear.

    http://hal.inria.fr/hal-00761533
  • 9G. Andrieu, C. Alias, L. Gonnord.

    SToP: Scalable Termination Analysis of (C) Programs (tool presentation), in: International Workshop on Tools for Automatic Program Analysis (TAPAS'12), Deauville, France, September 2012.

    http://hal.inria.fr/hal-00760926
  • 10F. Brandner, Q. Colombet.

    Copy Elimination on Data Dependence Graphs, in: 27th Annual ACM Symposium on Applied Computing (SAC'12), Trento, Italy, ACM Press, 2012, p. 1916-1918.

    http://hal.inria.fr/hal-00761499
  • 11B. Diouf, A. Cohen, F. Rastello.

    A Polynomial Spilling Heuristic: Layered Allocation, in: International Symposium on Code Generation and Optimization (CGO'13), Shenzhen, China, IEEE Computer Society Press, 2013, To appear.

    http://hal.inria.fr/hal-00761528
  • 12P. Feautrier.

    Approximating the Transitive Closure of a Boolean-Affine Relation, in: 2nd International Workshop on Polyhedral Compilation Techniques (IMPACT'12), held with HIPEAC'12, Paris, France, 2012.

    http://hal.inria.fr/hal-00761491
  • 13T. Yuki, P. Feautrier, S. Rajopadhye, V. Saraswat.

    Array Dataflow Analysis for Polyhedral X10 Programs, in: 18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'13), Shenzhen, China, ACM, 2013, To appear.

    http://hal.inria.fr/hal-00761537

Internal Reports

References in notes
  • 16C. Alias, A. Darte, P. Feautrier, L. Gonnord.

    Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs, in: 17th International Static Analysis Symposium (SAS'10), Perpignan, France, ACM press, September 2010, p. 117-133.
  • 17P. Boulet, P. Feautrier.

    Scanning Polyhedra without DO loops, in: PACT'98, October 1998.
  • 18Q. Colombet, F. Brandner, A. Darte.

    Studying Optimal Spilling in the Light of SSA, in: International Conference on Compilers, Architectures, and Synthesis of Embedded Systems (CASES'11), Taipei, Taiwan, IEEE Computer Society, October 2011.
  • 19A. Darte, R. Schreiber, G. Villard.

    Lattice-Based Memory Allocation, in: IEEE Transactions on Computers, October 2005, vol. 54, no 10, p. 1242-1257, Special Issue: Tribute to B. Ramakrishna (Bob) Rau.
  • 20B. Dupont de Dinechin, C. Monat, F. Rastello.

    Parallel Execution of Saturated Reductions, in: Workshop on Signal Processing Systems (SIPS'01), IEEE Computer Society Press, 2001, p. 373-384.
  • 21P. Feautrier.

    Scalable and Structured Scheduling, in: International Journal of Parallel Programming, October 2006, vol. 34, no 5, p. 459–487.
  • 22P. Feautrier.

    Bernstein's Conditions, in: Encyclopedia of Parallel Programming, D. Padua (editor), Springer, 2011, to appear.
  • 23P. Feautrier.

    Dataflow Analysis of Scalar and Array References, in: International Journal of Parallel Programming, February 1991, vol. 20, no 1, p. 23–53.
  • 24A. Fraboulet, K. Godary, A. Mignotte.

    Loop Fusion for Memory Space Optimization, in: IEEE International Symposium on System Synthesis, Montréal, Canada, IEEE Press, October 2001, p. 95–100.
  • 25A. Gamatié, L. Gonnord.

    Static Analysis of Synchronous Programs in Signal for Efficient Design of Multi-Clocked Embedded Systems, in: International conference on Languages, Compilers and Tools for Embedded Systems, LCTES'11, Chicago, USA, April 2011.
  • 26J.-W. Hong, H. T. Kung.

    I/O Complexity: The Red-Blue Pebble Game, in: 13th Annual ACM Symposium on Theory of Computing (STOC'81), ACM, 1981, p. 326–333.
  • 27R. Johnson, M. Schlansker.

    Analysis of Predicated Code, in: International Workshop on Microprogramming and Microarchitecture (Micro-29), 1996.
  • 28J. Le Guen, C. Guillon, F. Rastello.

    MinIR, a Minimalistic Intermediate Representation, in: Workshop on Intermediate Representations (WIR'11), held with CGO'11, Chamonix, F. Bouchez, S. Hack, E. Visser (editors), April 2011, p. 5-12.
  • 29A. Stoutchinin, F. De Ferrière.

    Efficient Static Single Assignment Form for Predication, in: International Symposium on Microarchitecture, ACM SIGMICRO and IEEE Computer Society TC-MICRO, 2001.
  • 30A. Turjan, B. Kienhuis, E. Deprettere.

    Translating affine nested-loop programs to process networks, in: International conference on Compilers, architecture, and synthesis for embedded systems (CASES'04), New York, NY, USA, ACM, 2004, p. 220–229.
  • 31S. Verdoolaege, H. Nikolov, N. Todor, P. Stefanov.

    Improved derivation of process networks, in: International Workshop on Optimization for DSP and Embedded Systems (ODES'06, 2006.


previous Previous | up Home