Bibliography

Publications of the year

Doctoral Dissertations and Habilitation Theses

• 1F. Li.
  
  Compiling for a multithreaded dataflow architecture : algorithms, tools, and experience, Université Pierre et Marie Curie - Paris VI, May 2014.
  
  https://tel.archives-ouvertes.fr/tel-00992753
• 2F. Zappa Nardelli.
  
  Reasoning between Programming Languages and Architectures, ENS Paris - Ecole Normale Supérieure de Paris, January 2014, Habilitation à diriger des recherches.
  
  https://hal.inria.fr/tel-01110117

Articles in International Peer-Reviewed Journals

• 3R. Giorgi, R. M. Badia, F. Bodin, A. Cohen, P. Evripidou, P. Faraboschi, B. Fechner, G. R. Gao, A. Garbade, R. Gayatri, S. Girbal, D. Goodman, B. Khan, S. Koliaï, J. Landwehr, N. Minh, F. Li, M. Lujàn, A. Mendelson, L. Morin, N. Navarro, T. Patejko, A. Pop, P. Trancoso, T. Ungerer, I. Watson, S. Weis, S. Zuckerman, M. Valero.
  
  TERAFLUX: Harnessing dataflow in next generation teradevices, in: Microprocessors and Microsystems, 2014, pp. 976-990, Available online 18 April 2014. [ DOI : 10.1016/j.micpro.2014.04.001 ]
  
  https://hal.inria.fr/hal-00992721

International Conferences with Proceedings

• 4A. Benveniste, B. Caillaud, B. Pagano, M. Pouzet.
  
  A type-based analysis of causality loops in hybrid modelers, in: HSCC '14: International Conference on Hybrid Systems: Computation and Control, Berlin, Germany, Proceedings of the 17th international conference on Hybrid systems: computation and control (HSCC '14), ACM Press, April 2014, 13 p. [ DOI : 10.1145/2562059.2562125 ]
  
  https://hal.inria.fr/hal-01093388
• 5T. Bourke, R. J. van Glabbeek, P. Höfner.
  
  A Mechanized Proof of Loop Freedom of the (Untimed) AODV Routing Protocol, in: ATVA 2014: Automated Technology for Verification and Analysis, Sydney, Australia, Lecture Notes in Computer Science, Springer, November 2014, vol. 8837, 17 p. [ DOI : 10.1007/978-3-319-11936-6_5 ]
  
  https://hal.inria.fr/hal-01092360
• 6T. Bourke, R. J. van Glabbeek, P. Höfner.
  
  Showing Invariance Compositionally for a Process Algebra for Network Protocols, in: ITP 2014: Interactive Theorem Proving, Vienna, Austria, Lecture Notes in Computer Science, Springer, July 2014, vol. 8558, 16 p. [ DOI : 10.1007/978-3-319-08970-6_10 ]
  
  https://hal.inria.fr/hal-01092348
• 7A. Delpeuch, A. Preller.
  
  From Natural Language to RDF Graphs with Pregroups, in: EACL'2014: 14th Conference of the European Chapter of the Association for Computational Linguistics, Gothenburg, Sweden, EACL, April 2014, pp. 55-62.
  
  http://hal-lirmm.ccsd.cnrs.fr/lirmm-00992381
• 8T. Grosser, A. Cohen, J. Holewinski, P. Sadayappan, S. Verdoolaege.
  
  Hybrid Hexagonal/Classical Tiling for GPUs, in: Intl. Symp. on Code Generation and Optimization (CGO), Orlando, FL, United States, February 2014.
  
  https://hal.inria.fr/hal-00911177
• 9N. Hili, C. Fabre, S. Dupuy-Chessa, D. Rieu, I. Llopard.
  
  Model-Based Platform Composition for Embedded System Design, in: 2014 IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, Aizu-Wakamatsu, Japan, University of Aizu, September 2014.
  
  https://hal.inria.fr/hal-01071208
• 10I. Llopard, A. Cohen, C. Fabre, N. Hili.
  
  A Parallel Action Language for Embedded Applications and its Compilation Flow, in: 17th International Workshop on Software and Compilers for Embedded Systems, Sankt Goar, Germany, Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems, June 2014, pp. 118-127. [ DOI : 10.1145/2609248.2609257 ]
  
  https://hal.inria.fr/hal-01001900
• 11L. Mandel, C. Pasteur.
  
  Reactivity of Cooperative Systems, in: Static Analysis (SAS), Munich, Germany, Lecture Notes in Computer Science, Springer, September 2014, vol. 8723, 17 p. [ DOI : 10.1007/978-3-319-10936-7_14 ]
  
  https://hal.inria.fr/hal-01093169
• 12K. Stock, M. Kong, T. Grosser, L.-N. Pouchet, F. Rastello, J. Ramanujam, P. Sadayappan.
  
  A Framework for Enhancing Data Reuse via Associative Reordering, in: PLDI '14 - 35th ACM SIGPLAN Conference on Programming Language Design and Implementation, Edinburgh, United Kingdom, ACM, June 2014, pp. 65-76. [ DOI : 10.1145/2594291.2594342 ]
  
  https://hal.inria.fr/hal-01016093
• 13V. Vafeiadis, T. Balabonski, S. Chakraborty, R. Morisset, F. Zappa Nardelli.
  
  Common compiler optimisations are invalid in the C11 memory model and what we can do about it, in: POPL 2015 - 42nd ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, Mumbai, India, January 2015.
  
  https://hal.inria.fr/hal-01089047
• 14S. Verdoolaege, S. Guelton, T. Grosser, A. Cohen.
  
  Schedule Trees, in: IMPACT - 4th Workshop on Polyhedral Compilation Techniques, associated with HiPEAC, Vienna, Austria, ACM, January 2014.
  
  https://hal.inria.fr/hal-00911894

National Conferences with Proceedings

• 15A. Guatto, L. Mandel.
  
  Réseaux de Kahn à rafales et horloges entières, in: JFLA 2014 - Vingt-cinquièmes Journées Francophones des Langages Applicatifs, Fréjus, France, January 2014.
  
  https://hal.inria.fr/hal-00919281
• 16L. Mandel, C. Pasteur.
  
  Exécution efficace de programmes ReactiveML, in: JFLA 2014 - Vingt-cinquièmes Journées Francophones des Langages Applicatifs, Fréjus, France, January 2014.
  
  https://hal.inria.fr/hal-00919271

Internal Reports

• 17G. Baudart, A. Benveniste, A. Bouillard, P. Caspi.
  
  A Unifying View of Loosely Time-Triggered Architectures, March 2014, n^o RR-8494, 14 p.
  
  https://hal.inria.fr/hal-00955496
• 18A. Benveniste, T. Bourke, B. Caillaud, M. Pouzet.
  
  On the index of multi-mode DAE Systems (also called Hybrid DAE Systems), Inria ; ENS, November 2014, n^o RR-8630, 30 p.
  
  https://hal.inria.fr/hal-01084069
• 19L. Mandel, C. Pasteur.
  
  Reactivity of Cooperative Systems: Application to ReactiveML – extended version, June 2014, n^o RR-8549, 29 p.
  
  https://hal.inria.fr/hal-01010349

Other Publications

• 20T. Bourke.
  
  Mechanization of the Algebra for Wireless Networks (AWN), August 2014, 186 p, Entry in the Archive of Formal Proofs (ISSN: 2150-914x).
  
  https://hal.inria.fr/hal-01104031
• 21T. Bourke, P. Höfner.
  
  Loop freedom of the (untimed) AODV routing protocol, October 2014, 496 p, Entry in the Archive of Formal Proofs (ISSN: 2150-914x).
  
  https://hal.inria.fr/hal-01104033
• 22G. Richards, F. Zappa Nardelli, J. Vitek.
  
  Concrete Types for JavaScript, 2014, forthcoming.
  
  https://hal.inria.fr/hal-00909092

References in notes

• 23R. Baghdadi, A. Cohen, S. Verdoolaege, K. Trifunović.
  
  Improved Loop Tiling based on the Removal of Spurious False Dependences, in: ACM Transactions on Architecture and Code Optimization, 2013, vol. 9, n^o 4, Selected for presentation at the HiPEAC 2013 Conf. [ DOI : 10.1145/2400682.2400711 ]
  
  https://hal.inria.fr/hal-00786674
• 24A. Benveniste, A. Bouillard, P. Caspi.
  
  A unifying view of loosely time-triggered architectures, in: EMSOFT, 2010, pp. 189–198.
• 25A. Benveniste, P. Caspi, M. Di Natale, C. Pinello, A. Sangiovanni-Vincentelli, S. Tripakis.
  
  Loosely time-triggered architectures based on communication-by-sampling, in: EMSOFT, 2007, pp. 231–239.
• 26D. Biernacki, J.-L. Colaço, G. Hamon, M. Pouzet.
  
  Clock-directed Modular Code Generation of Synchronous Data-flow Languages, in: ACM International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES), Tucson, Arizona, June 2008.
• 27F. Boussinot, R. de Simone.
  
  The SL synchronous language, in: IEEE Transaction on Software Engineering, 1996.
• 28P. Caspi, A. Benveniste.
  
  Time-robust discrete control over networked loosely time-triggered architectures, in: CDC, 2008, pp. 3595–3600.
• 29P. Caspi.
  
  The Quasi-Synchronous Approach to Distributed Control Systems, VERIMAG, Crysis Project, May 2000, n^o CMA/009931, The Cooking Book.
• 30P. Caspi, M. Pouzet.
  
  Synchronous Kahn Networks, in: ACM SIGPLAN International Conference on Functional Programming (ICFP), Philadelphia, Pensylvania, May 1996.
• 31P. Caspi, M. Pouzet.
  
  A Co-iterative Characterization of Synchronous Stream Functions, in: Coalgebraic Methods in Computer Science (CMCS'98), Electronic Notes in Theoretical Computer Science, March 1998, Extended version available as a VERIMAG tech. report no. 97–07.
• 32A. Cohen, M. Duranton, C. Eisenbeis, C. Pagetti, F. Plateau, M. Pouzet.
  
  Synchroning Periodic Clocks, in: ACM International Conference on Embedded Software (EMSOFT'05), Jersey city, New Jersey, USA, September 2005.
• 33A. Cohen, M. Duranton, C. Eisenbeis, C. Pagetti, F. Plateau, M. Pouzet.
  
  $N$-Synchronous Kahn Networks: a Relaxed Model of Synchrony for Real-Time Systems, in: ACM International Conference on Principles of Programming Languages (POPL'06), Charleston, South Carolina, USA, January 2006.
• 34A. Cohen, S. Girbal, D. Parello, M. Sigler, O. Temam, N. Vasilache.
  
  Facilitating the Search for Compositions of Program Transformations, in: Intl. Conf. on Supercomputing (ICS'05), Boston, Massachusetts, June 2005, pp. 151–160.
• 35A. Cohen, S. Girbal, O. Temam.
  
  A Polyhedral Approach to Ease the Composition of Program Transformations, in: Euro-Par'04, Pisa, Italy, LNCS, Springer-Verlag, August 2004, n^o 3149, pp. 292–303.
• 36A. Cohen, T. Grosser, P. H. J. Kelly, J. Ramanujam, P. Sadayappan, S. Verdoolaege.
  
  Split Tiling for GPUs: Automatic Parallelization Using Trapezoidal Tiles to Reconcile Parallelism and Locality, avoiding Divergence and Load Imbalance, in: GPGPU 6 - Sixth Workshop on General Purpose Processing Using GPUs, Houston, United States, March 2013.
  
  https://hal.inria.fr/hal-00786812
• 37A. Cohen, L. Mandel, F. Plateau, M. Pouzet.
  
  Abstraction of Clocks in Synchronous Data-flow Systems, in: The Sixth ASIAN Symposium on Programming Languages and Systems (APLAS), Bangalore, India, December 2008.
• 38A. Cohen, L. Mandel, F. Plateau, M. Pouzet.
  
  Relaxing Synchronous Composition with Clock Abstraction, 2009, Workshop on Hardware Design using Functional languages (HFL 09) - ETAPS.
  
  http://hal.inria.fr/hal-00645333
• 39J.-L. Colaço, G. Hamon, M. Pouzet.
  
  Mixing Signals and Modes in Synchronous Data-flow Systems, in: ACM International Conference on Embedded Software (EMSOFT'06), Seoul, South Korea, October 2006.
• 40J.-L. Colaço, B. Pagano, M. Pouzet.
  
  A Conservative Extension of Synchronous Data-flow with State Machines, in: ACM International Conference on Embedded Software (EMSOFT'05), Jersey city, New Jersey, USA, September 2005.
• 41J.-L. Colaço, M. Pouzet.
  
  Clocks as First Class Abstract Types, in: Third International Conference on Embedded Software (EMSOFT'03), Philadelphia, Pennsylvania, USA, october 2003.
• 42J.-L. Colaço, M. Pouzet.
  
  Type-based Initialization Analysis of a Synchronous Data-flow Language, in: International Journal on Software Tools for Technology Transfer (STTT), August 2004, vol. 6, n^o 3, pp. 245–255.
• 43J. Cortadella, M. Kishinevsky.
  
  Synchronous Elastic Circuits with Early Evaluation and Token Counterflow, in: DAC, 2007, pp. 416-419.
• 44P. Cuoq, M. Pouzet.
  
  Modular Causality in a Synchronous Stream Language, in: European Symposium on Programming (ESOP'01), Genova, Italy, April 2001.
• 45P. Feautrier.
  
  Some Efficient Solutions to the Affine Scheduling Problem, Part II, multidimensional time, in: Intl. J. of Parallel Programming, December 1992, vol. 21, n^o 6, pp. 389-420, See also Part I, one dimensional time, 21(5):315–348.
• 46A. Gamatié, E. Rutten, H. Yu, P. Boulet, J.-L. Dekeyser.
  
  Synchronous Modeling and Analysis of Data Intensive Applications, in: EURASIP Journal on Embedded Systems, 2008.
• 47S. Girbal, N. Vasilache, C. Bastoul, A. Cohen, D. Parello, M. Sigler, O. Temam.
  
  Semi-Automatic Composition of Loop Transformations for Deep Parallelism and Memory Hierarchies, in: Intl. J. of Parallel Programming, June 2006, vol. 34, n^o 3, pp. 261–317, Special issue on Microgrids.
• 48T. Grosser, A. Cohen, J. Holewinski, P. Sadayappan, S. Verdoolaege.
  
  Hybrid Hexagonal/Classical Tiling for GPUs, in: Intl. Symp. on Code Generation and Optimization (CGO), Orlando, FL, United States, February 2014.
  
  https://hal.inria.fr/hal-00911177
• 49T. Grosser, A. Größlinger, C. Lengauer.
  
  Polly - Performing Polyhedral Optimizations on a Low-Level Intermediate Representation, in: Parallel Processing Letters, 2012, vol. 22, n^o 4.
• 50A.-C. Guillou, F. Quilleré, P. Quinton, S. Rajopadhye, T. Risset.
  
  Hardware Design Methodology with the Alpha Language, in: FDL'01, Lyon, France, September 2001.
• 51H. Leverge, C. Mauras, P. Quinton.
  
  The Alpha language and its use for the design of systolic arrays, in: J. of VLSI Signal Processing, 1991, vol. 3, pp. 173–182.
• 52L. Mandel, F. Benbadis.
  
  Simulation of Mobile Ad hoc Network Protocols in ReactiveML, in: Proceedings of Synchronous Languages, Applications, and Programming (SLAP'05), Edinburgh, Scotland, Electronic Notes in Theoretical Computer Science, April 2005, Workshop ETAPS 2005.
• 53L. Mandel.
  
  Conception, Sémantique et Implantation de ReactiveML : un langage à la ML pour la programmation réactive, Université Paris 6, 2006.
• 54L. Mandel, F. Plateau, M. Pouzet.
  
  Lucy-n: a n-Synchronous Extension of Lustre, in: 10th International Conference on Mathematics of Program Construction (MPC'10), Manoir St-Castin, Québec, Canada, Springer LNCS, June 2010.
• 55L. Mandel, M. Pouzet.
  
  ReactiveML, a Reactive Extension to ML, in: ACM International Conference on Principles and Practice of Declarative Programming (PPDP), Lisboa, July 2005.
• 56F. Maraninchi, N. Berthier, O. Bezet, G. Funchal.
  
  Writing Simulators with Synchronous Languages, 2008, Synchron 2008: International Open Workshop on Synchronous Programming.
• 57C. Miranda, A. Pop, P. Dumont, A. Cohen, M. Duranton.
  
  Erbium: A Deterministic, Concurrent Intermediate Representation to Map Data-Flow Tasks to Scalable, Persistent Streaming Processes, in: Intl. Conf. on Compilers Architectures and Synthesis for Embedded Systems (CASES'10), October 2010.
• 58J.-B. Note, M. Shand, J. Vuillemin.
  
  Realtime video pixel matching, in: International Conference on Field Programmable Logic and Applications, 2006, pp. 507 – 512.
• 59J.-B. Note, J. Vuillemin.
  
  Towards automatically compiling efficient FPGA hardware, in: International Workshop on Design and Functional Languages, IEEE, 2007, pp. 115 – 124.
• 60E. Park, J. Cavazos, L.-N. Pouchet, C. Bastoul, A. Cohen, P. Sadayappan.
  
  Predictive Modeling in a Polyhedral Optimization Space, in: International Journal of Parallel Programming, 2013, vol. 41, n^o 5, pp. 704–750. [ DOI : 10.1007/s10766-013-0241-1 ]
  
  https://hal.inria.fr/hal-00918653
• 61F. Plateau.
  
  Modèle n-synchrone pour la programmation de réseaux de Kahn à mémoire bornée, Université Paris-Sud 11, Orsay, France, 6 janvier 2010.
  
  https://www.lri.fr/~mandel/lucy-n/~plateau/these/
• 62S. Pop, A. Cohen, C. Bastoul, S. Girbal, G.-A. Silber, N. Vasilache.
  
  GRAPHITE: Loop Optimizations Based on the Polyhedral Model for GCC, in: Proc. of the 4þ GCC Developper's Summit, Ottawa, Canada, June 2006.
• 63L.-N. Pouchet, C. Bastoul, A. Cohen, J. Cavazos.
  
  Iterative Optimization in the Polyhedral Model: Part II, Multidimensional Time, in: ACM Conf. on Programming Language Design and Implementation (PLDI'08), Tucson, Arizona, June 2008.
• 64L.-N. Pouchet, C. Bastoul, A. Cohen, N. Vasilache.
  
  Iterative Optimization in the Polyhedral Model: Part I, One-Dimensional Time, in: Intl. Symp. on Code Generation and Optimization (CGO'07), San Jose, California, March 2007.
• 65L.-N. Pouchet, U. Bondhugula, C. Bastoul, A. Cohen, J. Ramanujam, P. Sadayappan.
  
  Combined Iterative and Model-driven Optimization in an Automatic Parallelization Framework, in: ACM Supercomputing Conf. (SC'10), New Orleans, Lousiana, November 2010, 11 p.
• 66P. Raymond, Y. Roux, E. Jahier.
  
  Lutin: a language for specifying and executing reactive scenarios, in: EURASIP Journal on Embedded Systems, 2008, vol. 2008, Article ID 753821.
• 67L. Samper, F. Maraninchi, L. Mounier, L. Mandel.
  
  GLONEMO: Global and Accurate Formal Models for the Analysis of Ad hoc Sensor Networks, in: Proceedings of the First International Conference on Integrated Internet Ad hoc and Sensor Networks (InterSense'06), Nice, France, May 2006.
• 68J. Soula, P. Marquet, J.-L. Dekeyser, A. Demeure.
  
  Compilation principle of a specification language dedicated to signal processing, in: Intl. Conf. on Parallel Computing Technologies, Novosibirsk, Russia, LNCS, Springer-Verlag, September 2001, vol. 2127, pp. 358–370.
• 69K. Trifunović, A. Cohen, D. Edelsohn, F. Li, T. Grosser, H. Jagasia, R. Ladelski, S. Pop, J. Sjödin, R. Upadrasta.
  
  GRAPHITE Two Years After: First Lessons Learned From Real-World Polyhedral Compilation, in: GCC Research Opportunities Workshop (GROW'10), Pisa, Italy, January 2010.
• 70K. Trifunović, D. Nuzman, A. Cohen, A. Zaks, I. Rosen.
  
  Polyhedral-Model Guided Loop-Nest Auto-Vectorization, in: Parallel Architectures and Compilation Techniques (PACT'09), Raleigh, North Carolina, September 2009.
• 71S. Verdoolaege, S. Guelton, T. Grosser, A. Cohen.
  
  Schedule Trees, in: IMPACT - 4th Workshop on Polyhedral Compilation Techniques, associated with HiPEAC, Vienna, Austria, ACM, January 2014.
  
  https://hal.inria.fr/hal-00911894
• 72S. Verdoolaege, J. C. Juega, A. Cohen, J. I. Gómez, C. Tenllado, F. Catthoor.
  
  Polyhedral Parallel Code Generation for CUDA, in: ACM Transactions on Architecture and Code Optimization, 2013, vol. 9, n^o 4, Selected for presentation at the HiPEAC 2013 Conf.. [ DOI : 10.1145/2400682.2400713 ]
  
  https://hal.inria.fr/hal-00786677
• 73J. Vuillemin.
  
  On Circuits and Numbers, Digital, Paris Research Laboratory, 1993.