Major publications by the team in recent years
  • 1D. Chillet, A. Eiche, S. Pillement, O. Sentieys.

    Real-time scheduling on heterogeneous system-on-chip architectures using an optimised artificial neural network, in: Journal of Systems Architecture - Embedded Systems Design, April 2011, vol. 57, no 4, pp. 340-353.

  • 2A. Courtay, O. Sentieys, J. Laurent, N. Julien.

    High-level Interconnect Delay and Power Estimation, in: Journal of Low Power Electronics (JOLPE), 2008, vol. 4, no 1, pp. 21-33.
  • 3R. David, S. Pillement, O. Sentieys.

    Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.
  • 4S. Derrien, P. Quinton.

    Parallelizing HMMER for Hardware Acceleration on FPGAs, in: 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2007), Montreal, Canada, July 2007, pp. 10–18, Best Paper Award.
  • 5S. Derrien, S. Rajopadhye, P. Quinton, T. Risset.

    12, in: High-Level Synthesis of Loops Using the Polyhedral Model: The MMAlpha Software, P. Coussy, A. Morawiec (editors), Springer Netherlands, 2008, pp. 215-230.

  • 6L. Imbert, A. Peirera, A. Tisserand.

    A Library for Prototyping the Computer Arithmetic Level in Elliptic Curve Cryptography, in: Proc. Advanced Signal Processing Algorithms, Architectures and Implementations XVII, San Diego, California, U.S.A., F. T. Luk (editor), SPIE, August 2007, vol. 6697, no 66970N, pp. 1–9.

  • 7B. Le Gal, E. Casseau, S. Huet.

    Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis, in: IEEE Transactions on Very Large Scale Integration Systems, November 2008, vol. 16, no 11, pp. 1454-1464.
  • 8K. Martin, C. Wolinski, K. Kuchcinski, A. Floch, F. Charot.

    Constraint-Driven Instructions Selection and Application Scheduling in the DURASE system, in: Proc. of the 20th IEEE International Conference on Application-Specific Systems, Architectures and Processors, Boston, MA, USA, IEEE Computer Society, July 2009, pp. 145-152.
  • 9D. Menard, D. Chillet, O. Sentieys.

    Floating-to-fixed-point Conversion for Digital Signal Processors, in: EURASIP Journal on Applied Signal Processing (JASP), Special Issue Design Methods for DSP Systems, 2006, vol. 2006, no 1, pp. 1–15.
  • 10D. Menard, O. Sentieys.

    Automatic Evaluation of the Accuracy of Fixed-point Algorithms, in: IEEE/ACM Design, Automation and Test in Europe (DATE-02), Paris, March 2002.
  • 11S. Pillement, O. Sentieys, R. David.

    DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency, in: EURASIP Journal on Embedded Systems (JES), 2008, pp. 1-13, Article ID 562326, 13 pages.
  • 12A. Tisserand.

    High-Performance Hardware Operators for Polynomial Evaluation, in: Int. J. High Performance Systems Architecture, March 2007, vol. 1, no 1, pp. 14–23, invited paper.

  • 13C. Wolinski, K. Kuchcinski, E. Raffin.

    Automatic Design of Application-Specific Reconfigurable Processor Extensions with UPaK Synthesis Kernel, in: ACM Transactions on Design Automation of Electronic Systems, 2009, vol. 15, no 1, pp. 1–36.

Publications of the year

Doctoral Dissertations and Habilitation Theses

  • 14C. Huriaux.

    Enhanced FPGA Architecture and CAD Flow for Efficient Runtime Hardware Reconfiguration, Université de Rennes 1, December 2015.

  • 15Q. H. Khuat.

    Definition and evaluation of spatio-temporal scheduling strategies for 3D multi-core heterogeneous architectures, Université de Rennes 1, March 2015.


Articles in International Peer-Reviewed Journals

  • 16N. Abbas, S. Derrien, S. Rajopadhye, P. Quinton, A. Cornu, D. Lavenier.

    Combining execution pipelines to improve parallel implementation of HMMER on FPGA, in: Microprocessors and Microsystems, October 2015, vol. 39, pp. 457-470. [ DOI : 10.1016/j.micpro.2015.06.006 ]

  • 17V. A. Coutinho, R. J. Cintra, F. M. Bayer, S. Kulasekera, A. Madanayake.

    A multiplierless pruned DCT-like transformation for image and video compression that requires ten additions only, in: Journal of Real Time Image Processing, March 2015, pp. 1-9. [ DOI : 10.1007/s11554-015-0492-8 ]

  • 18A. Ghada, A. Tisserand, E.-M. Ahmed, W. Yasutaka.

    Towards FHE in Embedded Systems: A Preliminary Co-Design Space Exploration of a HW/SW Very Large Multiplier, in: IEEE Embedded Systems Letters, September 2015, vol. 7, no 3. [ DOI : 10.1109/LES.2015.2436372 ]

  • 19V. Kelefouras, A. Kritikakou, C. Goutis.

    A methodology for speeding up loop kernels by exploiting the software information and the memory architecture, in: Computer Languages, Systems and Structures, April 2015, vol. 41, pp. 21–41. [ DOI : 10.1016/j.cl.2015.01.003 ]

  • 20V. Kelefouras, A. Kritikakou, I. Mporas, V. Kolonias.

    A high performance Matrix-Matrix Multiplication Methodology for CPU and GPU architectures, in: Journal of Supercomputing, 2016, pp. 1-41. [ DOI : 10.1007/s11227-015-1613-7 ]

  • 21V. Kelefouras, A. Kritikakou, E. Papadima, C. Goutis.

    A methodology for speeding up matrix vector multiplication for single/multi-core architectures, in: The Journal of Supercomputing, March 2015, vol. 71, no 7, pp. 2644-2667. [ DOI : 10.1007/s11227-015-1409-9 ]

  • 22S. Khan, E. Casseau, D. Menard.

    High performance Discrete Cosine Transform (DCT) operator using multimedia oriented subword parallelism (SWP), in: Advances in Computer Engineering, February 2015, vol. 2015, 10 p, Article ID 405856. [ DOI : 10.1155/2015/405856 ]

  • 23A. Kritikakou, F. Catthoor, V. Kelefouras, C. Goutis.

    Array Size Computation under Uniform Overlapping and Irregular Accesses, in: ACM Transactions on Design Automation of Electronic Systems (TODAES), 2016.

  • 24T. N. Le, A. Pegatoquet, O. Berder, O. Sentieys, A. Carer.

    Energy Neutral Design Framework for Supercapacitor-based Autonomous Wireless Sensor Networks, in: ACM Journal on Emerging Technologies in Computing Systems, August 2015, vol. 2, no 2, August 2015, article 19 p. [ DOI : 10.1145/2787512 ]

  • 25T.-N. Le, A. Pegatoquet, O. Berder, O. Sentieys.

    Energy-Efficient Power Manager and MAC Protocol for Multi-Hop Wireless Sensor Networks Powered by Periodic Energy Harvesting Sources, in: IEEE Sensors Journal, August 2015, august 2015 p.

  • 26S. Piestrak.

    A note on RNS architectures for the implementation of the diagonal function, in: Information Processing Letters, 2015, pp. 1-9.

  • 27M. J. Sepulveda, J.-P. Diguet, M. Strum, G. Gogniat.

    NoC-Based Protection for SoC Time-Driven Attacks, in: IEEE Embedded Systems Letters, March 2015, vol. 7, no 1. [ DOI : 10.1109/LES.2014.2384744 ]

  • 28L.-Q.-V. Tran, A. Didioui, C. Bernier, G. Vaumourin, F. Broekaert, A. Fritch.

    Co-Simulating Complex Energy Harvesting WSN Applications: An In-Tunnel Wind Powered Monitoring Example, in: International Journal of Sensor Networks, 2016.


Invited Conferences

  • 29A. Tisserand.

    Hardware Accelerators for ECC and HECC, in: ECC: 19th Workshop on Elliptic Curve Cryptography, Bordeaux, France, September 2015.


International Conferences with Proceedings

  • 30V. Ariyarathna, S. Kulasekera, A. Madanayake, K.-S. Lee, D. Suarez, R. J. Cintra, F. M. Bayer, L. Belostotski.

    Multi-beam 4 GHz Microwave Apertures Using Current-Mode DFT Approximation on 65 nm CMOS, in: International Microwave Symposium (IMS), Phoenix, United States, May 2015.

  • 31A. Aulery, J.-P. Diguet, O. Sentieys, C. Roland.

    Low-complexity energy proportional posture/gesture recognition based on WBSN, in: 12th IEEE Int. Conference on Wearable and Implantable Body Sensor Networks (BSN), MIT, Cambridge, United States, June 2015.

  • 32A. Aulery, C. Roland, J.-P. Diguet, Z. Zhongwei, O. Sentieys, P. Scalart.

    Radio Signature Based Posture Recognition Using WBSN, in: The 14th International Conference on Information Processing in Sensor Networks (IPSN), Seattle, United States, April 2015.

  • 33R. Bardoux, A. Carer, A. Lebreton, L. Bramerie, P. Scalart, B. Charbonnier.

    Experimental Demonstration of Real Time Receiver for FDMA PON, in: 41st European Conference on Optical Communication (ECOC 2015), Valencia, Spain, September 2015.

  • 34B. Barrois, K. Parashar, O. Sentieys.

    Leveraging Power Spectral Density for Scalable System-Level Accuracy Evaluation, in: IEEE/ACM Conference on Design Automation and Test in Europe (DATE), Dresden, Germany, March 2016, 6 p.

  • 35F. Berthier, E. Beigne, P. VIVET, O. Sentieys.

    Power gain estimation of an event-driven wake-up controller dedicated to WSN's microcontroller, in: IEEE 13th International New Circuits and Systems Conference (NEWCAS), Grenoble, France, June 2015, pp. 1-4. [ DOI : 10.1109/NEWCAS.2015.7182064 ]

  • 36K. Bigou, A. Tisserand.

    Single Base Modular Multiplication for Efficient Hardware RNS Implementations of ECC, in: CHES: 17th International Workshop on Cryptographic Hardware and Embedded Systems, Saint-Malo, France, T. Guneysu, H. Handschuh (editors), Lecture notes in computer science, Springer, September 2015, vol. 9293, pp. 123-140. [ DOI : 10.1007/978-3-662-48324-4_7 ]

  • 37J. Chen, A. Tisserand, E. Popovici, S. Cotofana.

    Asynchronous Charge Sharing Power Consistent Montgomery Multiplier, in: ASYNC: 21st IEEE International Symposium on Asynchronous Circuits and Systems, Mountain View, Silicon Valley California, United States, May 2015.

  • 38F. Cladera, M. Gautier, O. Sentieys.

    Channel-Aware Energy Optimization of OFDM Receivers Using Dynamic Precision Scaling in FPGAs, in: European Signal Processing Conference (EUSIPCO 2015), Nice, France, August 2015.

  • 40G. Deest, N. Estibals, T. Yuki, S. Derrien, S. Rajopadhye.

    Towards Scalable and Efficient FPGA Stencil Accelerators, in: 6th International Workshop on Polyhedral Compilation Techniques (IMPACT'16), held with HIPEAC'16, Prague, Czech Republic, Proceedings of the IMPACT series, January 2016, http://impact.gforge.inria.fr/ .

  • 41A. Gammoudi, A. Benzina, M. Khalgui, D. Chillet.

    New Pack Oriented Solutions for Energy-Aware Feasible Adaptive Real-Time Systems, in: International Conference on Intelligent Software Methodologies, Tools and Techniques, SoMeT 15, Naples, Italy, University of Naples "Federico II", ITALY, September 2015. [ DOI : 10.1007/978-3-319-22689-7_6 ]

  • 42C. Huriaux, A. Courtay, O. Sentieys.

    Design Flow and Run-Time Management for Compressed FPGA Configurations, in: DATE - Design, Automation and Test in Europe, Grenoble, France, March 2015.

  • 43B. Janßen, F. Schwiegelshohn, M. Koedam, F. Duhem, L. Masing, S. Werner, C. Huriaux, A. Courtay, E. Wheatley, K. Goossens, F. Lemonnier, P. Millet, J. Becker, O. Sentieys, M. Hübner.

    Designing Applications for Heterogeneous Many-Core Architectures with the FlexTiles Platform, in: SAMOS - 15th International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, Samos Island, Greece, IEEE, July 2015, 9 p.

  • 44L. Jiating, C. Killian, S. Le Beux, D. Chillet, H. Li, I. O'Connor, O. Sentieys.

    Channel allocation protocol for reconfigurable Optical Network-on-Chip, in: SiPhotonics: Exploiting Silicon Photonics for energy-efficient high-performance computing (SiPhotonics'15), Amsterdam, Netherlands, January 2015, 7 p.

  • 45S. Kulasekera, A. Madanayake, D. Suarez, R. J. Cintra, F. M. Bayer.

    Multi-beam receiver apertures using multiplierless 8-point approximate DFT, in: IEEE Radar Conference (RadarCon), Arlington, VA, United States, May 2015, pp. 1244-1249. [ DOI : 10.1109/RADAR.2015.7131185 ]

  • 46S. Kulasekera, A. Madanayake, C. Wijenayake, F. M. Bayer, D. Suarez, R. J. Cintra.

    Multi-beam 8×8 RF aperture digital beamformers using multiplierless 2-D FFT approximations, in: IEEE Moratuwa Engineering Research Conference (MERCon), Moratuwa, Sri Lanka, April 2015, pp. 260-264. [ DOI : 10.1109/MERCon.2015.7112356 ]

  • 47X.-C. Le, B. Vrigneau, O. Sentieys.

    l1-norm Minimization Based Algorithm for Non-Intrusive Load Monitoring, in: IEEE International Conference on Pervasive Computing and Communication Workshops (PerCom Workshops), IEEE Workshop on Pervasive Energy Services, St. Louis, United States, March 2015, pp. 299 - 304. [ DOI : 10.1109/PERCOMW.2015.7134052 ]

  • 48J. Métairie, A. Tisserand, E. Casseau.

    Small FPGA based Multiplication-Inversion Unit for Normal Basis Representation in GF(2m), in: ISVLSI: IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, July 2015.

  • 49T. H. Nguyen, M. Gay, L. Bramerie, K. Lenglé, C. Peucheret, O. Sentieys, J.-C. Simon, A. Bazin, R. Raj, F. Raineri.

    Nonlinear phase noise reduction for 20-Gbit/s NRZ-QPSK signals using InP on SOI photonic crystal nanocavity, in: Optical Fiber Communication Conference (OFC 2015), Los Angeles, California, USA, United States, OSA (ISBN: 978-1-55752-937-4), March 2015, vol. Tu2F, Tu2F.3 p. [ DOI : 10.1364/OFC.2015.Tu2F.3 ]

  • 50T. H. Nguyen, M. Joindot, M. Gay, L. Bramerie, J.-C. Simon, P. Scalart, O. Sentieys.

    Carrier frequency offset estimation based on circular harmonic expansion for optical coherent M-QAM communication systems, in: Opto-Electronics and Communications Conference (OECC), Shanghai, China, 2015, pp. 1-3. [ DOI : 10.1109/OECC.2015.7340175 ]

  • 51V.-H. Nguyen, C. Langlais, B. Vrigneau, O. Berder.

    Distributed Minimum Euclidean Distance based Precoding for Wireless Sensor Network, in: International Conference on Computing, Networking and Communications (ICNC), Anaheim, United States, IEEE, February 2015.

  • 52T. H. Nguyen, P. Scalart, M. Joindot, M. Gay, L. Bramerie, C. Peucheret, A. Carer, J.-C. Simon, O. Sentieys.

    Joint Simple Blind IQ Imbalance Compensation and Adaptive Equalization for 16-QAM Optical Communications, in: IEEE International Conference on Communications - ICC, Londres, United Kingdom, IEEE, June 2015, pp. 4913 - 4918. [ DOI : 10.1109/ICC.2015.7249101 ]

  • 53D. Pamula, A. Tisserand.

    Fast and Secure Finite Field Multipliers, in: DSD: Euromicro Conference on Digital System Design, Funchal, Portugal, August 2015. [ DOI : 10.1109/DSD.2015.46 ]

  • 54R. Ragavan, C. Killian, O. Sentieys.

    Low complexity on-chip distributed DC-DC converter for low power WSN nodes, in: NEWCAS 2015 - New Circuits and Systems Conference, Grenoble, France, June 2015, 4 p. [ DOI : 10.1109/NEWCAS.2015.7182118 ]

  • 55M. J. Sepulveda, S. Le Beux, L. Jiating, C. Killian, D. Chillet, I. O’Connor, O. Sentieys.

    Communication Aware Design Method for Optical Network-on-Chip, in: International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC-15, Turin, Italy, Politecnico di Torino, Turin, Italy, September 2015.

  • 56P. Swierczynski, M. Fyrbiak, C. Paar, C. Huriaux, R. Tessier.

    Protecting against Cryptographic Trojans in FPGAs, in: FCCM - 23rd IEEE International Symposium on Field-Programmable Custom Computing Machines, Vancouver, Canada, IEEE, May 2015. [ DOI : 10.1109/FCCM.2015.55 ]

  • 57S. Wang, C. Xiao, W. Liu, E. Casseau, Y. Xiao.

    Selecting Most Profitable Instruction-Set Extensions Using Ant Colony Heuristic, in: Conference on Design and Architectures for Signal and Image Processing, DASIP 2015, Cracow, Poland, September 2015.


National Conferences with Proceedings

  • 58C. B. Basheer Ahmed, S. Pillement, L. Lagadec, A. Tisserand.

    Fast Prototyping of a New Reconfigurable Architecture : Toward Tailored Space FPGA, in: Conférence d’informatique en Parallélisme, Architecture et Système (Compas), Villeneuve d'Ascq, France, June 2015, 10 p.

  • 59D. Chillet, D. MA CHIN, O. Sentieys.

    Gestion des zones en fautes d’une architecture reconfigurable lors du placement des tâches matérielles, in: Gretsi 2015, Lyon, France, September 2015.

  • 60G. Gallin, A. Tisserand, N. Veyrat-Charvillon.

    Comparaison expérimentale d'architectures de crypto-processeurs pour courbes elliptiques et hyper-elliptiques, in: Compas: Conférence d’informatique en Parallélisme, Architecture et Système, Lille, France, June 2015, Prix du meilleur papier de la "track Architecture" de la conférence.

  • 61Y. Oliva, E. Casseau, K. Martin, J.-P. Diguet, T. D. Ngo, Y. Eustache.

    COMPA backend : Runtime dynamique pour l’exécution de programmes flot de données sur plates-formes multiprocesseurs, in: Conférence d’informatique en Parallélisme, Architecture et Système, Lille, France, July 2015.

  • 62J. Proy, N. Veyrat-Charvillon, A. Tisserand, N. Méloni.

    Full Hardware Implementation of Short Addition Chains Recoding for ECC Scalar Multiplication, in: Compas: Conférence d’informatique en Parallélisme, Architecture et Système, Lille, France, June 2015.


Conferences without Proceedings

  • 63F. Berthier, E. Beigne, P. VIVET, O. Sentieys.

    Asynchronous Wake Up Controller for WSN’s Microcontroller: Power Simulation and Specifications, in: 21st IEEE International Symposium on Asynchronous Circuits and Systems, Mountain View, United States, 2015.

  • 64R. Bonamy, S. Bilavarn, F. Muller.

    An Energy-Aware Scheduler for Dynamically Reconfigurable Multi-Core Systems, in: 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2015, Bremen, Germany, June 2015.


Books or Proceedings Editing

  • 65J.-M. Muller, A. Tisserand, J. Villalba Moreno (editors)

    Proceedings of IEEE 22nd Symposium on Computer Arithmetic, IEEE, Lyon, France, June 2015. [ DOI : 10.1109/ARITH.2015.1 ]


Other Publications

  • 66K. Bigou, A. Tisserand.

    RNS Modular Computations for Cryptographic Applications, April 2015, RAIM: 7ème Rencontre Arithmétique de l'Informatique Mathématique, Poster.

  • 67G. Gallin, A. Tisserand, N. Veyrat-Charvillon.

    Experimental Comparison of Crypto-processors Architectures for Elliptic and Hyper-Elliptic Curves Cryptography, June 2015, CryptArchi: 13th International Workshops on Cryptographic Architectures Embedded in Reconfigurable Devices.

  • 68G. Gallin, A. Tisserand, N. Veyrat-Charvillon.

    Hardware and Arithmetic for Hyperelliptic Curves Cryptography, April 2015, RAIM: 7ème Rencontre Arithmétique de l'Informatique Mathématique, Poster.

  • 69K. Martin, J.-P. Diguet, Y. Eustache, T. D. Ngo, E. Casseau, Y. Oliva.

    Compa backend: a Dynamic Runtime for the execution of dataflow programs onto multi-core platforms, September 2015, Conference on Design & Architectures for Signal & Image Processing, Demo Night, Poster.

  • 70O. Sentieys, D. Menard, D. Novo, K. Parashar.

    Fixed-point refinement, a guaranteed approach towards energy efficient computing, March 2015, Tutorial at IEEE/ACM Design Automation and Test in Europe (DATE'15).

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  • 93B. Mei, S. Vernalde, D. Verkest, H. De Man, R. Lauwereins.

    ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix, in: Proc. Int. Conf. on Field Programmable Logic and Applications, Springer, 2003, pp. 61–70.
  • 94D. Menard, D. Chillet, F. Charot, O. Sentieys.

    Automatic Floating-point to Fixed-point Conversion for DSP Code Generation, in: IEEE/ACM Int. Conf. on Compilers, Architectures and Synthesis for Embedded Systems (CASES), Grenoble, October 2002.
  • 95H. Nikolov, M. Thompson, T. Stefanov, A. Pimentel, S. Polstra, R. Bose, C. Zissulescu, E. Deprettere.

    Daedalus: toward composable multimedia MP-SoC design, in: Proc. Design Automation Conference, New York, NY, USA, DAC'08, ACM, 2008, pp. 574–579.

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