EN FR
EN FR


previous Previous | up Home


Bibliography

Major publications by the team in recent years
  • 1C. Berthaud, L. Capelli, J. Gustedt, C. Kirchner, K. Loiseau, A. Magron, M. Medves, A. Monteil, G. Riverieux, L. Romary.

    EPISCIENCES - an overlay publication platform, in: ELPUB2014 - International Conference on Electronic Publishing, Thessalonique, Greece, D. P. Polydoratou (editor), IOS Press, June 2014, pp. 78-87. [ DOI : 10.3233/978-1-61499-409-1-78 ]

    https://hal.inria.fr/hal-01002815
  • 2J. C. Beyler, P. Clauss.

    Performance driven data cache prefetching in a dynamic software optimization system, in: ICS '07: Proceedings of the 21st annual international conference on Supercomputing, New York, NY, USA, ACM, 2007, pp. 202–209.

    http://doi.acm.org/10.1145/1274971.1275000
  • 3J. C. Beyler, M. Klemm, P. Clauss, M. Philippsen.

    A meta-predictor framework for prefetching in object-based DSMs, in: Concurr. Comput. : Pract. Exper., September 2009, vol. 21, pp. 1789–1803.
  • 4P. Clauss, F. J. Fernández, D. Garbervetsky, S. Verdoolaege.

    Symbolic polynomial maximization over convex sets and its application to memory requirement estimation, in: IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Aug 2009, vol. 17, no 8, pp. 983-996.
  • 5P.-N. Clauss, J. Gustedt.

    Iterative Computations with Ordered Read-Write Locks, in: Journal of Parallel and Distributed Computing, 2010, vol. 70, no 5, pp. 496­-504. [ DOI : 10.1016/j.jpdc.2009.09.002 ]

    https://hal.inria.fr/inria-00330024
  • 6A. Ketterlin, P. Clauss.

    Prediction and trace compression of data access addresses through nested loop recognition, in: 6th annual IEEE/ACM international symposium on Code generation and optimization, Boston, USA, ACM, April 2008, pp. 94-103.

    http://dx.doi.org/10.1145/1356058.1356071
  • 7A. Ketterlin, P. Clauss.

    Profiling Data-Dependence to Assist Parallelization: Framework, Scope, and Optimization, in: MICRO-45 – Proceedings of the 2012 IEEE/ACM 45th International Symposium on Microarchitecture, Vancouver, Canada, December 2012.
  • 8B. Pradelle, A. Ketterlin, P. Clauss.

    Polyhedral parallelization of binary code, in: ACM Transactions on Architecture and Code Optimization, January 2012, vol. 8, no 4, pp. 39:1–39:21. [ DOI : 10.1145/2086696.2086718 ]

    http://hal.inria.fr/hal-00664370
  • 9R. Seghir, V. Loechner, B. Meister.

    Integer Affine Transformations of Parametric Z-polytopes and Applications to Loop Nest Optimization, in: ACM Transactions on Architecture and Code Optimization, June 2012, vol. 9, no 2, pp. 8.1-8.27. [ DOI : 10.1145/2207222.2207224 ]

    http://hal.inria.fr/inria-00582388
  • 10S. Verdoolaege, R. Seghir, K. Beyls, V. Loechner, M. Bruynooghe.

    Counting Integer Points in Parametric Polytopes Using Barvinok's Rational Functions, in: Algorithmica, 2007, vol. 48, no 1, pp. 37–66.

    http://dx.doi.org/10.1007/s00453-006-1231-0
Publications of the year

Doctoral Dissertations and Habilitation Theses

  • 11J.-F. Dollinger.

    A framework for efficient execution on GPU and CPU+GPU systems, Université de Strasbourg, July 2015.

    https://hal.inria.fr/tel-01251719
  • 12I. Fassi.

    XFOR (Multifor): A New Programming Structure to Ease the Formulation of Efficient Loop Optimizations, Université de Strasbourg, November 2015.

    https://hal.inria.fr/tel-01251721
  • 13A. Sukumaran-Rajam.

    Beyond the Realm of the Polyhedral Model: Combining Speculative Program Parallelization with Polyhedral Compilation, Université de Strasbourg, November 2015.

    https://hal.inria.fr/tel-01251748

Articles in International Peer-Reviewed Journals

  • 14A. Sukumaran-Rajam, P. Clauss.

    The Polyhedral Model of Nonlinear Loops, in: ACM Transactions on Architecture and Code Optimization, December 2015, vol. 12, no 4. [ DOI : 10.1145/2838734 ]

    https://hal.inria.fr/hal-01244464

International Conferences with Proceedings

  • 15L. Bagnères, O. Zinenko, S. Huot, C. Bastoul.

    Opening Polyhedral Compiler's Black Box, in: CGO 2016 - 14th Annual IEEE/ACM International Symposium on Code Generation and Optimization, Barcelona, Spain, March 2016.

    https://hal.inria.fr/hal-01253322
  • 16C. Bastoul, C. Sabater.

    Automatic Generation of Adaptive Simulation Codes, in: SimRace, Conference on Numerical Methods and High Performance Computing for Industrial Fluid Flows, Rueil-Malmaison, France, IFPEN, December 2015.

    https://hal.inria.fr/hal-01245558
  • 17T. Buchert, L. Nussbaum, J. Gustedt.

    Towards Complete Tracking of Provenance in Experimental Distributed Systems Research, in: REPPAR - Second International Workshop on Reproducibility in Parallel Computing – held together with Euro-Par, Vienna, Austria, August 2015.

    https://hal.inria.fr/hal-01191855
  • 18P. Clauss.

    Mind The Gap! A study of some pitfalls preventing peak performance in polyhedral compilation using a polyhedral antidote, in: IMPACT 2015, Fifth International Workshop on Polyhedral Compilation Techniques, In conjunction with HiPEAC 2015, Amsterdam, Netherlands, January 2015.

    https://hal.inria.fr/hal-01099583
  • 19I. Fassi, P. Clauss.

    XFOR: Filling the Gap between Automatic Loop Optimization and Peak Performance, in: 14th International Symposium on Parallel and Distributed Computing, Limassol, Cyprus, IEEE (editor), June 2015.

    https://hal.inria.fr/hal-01155144
  • 20N. Hallou, E. Rohou, P. Clauss, A. Ketterlin.

    Dynamic Re-Vectorization of Binary Code, in: International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation - SAMOS XV, Agios Konstantinos, Greece, July 2015.

    https://hal.inria.fr/hal-01155207
  • 21O. Zinenko, C. Bastoul, S. Huot.

    Manipulating Visualization, Not Codes, in: International Workshop on Polyhedral Compilation Techniques (IMPACT), Amsterdam, Netherlands, January 2015, 8 p.

    https://hal.inria.fr/hal-01100974

Conferences without Proceedings

  • 22J.-F. Dollinger, V. Loechner.

    CPU+GPU Load Balance Guided by Execution Time Prediction, in: Fifth International Workshop on Polyhedral Compilation Techniques (IMPACT 2015), Amsterdam, Netherlands, January 2015.

    https://hal.inria.fr/hal-01095890
  • 23A. Sukumaran-Rajam, L. E. Campostrini, M. Juan Manuel, P. Clauss.

    Speculative Runtime Parallelization of Loop Nests: Towards Greater Scope and Efficiency, in: 20th International Workshop on High-level Parallel Programming Models and Supportive Environments, held in conjunction with 29th IEEE International Parallel & Distributed Processing Symposium, Hyderabad, India, May 2015.

    https://hal.inria.fr/hal-01155172

Internal Reports

References in notes
  • 28C. Bastoul.

    Code Generation in the Polyhedral Model Is Easier Than You Think, in: PACT'13 IEEE International Conference on Parallel Architecture and Compilation Techniques, Juan-les-Pins, France, 2004, pp. 7–16.

    https://hal.archives-ouvertes.fr/ccsd-00017260
  • 29U. Bondhugula, A. Hartono, J. Ramanujam, P. Sadayappan.

    A practical automatic polyhedral parallelizer and locality optimizer, in: PLDI '08, ACM, 2008, pp. 101–113.
  • 30T. Grosser, J. Ramanujam, L.-N. Pouchet, P. Sadayappan, S. Pop.

    Optimistic Delinearization of Parametrically Sized Arrays, in: Proceedings of the 29th ACM on International Conference on Supercomputing, New York, NY, USA, ICS '15, ACM, 2015, pp. 351–360.

    http://doi.acm.org/10.1145/2751205.2751248
  • 31M. Hall, D. Padua, K. Pingali.

    Compiler research: the next 50 years, in: Commun. ACM, 2009, vol. 52, no 2, pp. 60–67.

    http://doi.acm.org/10.1145/1461928.1461946
  • 32A. Hobor, A. W. Appel, F. Z. Nardelli.

    Oracle Semantics for Concurrent Separation Logic, in: ESOP, 2008, pp. 353-367.
  • 33T. Yuki, P. Feautrier, S. Rajopadhye, V. Saraswat.

    Array Dataflow Analysis for Polyhedral X10 Programs, in: Proceedings of the 18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, New York, NY, USA, PPoPP '13, ACM, 2013, pp. 23–34.

    http://doi.acm.org/10.1145/2442516.2442520


previous Previous | up Home