Section: Dissemination

Teaching - Supervision - Juries

Teaching

• E. Casseau: signal processing, 16h, Enssat (L3)

• E. Casseau: low power design, 6h, Enssat (M1)

• E. Casseau: real time design methodology, 24h, Enssat (M1)

• E. Casseau: computer architecture, 24h, Enssat (M1)

• E. Casseau: SoC and high-level synthesis, 24h, Master by Research (SISEA) and Enssat (M2)

• S. Derrien: component and system synthesis, 20h, Master by Research (istic ) (M2)

• S. Derrien: computer architecture, 12h, ENS Rennes (L3)

• S. Derrien: computer architecture, 24h, istic (L3)

• S. Derrien: introduction to operating systems, 8h, istic (M1)

• S. Derrien: embedded architectures, 48h, istic (M1)

• S. Derrien: high-level synthesis, 6h, istic (M1)

• S. Derrien: software engineering project, 40h, istic (M1)

• F. Charot: processor architecture, 25h, Univ. of Science and Tech. of Hanoi (M1)

• D. Chillet: embedded processor architecture, 20h, Enssat (M1)

• D. Chillet: multimedia processor architectures, 24h, Enssat (M2)

• D. Chillet: low-power digital CMOS circuits, 6h, Telecom Bretagne (M2)

• C. Killian: digital electronics, 62h, iut Lannion (L1)

• C. Killian: signal processing, 36h, iut Lannion (L2)

• C. Killian: automated measurements, 56h, iut Lannion (L2)

• C. Killian: measurement chain, 58h, iut Lannion (L2)

• C. Killian: embedded systems programming, 12h, iut Lannion (L2)

• C. Killian: automatic control, 18h, iut Lannion (L2)

• A. Kritikakou: computer architecture 1, 32h, istic (L3)

• A. Kritikakou: computer architecture 2, 44h, istic (L3)

• A. Kritikakou: C and unix programming languages, 102h, istic (L3)

• A. Kritikakou: operating systems, 96h, istic (L3)

• A. Kritikakou: multitasking operating systems, 20h, ISTIC (M1)

• O. Sentieys: digital signal processing, 40h, Enssat (M1)

• O. Sentieys: VLSI integrated circuit design, 40h, Enssat (M1)

• C. Wolinski: computer architectures, 92h, Esir (L3)

• C. Wolinski: design of embedded systems, 48h, Esir (M1)

• C. Wolinski: signal, image, architecture, 26h, Esir (M1)

• C. Wolinski: programmable architectures, 10h, Esir (M1)

• C. Wolinski: component and system synthesis, 10h, Master by Research (istic ) (M2)

Teaching Responsibilities

• C. Wolinski is the Director of Esir .

• S. Derrien was the responsible of the first year (M1) of the Master of Computer Science at ISTIC until Aug. 2017.

• O. Sentieys is responsible of the ”Embedded Systems” major of the SISEA Master by Research.

• D. Chillet is the responsible of the ICT Master of University of Science and Technology of Hanoi.

• C. Killian is the responsible of the second year of the Physical Measurement DUT at IUT of Lannion.

Enssat stands for ”École Nationale Supérieure des Sciences Appliquées et de Technologie” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Lannion.

istic is the Electrical Engineering and Computer Science Department of the University of Rennes 1.

Esir stands for ”École supérieure d'ingénieur de Rennes” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Rennes.

Supervision

• PhD: Benjamin Barrois, Methods to Evaluate Accuracy-Energy Trade-Off in Operator-Level Approximate Computing, Dec. 2017, O. Sentieys.

• PhD: Gaël Deest, Implementation Trade-Offs for FPGA Accelerators, Dec. 2017, S. Derrien.

• PhD: Xuan Chien Le, Improving performance of non-intrusive load monitoring with low-cost sensor networks, Apr. 2017, O. Sentieys, B. Vrigneau.

• PhD: Rengarajan Ragavan, Error handling and energy estimation for error resilient near-threshold computing, Sep. 2017, O. Sentieys, C. Killian.

• PhD: Baptiste Roux, Methodology and Tools for Energy-aware Task Mapping on Heterogeneous Multiprocessor Architectures, Nov. 2017, O. Sentieys, M. Gautier.

• PhD in progress: Minh Thanh Cong, Hardware Accelerated Simulation of Heterogeneous Multicore Platforms, May 2017, F. Charot, S. Derrien.

• PhD in progress: Petr Dobias, Towards efficient application execution on resilient multi-core architectures, Oct. 2017, E. Casseau.

• PhD in progress: Gabriel Gallin, Hardware Arithmetic Units and Crypto-Processor for Hyperelliptic Curves Cryptography, Oct. 2014, A. Tisserand.

• PhD in progress: Aymen Gammoudi, New Visual Adaptive Real-Time OS for Embedded Multi-Core Architecture, Oct. 2015, D. Chillet, M.Khalgui.

• PhD in progress: Mael Gueguen, Improving the performance and energy efficiency of complex heterogeneous manycore architectures with on-chip data mining, Nov. 2016, O. Sentieys, A. Termier.

• PhD in progress: Van-Phu Ha, Application-Level Tuning of Accuracy, Nov. 2017, T. Yuki, O. Sentieys.

• PhD in progress: Audrey Lucas, Software support resistant to passive and active attacks for asymmetric cryptography on (very) small computation cores, Jan. 2016, A. Tisserand.

• PhD in progress: Jiating, Luo, Communication protocol exploration in the context of 3D integration of multiprocessors interconnected by Optical Network-on-Chip with energy constraints, Nov. 2014, D. Chillet, C. Killian, S. Le-Beux.

• PhD in progress: Thibaut Marty, Compiler support for speculative custom hardware accelerators, Sep. 2017, T. Yuki, O. Sentieys.

• PhD in progress: Genevieve Ndour, Approximate Computing with High Energy Efficiency for Internet of Things Applications, Apr. 2016, A. Tisserand, A. Molnos (CEA LETI).

• PhD in progress: Joel Ortiz Sosa, Study and design of a digital baseband transceiver for wireless network-on-chip architectures, Nov. 2016, O. Sentieys, C. Roland (Lab-STICC).

• PhD in progress: Van Dung Pham, Design space exploration in the context of 3D integration of multiprocessors interconnected by Optical Network-on-Chip, Dec 2014, O. Sentieys, D. Chillet, C. Killian, S. Le-Beux.

• PhD in progress: Rafail Psiakis, A Self-Healing Reconfigurable Accelerator Structure for Fault-Tolerant Multi-Cores, Oct. 2015, A. Kritikakou, O. Sentieys.

• PhD in progress: Simon Rokicki, Hybrid Hardware/Software Dynamic Compilation for Adaptive Embedded Systems, Oct. 2015, S. Derrien.

• PhD in progress: Nicolas Roux, Sensor-aided Non-Intrusive Appliance Load Monitoring: Detecting Activity of Devices through Low-Cost Wireless Sensors, Oct. 2016, O. Sentieys, B. Vrigneau.

• PhD in progress: Mai-Thanh Tran, Hardware Synthesis of Flexible and Reconfigurable Radio from High-Level Language Dedicated to Physical Layer of Wireless Systems, Oct. 2013, E. Casseau, M. Gautier.