Section: New Results

Early Interconnect Contention Analysis

Participants : Amin Oueslati, Julien Deantoni.

In the context of the Atippic project, industrial partners are using the Capella system engineering language (http://polarsys.org/capella) to migrate a satellite control software on a totally new architecture platform based on “COTS” dual core processors. In order to better deal with the potential contention on the interconnect between the different cores, it was required to help for contention analysis. In this context and based on one of our software (GEMOC Studio: http://eclipse.org/gemoc) we developed an executable extension to Capella, from which simulation of Capella model can be used to obtain bus latency and bandwidth.

We are currently extending this simulation approach to ease Design Space Exploration based on variation of some parameters (typically parameters of the tasks that create traffic like for instance, periods or consumed/produced data size). First results have already been demonstrated to the IRT Saint-Exupery and should be published early 2019.