Section: Partnerships and Cooperations

Regional Initiatives

• CPER LECO++: Parallel HPC architectures evolve and the calculation codes are naturally bound to vary over time. Indeed, the architectures change every 2-3 years while the lifespan of a scientific code is much longer (at least 10 years). Knowing how to control the impacts of these changes in order to automatically adapt the digital simulation codes to maintain a high level of performance is a necessity to guarantee a certain sustainability of the developed code. Currently, these variations are manually managed by programmers which require a high level of expertise as well as time.

  A collaboration between the AVALON teams from LIP and BEAGLE from LIRIS on this subject involved one master trainees this year (funding from Federation Informatique de Lyon – PMSISEE project). More specifically, BEAGLE is interested in designing AEVOL a high performance parallel code for simulating the evolution of a population of bacteria. The different parts of the code have been adapted to the hardware characteristics of current architectures (multicore, vector computing, etc.) for which certain operations have several implementations (CPU or vector) or several parallel variants. Designing the assembly of the right versions and choosing the right parameters remains a difficult problem. In this issue, the AVALON team brings its expertise in the development and exploitation of component models, in parallel programming models and in the expertise of executive supports for HPC.

  A PhD thesis between Avalon and Beagle (Laurent Turpin) linked to the CPER LECO++ project (coordinator: T. Gautier, AVALON) has started with the aim of studying the robustness of computer codes on modern parallel architectures and their evolution. Thus, the targeted hardware is that being acquired through the LECO++ project (ARM machine, massively multi-GPU (10)).

  The work of this thesis aims to study the methods and approaches allowing to contribute to a solution to the problems of composition, choice of parameters and efficient execution on a parallel architecture in HPC. The problem addressed in the thesis concerns the portability of the performance of a parallel application for managing code variants and variations at runtime. The solutions that will be studied will be those at the interface between a programming model and its exploitation by executive support. In order to exploit the performance of a class of machines in a portable manner, the candidate will propose the necessary adaptations, whether to the existing component-based programming model (typically Comet) and to executive support (OpenMP type or an executive engine with task base). A major constraint of this work is the performance at execution: the evaluation will be based on an experimental methodology with AEVol as target application. The target hardware is that of an HPC computing node of tomorrow: a multi-core server coupled with a large number of hardware accelerators - GPUs - allowing to have a significant computing density (approximately from 30 to 128 TFlops double precision for 4 to 16 GPUs).