Section: Partnerships and Cooperations

European Initiatives

H2020 Projects

  • Title: PRACE Sixth Implementation Phase (PRACE-6IP) project

  • See also: https://cordis.europa.eu/project/id/823767

  • Duration: May 2019 - December 2021

  • Partners: see https://cordis.europa.eu/project/id/823767

  • Inria contact: Luc Giraud

  • PRACE, the Partnership for Advanced Computing is the permanent pan-European High Performance Computing service providing world-class systems for world-class science. Systems at the highest performance level (Tier-0) are deployed by Germany, France, Italy, Spain and Switzerland, providing researchers with more than 17 billion core hours of compute time. HPC experts from 25 member states enabled users from academia and industry to ascertain leadership and remain competitive in the Global Race. Currently PRACE is finalizing the transition to PRACE 2, the successor of the initial five year period. The objectives of PRACE-6IP are to build on and seamlessly continue the successes of PRACE and start new innovative and collaborative activities proposed by the consortium. These include: assisting the development of PRACE 2; strengthening the internationally recognised PRACE brand; continuing and extend advanced training which so far provided more than 36 400 person·training days; preparing strategies and best practices towards Exascale computing, work on forward-looking SW solutions; coordinating and enhancing the operation of the multi-tier HPC systems and services; and supporting users to exploit massively parallel systems and novel architectures. A high level Service Catalogue is provided. The proven project structure will be used to achieve each of the objectives in 7 dedicated work packages. The activities are designed to increase Europe's research and innovation potential especially through: seamless and efficient Tier-0 services and a pan-European HPC ecosystem including national capabilities; promoting take-up by industry and new communities and special offers to SMEs; assistance to PRACE 2 development; proposing strategies for deployment of leadership systems; collaborating with the ETP4HPC, CoEs and other European and international organisations on future architectures, training, application support and policies. This will be monitored through a set of KPIs.

  • Title: European joint effort toward a highly productive programming environment for heterogeneous exascale computing

  • Program: H2020

  • See also: https://epeec-project.eu

  • Duration: October 2018 - September 2021

  • Coordinator: Barcelona Supercomputing Center

  • Partner: Barcelona Supercomputing Center (Spain)

  • Coordinator: CEA

  • Partners:

    • Fraunhofer–Gesellschaft (Germany)

    • CINECA (Italy)

    • IMEC (Blegium)

    • INESC ID (Portugal)

    • Appentra Solutions (Spain)

    • Eta Scale (Sweden)

    • Uppsala University (Sweden)

    • Inria (France)

    • Cerfacs (France)

  • Inria contact: Stéphane Lanteri

  • EPEEC’s main goal is to develop and deploy a production-ready parallel programming environment that turns upcoming overwhelmingly-heterogeneous exascale supercomputers into manageable platforms for domain application developers. The consortium will significantly advance and integrate existing state-of-the-art components based on European technology (programming models, runtime systems, and tools) with key features enabling 3 overarching objectives: high coding productivity, high performance, and energy awareness. An automatic generator of compiler directives will provide outstanding coding productivity from the very beginning of the application developing/porting process. Developers will be able to leverage either shared memory or distributed-shared memory programming flavours, and code in their preferred language: C, Fortran, or C++. EPEEC will ensure the composability and interoperability of its programming models and runtimes, which will incorporate specific features to handle data-intensive and extreme-data applications. Enhanced leading-edge performance tools will offer integral profiling, performance prediction, and visualisation of traces. Five applications representative of different relevant scientific domains will serve as part of a strong inter-disciplinary co-design approach and as technology demonstrators. EPEEC exploits results from past FET projects that led to the cutting-edge software components it builds upon, and pursues influencing the most relevant parallel programming standardisation bodies.