Moore’s Law is Running Out of Steam

The limits of traditional transistor process technology have been known for a long time. We are now approaching these limits while alternative technologies are still in early stages of development. The economical drive for more performance will persist, and we expect a surge in specialized architectures in the mid-term to squeeze performance out of CMOS technology. Use of Non-Volatile Memory (NVM), Processing-in-Memory (PIM), and various work on approximate computing are all examples of such architectures.

Specialization is the Common Denominator

Specialization, which has been a small niche in the past, is now widespread  63. The main driver today is energy efficiency—small embedded devices need specialized hardware to operate under power/energy constraints. In the next ten years, we expect specializations to become even more common to meet increasing demands for performance. In particular, high-throughput workloads traditionally ran on servers (e.g., computational science and machine learning) will offload (parts of) their computations to accelerators. We are already seeing some instances of such specialization, most notably accelerators for neural networks that use clusters of nodes equipped with FPGAs and/or ASICs.

The Need for Abstractions

The main drawback of hardware specialization is that it comes with significant costs in terms of productivity. Although High-Level Synthesis tools have been steadily improving, design and implementation of custom hardware (HW) are still time consuming tasks that require significant expertise. As specializations become inevitable, we need to provide programmers with tools to develop specialized accelerators and explore their large design spaces. Raising the level of abstraction is a promising way to improve productivity, but also introduces additional challenges to maintain the same levels of performance as manually specified counterparts. Taking advantage of domain knowledge to better automate the design flow from higher level specifications to efficient implementations is necessary for making specialized accelerators accessible.

Language/Programming Model

This is the main interface to the programmer that has two (sometimes conflicting) goals. One is that the programmer should be able to concisely specify the computation. The other is that the domain knowledge of the programmer must also be expressed such that the other layers can utilize it.

Compiler

The compiler is an important component for both productivity and performance. It improves productivity by allowing the input language to be more concise by recovering necessary information through compiler analysis. It is also where the first set of analyses and transformations are performed to realize efficient custom hardware.

Runtime

Runtime complements adjacent layers with its dynamicity. It has access to more concrete information about the input data that static analyses cannot use. It is also responsible for coordinating various processing elements, especially in heterogeneous settings.

Hardware Design

There are many design knobs when building an accelerator: the amount/type of parallelism, communication and on-chip storage, number representation and computer arithmetic, and so on. The key challenge is in navigating through this design space with the help of domain knowledge passed through the preceding layers.

Emerging Technology

Use of non-conventional hardware components (e.g., NVM or optical interconnects) opens further avenues to explore specialized designs. For a domain where such emerging technologies make sense, this knowledge should also be taken into account when designing the HW.

Key Investigators:

E. Casseau, F. Charot, D. Chillet, S. Derrien, A. Kritikakou, P. Quinton, O. Sentieys.

Accelerators are custom hardware that primarily aim to provide high-throughput, energy-efficient, computing platforms. Custom hardware can give much better performance compared to more general architectures simply because they are specialized, at the price of being much harder to “program.” Accelerator designers need to explore a massive design space, which includes many hardware parameters that a software programmer has no control over, to find a suitable design for the application at hand.

Our first objective in this context is to further enlarge the design space and enhance the performance of accelerators. The second, equally important, objective is to provide the designers with the means to efficiently navigate through the ever-expanding design space. Cross-layer expertise is crucial in achieving these goals—we need to fully utilize available domain knowledge to improve both the productivity and the performance of custom hardware design.

Positioning

Hardware acceleration has already proved its efficiency in many datacenter, cloud-computing or embedded high-performance computing (HPC) applications: machine learning, web search, data mining, database access, information security, cryptography, financial, image/signal/video processing, etc. For example, the work at Microsoft in accelerating the Bing web search engine with large-scale reconfigurable fabrics has shown to improve the ranking throughput of each server by 95%  76, and the increasing need for acceleration of deep learning workloads  74.

Hardware accelerators still lack efficient and standardized compilation toolflows, which makes the technology impractical for large-scale use. Generating and optimizing hardware from high-level specifications is a key research area with considerable interest  64, 70. On this topic, we have been pursuing our efforts to propose tools whose design principles are based on a tight coupling between the compiler and the target hardware architectures.

Key Investigators:

S. Filip, S. Derrien, O. Sentieys.

An important design knob in accelerators is the number representation—digital computing is by nature some approximation of real world behavior. Appropriately selecting the number representation that respects a given quality requirement has been a topic of study for many decades in signal/image processing: a process known as Word-Length Optimization (WLO). We are now seeing the scope of number format-centered approximations widen beyond these traditional applications. This gives us many more approximation opportunities to take advantage of, but introduces additional challenges as well.

Earlier work on arithmetic optimizations has primarily focused on low-level representations of the computation (i.e., signal-flow graphs) that do not scale to large applications. Working on higher level abstractions of the computation is a promising approach to improve scalability and to explore high-level transformations that affect accuracy. Moreover, the acceptable degree of approximation is decided by the programmer using domain knowledge, which needs to be efficiently utilized.

Positioning

Traditionally, fixed-point (FxP) arithmetic is used to relax accuracy, providing important benefits in terms of delay, power and area 7. There is also a large body of work on carefully designing efficient arithmetic operators/functions that preserve good numerical properties. Such numerical precision tuning leads to a massive design space, necessitating the development of efficient and automatic exploration methods.

The need for further improvements in energy efficiency has led to renewed interest in approximation techniques in the recent years  71. This field has emerged in the last years, and is very active recently with deep learning as its main driver. Many applications have modest numerical accuracy requirements, allowing for the introduction of approximations in their computations  65.

Key Investigators:

E. Casseau, D. Chillet, C. Killian, A. Kritikakou, O. Sentieys.

With advanced technology nodes and the emergence of new devices pressured by the end of Moore's law, manufacturing problems and process variations strongly influence electrical parameters of circuits and architectures  69, leading to dramatically reduced yield rates  72. Transient errors caused by particles or radiations will also more and more often occur during execution  75, 73, and process variability will prevent predicting chip performance (e.g., frequency, power, leakage) without a self-characterization at run time. On the other hand, many systems are under constant attacks from intruders and security has become of utmost importance.

In this research direction, we will explore techniques to protect architectures against faults, errors, and attacks, which have not only a low overhead in terms of area, performance, and energy 9, 8, 4, but also a significant impact on improving the resilience of the architecture under consideration. Such protections require to act at most layers of the design stack.

Key Investigators:

D. Chillet, S. Derrien, C. Killian, O. Sentieys.

Domain specific accelerators have more exploratory freedom to take advantage of non-conventional technologies that are too specialized for general purpose use. Examples of such technologies include optical interconnects for Network-on-Chip (NoC) and Non-Volatile Memory (NVM) for low-power sensor nodes. The objective of this research direction is to explore the use of such technologies, and find appropriate application domains. The primary cross-layer interaction is expected from Hardware Design to accommodate non-conventional Technologies. However, this research direction may also involve Runtime and Compilers.

5.1.1 Gecos

• Name:
  Generic Compiler Suite
• Keywords:
  Source-to-source compiler, Model-driven software engineering, Retargetable compilation
• Scientific Description:
  The Gecos (Generic Compiler Suite) project is a source-to-source compiler infrastructure targeted at program transformations mainly for High-Level-Synthesis tools. Gecos uses the Eclipse Modeling Framework (EMF) as an underlying infrastructure. Gecos is open-source and is hosted on the Inria gitlab. The Gecos infrastructure is still under very active development and serves as a backbone infrastructure to several research projects of the group.
• Functional Description:
  GeCoS provides a programme transformation toolbox facilitating parallelisation of applications for heterogeneous multiprocessor embedded platforms. In addition to targeting programmable processors, GeCoS can regenerate optimised code for High Level Synthesis tools.
• News of the Year:
  This year, we have proposed a fully automated hardware synthesis flow based on a source-to-source compiler that identifies and explores intricate speculation configurations to generate speculative hardware accelerators 16.
• URL:
  https://­gitlab.­inria.­fr/­gecos
• Publication:
  hal-03714101
• Contact:
  Steven Derrien
• Participants:
  Tomofumi Yuki, Thomas Lefeuvre, Imèn Fassi, Mickael Dardaillon, Ali Hassan El Moussawi, Steven Derrien
• Partner:
  Université de Rennes 1

5.1.2 SmartSense

• Name:
  Sensor-Aided Non-Intrusive Load Monitoring
• Keywords:
  Wireless Sensor Networks, Smart building, Non-Intrusive Appliance Load Monitoring
• Functional Description:
  To measure energy consumption by equipment in a building, NILM techniques (Non-Intrusive Appliance Load Monitoring) are based on observation of overall variations in electrical voltage. This avoids having to deploy watt-meters on every device and thus reduces the cost. SmartSense goes a step further to improve on these techniques by combining sensors (light, temperature, electromagnetic wave, vibration and sound sensors, etc.) to provide additional information on the activity of equipment and people. Low-cost sensors can be energy-autonomous too.
• URL:
  https://­smartsense.­inria.­fr/
• Contact:
  Olivier Sentieys
• Participants:
  Olivier Sentieys, Guillermo Enrique Andrade Barroso, Mickael Le Gentil, Sonia Barrios Pereira

5.1.3 TypEx

• Name:
  Type Exploration Tool
• Keywords:
  Embedded systems, Fixed-point arithmetic, Floating-point, Low power consumption, Energy efficiency, FPGA, ASIC, Accuracy optimization, Automatic floating-point to fixed-point conversion
• Scientific Description:
  The main goal of TypEx is to explore the design space spanned by possible number formats in the context of High-Level Synthesis. TypEx takes a C code written using floating-point datatypes specifying the application to be explored. The tool also takes as inputs a cost model as well as some user constraints and generates a C code where the floating-point datatypes are replaced by the wordlengths found after exploration. The best set of wordlengths is the one found by the tool that respects the accuracy constraint given and that minimizes a parametrized cost function.
• Functional Description:
  TypEx is a tool designed to automatically determine custom number representations and word-lengths (i.e., bit-width) for FPGAs and ASIC designs at the C source level. TypEx is available open-source at https://gitlab.inria.fr/gecos/gecos-float2fix. See README.md for detailed instructions on how to install the software.
• URL:
  https://­gitlab.­inria.­fr/­gecos/­gecos-float2fix
• Contact:
  Olivier Sentieys
• Participants:
  Olivier Sentieys, Van Phu Ha, Tomofumi Yuki, Ali Hassan El Moussawi

5.2.1 MPTorch: a PyTorch-based framework for simulating custom precision DNN training

Participants: Silviu-Ioan Filip, Paul Estano.

Keywords: Computer architecture, Arithmetic, Custom Floating-point, Deep learning, Multiple-Precision

Scientific description: MPTorch is a wrapper framework built atop PyTorch that is designed to simulate the use of custom/mixed precision arithmetic in PyTorch, especially for DNN training.

Functional description: MPTorch reimplements the underlying computations of commonly used layers for CNNs (e.g. matrix multiplication and 2D convolutions) using user-specified floating-point formats for each operation (e.g. addition, multiplication). All the operations are internally done using IEEE-754 32-bit floating-point arithmetic, with the results rounded to the specified format.

• Contact: Silviu-Ioan Filip
• URL: https://github.com/mptorch/mptorch

5.2.2 E-methodHW: an automatic tool for the evaluation of polynomial and rational function approximations

Participants: Silviu-Ioan Filip, Matei Istoan.

Keywords: function approximation, FPGA hardware implementation generator

Scientific description: E-methodHW is an open source C/C++ prototype tool written to exemplify what kind of numerical function approximations can be developed using a digit recurrence evaluation scheme for polynomials and rational functions.

Functional description: E-methodHW provides a complete design flow from choice of mathematical function operator up to optimised VHDL code that can be readily deployed on an FPGA. The use of the E-method allows the user great flexibility if targeting high throughput applications.

• Contact: Silviu-Ioan Filip
• Partners: Univ Rennes, Imperial College London
• URL: https://github.com/sfilip/emethod

5.2.3 Firopt: a tool for the simultaneous design of digital FIR filters along with the dedicated hardware model

Participants: Silviu-Ioan Filip, Martin Kumm, Anastasia Volkova.

Keywords: FIR filter design, multiplierless hardware implementation generator

Scientific description: the firopt tool is an open source C++ prototype that produces Finite Impulse Response (FIR) filters that have minimal cost in terms of digital adders needed to implement them. This project aims at fusing the filter design problem from a frequency domain specification with the design of the dedicated hardware architecture. The optimality of the results is ensured by solving appropriate mixed integer linear programming (MILP) models developed for the project. It produces results that are generally more efficient than those of other methods found in the literature or from commercial tools (such as MATLAB).

• Contact: Silviu-Ioan Filip
• Partners: Univ Rennes, Université de Nantes, Fulda University of Applied Sciences
• URL: https://gitlab.com/filteropt/firopt

5.2.4 Hybrid-DBT

Participants: Simon Rokicki, Louis Savary, Steven Derrien.

Keywords: Dynamic Binary Translation, hardware acceleration, VLIW processor, RISC-V

Scientific description: Hybrid-DBT is a hardware/software Dynamic Binary Translation (DBT) framework capable of translating RISC-V binaries into VLIW binaries. Since the DBT overhead has to be as small as possible, our implementation takes advantage of hardware acceleration for performance critical stages (binary translation, dependency analysis and instruction scheduling) of the flow. Thanks to hardware acceleration, our implementation is two orders of magnitude faster than a pure software implementation and enables an overall performance increase of 23% on average, compared to a native RISC-V execution.

• Contact: Simon Rokicki
• Partners: Univ Rennes
• URL: https://github.com/srokicki/HybridDBT

5.2.5 Comet

Participants: Simon Rokicki, Olivier Sentieys, Joseph Paturel.

Keywords: Processor core, RISC-V instruction-set architecture

Scientific description: Comet is a RISC-V pipelined processor with data/instruction caches, fully developed using High-Level Synthesis. The behavior of the core is defined in a small C++ code which is then fed into a HLS tool to generate the RTL representation. Thanks to this design flow, the C++ description can be used as a fast and cycle-accurate simulator, which behaves exactly like the final hardware. Moreover, modifications in the core can be done easily at the C++ level.

• Contact: Simon Rokicki
• Partners: Univ Rennes
• URL: https://gitlab.inria.fr/srokicki/Comet

8.1.1 Inria Associate Team

8.1.2 Inria International Partners

8.2.1 Visits of international scientists

Louis Narmour from Colorado State University (CSU), USA, is visiting TARAN from Jan. 2022 for two years, in the context of his international jointly supervised PhD (or ’cotutelle’ in French) between CSU and Univ. Rennes.

Jinyi Xu, PhD Student from East China Normal University, China, is visiting TARAN from Nov. 2020 for two years.

8.2.2 Visits to international teams

Corentin Ferry is visiting Colorado State University (CSU) since Sep. 2021 for two years, in the context of his international jointly supervised PhD (or ’cotutelle’ in French) between CSU and Univ. Rennes.

8.3.1 ANR AdequateDL

Participants: Olivier Sentieys, Silviu-Ioan Filip.

• Program: ANR PRC
• Project acronym: AdequateDL
• Project title: Approximating Deep Learning Accelerators
• Duration: Jan. 2019 - Dec. 2023
• Coordinator: TARAN
• Other partners: INL, LIRMM, CEA-LIST

The design and implementation of convolutional neural networks for deep learning is currently receiving a lot of attention from both industrials and academics. However, the computational workload involved with CNNs is often out of reach for low power embedded devices and is still very costly when run on datacenters. By relaxing the need for fully precise operations, approximate computing substantially improves performance and energy efficiency. Deep learning is very relevant in this context, since playing with the accuracy to reach adequate computations will significantly enhance performance, while keeping quality of results in a user-constrained range. AdequateDL will explore how approximations can improve performance and energy efficiency of hardware accelerators in deep-learning applications. Outcomes include a framework for accuracy exploration and the demonstration of order-of-magnitude gains in performance and energy efficiency of the proposed adequate accelerators with regards to conventional CPU/GPU computing platforms.

8.3.2 ANR RAKES

Participants: Olivier Sentieys, Cédric Killian, Abhijit Das.

• Program: ANR PRC
• Project acronym: RAKES
• Project title: Radio Killed an Electronic Star: speed-up parallel programming with broadcast communications based on hybrid wireless/wired network on chip
• Duration: June 2019 - June 2023
• Coordinator: TIMA
• Other partners: TIMA, TARAN, Lab-STICC

The efficient exploitation by software developers of multi/many-core architectures is tricky, especially when the specificities of the machine are visible to the application software. To limit the dependencies to the architecture, the generally accepted vision of the parallelism assumes a coherent shared memory and a few, either point to point or collective, synchronization primitives. However, because of the difference of speed between the processors and the main memory, fast and small dedicated hardware controlled memories containing copies of parts of the main memory (a.k.a caches) are used. Keeping these distributed copies up-to-date and synchronizing the accesses to shared data, requires to distribute and share information between some if not all the nodes. By nature, radio communications provide broadcast capabilities at negligible latency, they have thus the potential to disseminate information very quickly at the scale of a circuit and thus to be an opening for solving these issues. In the RAKES project, we intend to study how wireless communications can solve the scalability of the abovementioned problems, by using mixed wired/wireless Network on Chip. We plan to study several alternatives and to provide (a) a virtual platform for evaluation of the solutions and (b) an actual implementation of the solutions.

8.3.3 ANR Opticall2

Participants: Olivier Sentieys, Cédric Killian, Daniel Chillet.

• Program: ANR PRCE
• Project acronym: Opticall2
• Project title: on-chip OPTIcal interconnect for ALL to ALL communications
• Duration: Dec. 2018 - June. 2023
• Coordinator: INL
• Other partners: INL, TARAN, C2N, CEA-LETI, Kalray

The aim of Opticall2 is to design broadcast-enabled optical communication links in manycore architectures at wavelengths around 1.3um. We aim to fabricate an optical broadcast link for which the optical power is equally shared by all the destinations using design techniques (different diode absorption lengths, trade-off depending on the current point in the circuit and the insertion losses). No optical switches will be used, which will allow the link latency to be minimized and will lead to deterministic communication times, which are both key features for efficient cache coherence protocols. The second main objective of Opticall2 is to propose and design a new broadcast-aware cache coherence communication protocol allowing hundreds of computing clusters and memories to be interconnected, which is well adapted to the broadcast-enabled optical communication links. We expect better performance for the parallel execution of benchmark programs, and lower overall power consumption, specifically that due to invalidation or update messages.

8.3.4 ANR SHNOC

Participants: Cédric Killian, Daniel Chillet, Olivier Sentieys, Emmanuel Casseau, Ibrahim Krayem.

• Program: ANR JCJC (young researcher)
• Project acronym: SHNOC
• Project title: Scalable Hybrid Network-on-Chip
• Duration: Feb. 2019 - Apr. 2024
• P.I.: C. Killian, TARAN

The goal of the SHNoC project is to tackle one of the manycore interconnect issues (scalability in terms of energy consumption and latency provided by the communication medium) by mixing emerging technologies. Technology evolution has allowed for the integration of silicon photonics and wireless on-chip communications, creating Optical and Wireless NoCs (ONoCs and WNoCs, respectively) paradigms. The recent publications highlight advantages and drawbacks for each technology: WNoCs are efficient for broadcast, ONoCs have low latency and high integrated density (throughput/sqcm) but are inefficient in multicast, while ENoCs are still the most efficient solution for small/average NoC size. The first contribution of this project is to propose a fast exploration methodology based on analytical models of the hybrid NoC instead of using time consuming manycore simulators. This will allow exploration to determine the number of antennas for the WNoC, the amount of embedded lasers sources for the ONoC and the routers architecture for the ENoC. The second main contribution is to provide quality of service of communication by determining, at run-time, the best path among the three NoCs with respect to a target, e.g. minimizing the latency or energy. We expect to demonstrate that the three technologies are more efficient when jointly used and combined, with respect to traffic characteristics between cores and quality of service targeted.

8.3.5 ANR FASY

Participants: Angeliki Kritikakou, Marcello Traiola, Olivier Sentieys.

• Program: ANR JCJC (young researcher)
• Project acronym: FASY
• Project title: FAult-aware timing behaviour for safety-critical multicore SYstems
• Duration: Jan. 2022 - Dec. 2025
• P.I.: K. Kritikakou, TARAN

The safety-critical embedded industries, such as avionics, automobile, robotics and health-care, require guarantees for hard real-time, correct application execution, and architectures with multiple processing elements. While multicore architectures can meet the demands of best-effort systems, the same cannot be stated for critical systems, due to hard-to-predict timing behaviour and susceptibility to reliability threats. Existing approaches design systems to deal with the impact of faults regarding functional behaviors. FASY extends the SoA by answering the two-fold challenge of time-predictable and reliable multicore systems through functional and timing analysis of applications behaviour, fault-aware WCET estimation and design of cores with time-predictable execution, under faults.

8.3.6 ANR Re-Trusting

Participants: Olivier Sentieys, Angeliki Kritikakou, Marcello Traiola, Silviu-Ioan Filip.

• Program: ANR PRC
• Project acronym: Re-Trusting
• Project title: REliable hardware for TRUSTworthy artificial INtelliGence
• Duration: Oct. 2021 - Sep. 2025
• Coordinator: INL
• Other partners: LIP6, TARAN, THALES

To be able to run Artificial Intelligence (AI) algorithms efficiently, customized hardware platforms for AI (HW-AI) are required. Reliability of hardware becomes mandatory for achieving trustworthy AI in safety-critical and mission-critical applications, such as robotics, smart healthcare, and autonomous driving. The RE-TRUSTING project develops fault models and performs failure analysis of HW-AIs to study their vulnerability with the goal of “explaining” HW-AI. Explaining HW-AI means ensuring that the hardware is error-free and that the AI hardware does not compromise the AI prediction accuracy and does not bias AI decision-making. In this regard, the project aims at providing confidence and trust in decision-making based on AI by explaining the hardware wherein AI algorithms are being executed.

8.3.7 DGA/INRIA Sniffer

Participants: Olivier Sentieys.

• Program: DGA/INRIA joint call on AI
• Project acronym: Sniffer
• Project title: Non-intrusive monitoring of mains operated equipment
• Duration: Feb. 2020 - Mar. 2022
• Partners: TARAN, DGA-MI

Based on the SmartSense platform and on high-frequency traces of the power consumption of individual electrical appliances and building-level power monitoring, the aim of Sniffer is the detection and surveillance of equipment connected to the mains supply.

8.3.8 Labex CominLabs - LeanAI (2021-2024)

Participants: Silviu-Ioan Filip (PI), Olivier Sentieys, Steven Derrien.

9.1.1 Scientific events: organisation

9.1.2 Scientific events: selection

9.1.3 Journal

9.1.4 Invited talks

• O. Sentieys gave an invited keynote at the Inria Scientific Days on ”Opportunities for computer architecture research with open-source hardware: The case for RISC-V“.
• D.Chillet gave a talk at RITS'22 (Recherche en Imagerie et Technologies pour la Santé), ”Carrière des Enseignants-Chercheurs”.
• A. Kritikakou gave an invited talk on ”Energy-Quality-Time Optimized Mapping for Imprecise Computation Tasks on Multicores” at a common thematic day on optimization methods organized by GDR RO and SOC2.
• M. Traiola gave an invited talk on “Approximate Computing in Hardware: Challenges and Opportunities for Test and Reliability” at the Winter French school on Design Technologies for Heterogeneous Embedded Systems (FETCH) 2022.

9.1.5 Leadership within the scientific community

• D.Chillet is a member of the French National University Council in Signal Processing and Electronics (CNU - Conseil National des Universites, 61ème section) since 2019.
• D. Chillet is member of the Board of Directors of Gretsi Association.
• D. Chillet is co-animator of the "Connected Systems for Transitions" topic of GDR SoC${}^2$.
• F. Charot and O. Sentieys are members of the steering committee of a CNRS Spring School for graduate students on embedded systems architectures and associated design tools (ARCHI).
• O. Sentieys is a member of the steering committee of GDR SoC${}^2$.
• O. Sentieys is an elected member of the Evaluation Committee (CE) of Inria.
• A. Kritikakou is a member of the French National University Council in Computer Science (CNU - Conseil National des Universites, 27ème section) since 2022.
• A. Kritikakou is co-animator of the "High performance embedded computing" topic of GDR SoC${}^2$.

9.1.6 Scientific expertise

• O. Sentieys was a member of the ANR Scientific Evaluation Committee CE25 "Software science and engineering - Multi-purpose communication networks, high-performance infrastructure".
• D. Chillet is a member of the HCERES Evaluation Committee for Master Programs of Université Nice Côte d'Azur.
• A. Kritikakou is a member of the Examination Committee of Industrial Engineering Sciences and Computer Engineering (SII) Aggrégation

9.1.7 Research administration

• S. Derrien is the head of the D3 "Computer Architecture" Department of IRISA Lab.

9.2.1 Teaching Responsibilities

• E. Casseau is in charge of the Department of “Digital Systems” at ENSSAT Engineering Graduate School.
• D. Chillet is associate director of studies at ENSSAT Engineering Graduate School.
• D. Chillet is the responsible of the ”Embedded Systems” major of the SISEA Master by Research.
• C. Killian is the responsible of the second year of the ”Instrumentation” BUT at IUT, Lannion.
• S. Rokicki is the responsible of the second year in the computer science department of ENS Rennes

9.2.2 Teaching

• E. Casseau: programmable logic, 20h, Enssat (L3)
• E. Casseau: low power design, 8h, Enssat (M1)
• E. Casseau: real time design methodology, 54h, Enssat (M1)
• E. Casseau: computer architecture, 24h, Enssat (M1)
• E. Casseau: VHDL design, 42h, Enssat (M1)
• E. Casseau: SoC and high-level synthesis, 24h, Master by Research (SISEA) and Enssat (M2)
• S. Derrien, optimizing and parallelising compilers, 14h, Master of Computer Science, istic(M2)
• S. Derrien, advanced processor architectures, 8h, Master of Computer Science, istic(M2)
• S. Derrien, high level synthesis, 20h, Master of Computer Science, istic(M2)
• S. Derrien: introduction to operating systems, 8h, istic (M1)
• S. Derrien, principles of digital design, 20h, Bachelor of EE/CS, istic(L2)
• S. Derrien, computer architecture, 48h, Bachelor of Computer Science, istic(L3)
• S.I. Filip, Operating Systems, 24h, Master of Mechatronics, ENS Rennes (M2)
• F. Charot: computer architecture, 48h, Esir (L3)
• F. Charot: software hardware interfaces, 44h, istic (L3)
• F. Charot: Compilation and code optimization architecture, 18h, Enssat (M2)
• D. Chillet: embedded processor architecture, 20h, Enssat (M1)
• D. Chillet: multimedia processor architectures, 24h, Enssat (M2)
• D. Chillet: advanced processor architectures, 20h, Enssat (M2)
• D. Chillet: micro-controller, 32h, Enssat (L3)
• D. Chillet: low-power digital CMOS circuits, 4h, UBO (M2)
• C. Killian: digital electronics, 75h, iut Lannion (L1)
• C. Killian: automated measurements, 52.5h, iut Lannion (L2)
• C. Killian: computer architecture, 6h, iut Lannion (L3)
• C. Killian: embedded systems, 22.5h, iut Lannion (L2)
• C. Killian: microcontrollers, 44h, iut Lannion (L2)
• C. Killian: data acquisition and signal processing, 21h, UFAZ (L3)
• A. Kritikakou: principles of computer design, 32h, istic (L3)
• A. Kritikakou: software hardware interfaces, 12h, istic (L3)
• A. Kritikakou: C and unix programming languages, 76h, istic (L3)
• A. Kritikakou: operating systems, 48h, istic (L3)
• O. Sentieys: VLSI integrated circuit design, 24h, Enssat (M1)
• O. Sentieys: VHDL and logic synthesis, 18h, Enssat (M1)
• S. Rokicki: C Programming, 24h, ENS Rennes

9.2.3 PhD Supervision

• PhD: Davide Pala, Microarchitectures for Robust and Efficent Incremental Backup in Intermittently Powered Systems, Nov. 2022, O. Sentieys, I. Miro-Panades (CEA LETI).
• PhD: Minyu Cui, Energy-Quality-Time Fault Tolerant Task Mapping on Multicore Architectures, Jun. 2022, E. Casseau, A. Kritikakou.
• PhD: Jaechul Lee, Approximate communication techniques exploration for efficient nano-photonics interconnects, Dec. 2022, D. Chillet, C. Killian.
• PhD: Thibaut Marty, Timing speculation for hardware accelerators, March 2022, S. Derrien.
• PhD in progress: Thibault Allenet, Low-Cost Neural Network Algorithms and Implementations for Temporal Sequence Processing, March 2019, O. Sentieys, O. Bichler (CEA LIST).
• PhD in progress: Hamza Amara, Detection and countermeasures for DoS attack in Noc-based SoC using machine learning, Oct. 2022, E. Casseau, D. Chillet, C. Killian.
• PhD in progress: Herinomena Andrianatrehina, Ensuring confidentiality in modern Out-of-Order cores, Nov 2022, S. Rokicki, R. Lashermes.
• PhD in progress: Gaetan Barret, Predictive model of energy consumption of cloud-native applications, Nov. 2022, D. Chillet.
• PhD in progress: Sami Ben Ali, Efficient Low-Precision Training for Deep Learning Accelerators, Jan. 2022, O. Sentieys.
• PhD in progress: Benoit Coqueret, Physical Security Attacks Against Artificial Intelligence Based Algorithms, Nov. 2022, O. Sentieys, M. Carbone (Thales), G. Zaid (Thales).
• PhD in progress: Minh Thanh Cong, Hardware Accelerated Simulation of Heterogeneous Multicore Platforms, May 2017, F. Charot, S. Derrien.
• PhD in progress: Léo De La Fuente, In-Memory Computing for Ultra Low Power Architectures, Nov. 2021, O. Sentieys, J.-F. Christmann (CEA LETI).
• PhD in progress: Paul Estano, Dynamic Precision Training of Deep Neural Network Models on the Edge, Feb. 2022, S. Filip, E. Riccietti (ENS Lyon), S. Derrien.
• PhD in progress: Corentin Ferry, Compiler support for Runtime data compression for FPGA accelerators, Sep. 2019, S. Derrien, T. Yuki and S. Rajopadhye (co-tutelle between Univ Rennes and Colorado State University).
• PhD in progress: Cédric Gernigon, Highly compressed/quantized neural networks for FPGA on-board processing in Earth observation by satellite, Oct. 2020, O. Sentieys, S. Filip.
• PhD in progress: Jean-Michel Gorius, Speculative Software Pipeline for Micro-Architecture Synthesis, Oct. 2021, S. Derrien, S. Rokicki.
• PhD in progress: Wilfread Guilleme, Fault Tolerant Hardware Architectures for Artificial Intelligence, Oct. 2022, D. Chillet, C. Killian, A.Kritikakou.
• PhD in progress: Van-Phu Ha, Application-Level Tuning of Accuracy, Nov. 2017, O. Sentieys.
• PhD in progress: Ibrahim Krayem, Fault tolerant emerging on-chip interconnects for manycore architectures, Oct. 2020, C. Killian, D. Chillet.
• PhD in progress: Seungah Lee, Efficient Designs of On-Board Heterogeneous Embedded Systems for Space Applications, Nov. 2021, A. Kritikakou, E. Casseau, R. Salvador (Centrale-Supelec), O. Sentieys.
• PhD in progress: Guillaume Lomet, Guess What I'm Learning: Side-Channel Analysis of Edge AI Training Accelerators, Oct. 2022, C. Killian, R. Salvador, O. Sentieys
• PhD in progress: Amélie Marotta, Emp-error: EMFI-Resilient RISC-V Processor, Oct. 2021, O. Sentieys, R. Lashermes (LHS), Rachid Dafali (DGA).
• PhD in progress: Louis Narmour, Revisiting memory allocation in the polyhedral model, Sep. 2019, S. Derrien, T. Yuki and S. Rajopadhye (co-tutelle between Université de Rennes 1 and Colorado State University).
• PhD in progrees: Romaric (Pegdwende) Nikiema, Time-guaranteed and reliable execution for real-time multicore architectures, Oct. 2022, A. Kritikakou, M. Traiola
• PhD in progress: Leo Pradels, Constrained optimization of FPGA accelerators for embedded deep convolutional neural networks, Dec. 2020, D. Chillet, O. Sentieys, S. Filip.
• PhD in progress: Baptiste Rossigneux, Adapting sparsity to hardware in neural networks, Nov. 2022, E. Casseau, I. Kucher(CEA), V. Lorrain (CEA).
• PhD in progress: Louis Savary, Security of DBT-based processors, Sept 2022, S. Rokicki, S. Derrien.

International journals

• 11 articleM.Mario Barbareschi, S.Salvatore Barone, A.Alberto Bosio, J.Jie Han and M.Marcello Traiola. A Genetic-algorithm-based Approach to the Design of DCT Hardware Accelerators.ACM Journal on Emerging Technologies in Computing Systems183July 2022, 1-25
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• 12 articleM.Minyu Cui, A.Angeliki Kritikakou, L.Lei Mo and E.Emmanuel Casseau. Energy-Efficient Partial-Duplication Task Mapping under multiple DVFS schemes.International Journal of Parallel Programming502April 2022, 267-294
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• 13 articleM.Minyu Cui, A.Angeliki Kritikakou, L.Lei Mo and E.Emmanuel Casseau. Near-Optimal Energy-Efficient Partial-Duplication Task Mapping of Real-Time Parallel Applications.Journal of Systems Architecture134January 2023, 102790
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• 14 articleF.Fernando Fernandes dos Santos, A.Angeliki Kritikakou, J.Josie Esteban Rodriguez Condia, J.Juan David Guerrero Balaguera, M.Matteo Sonza Reorda, O.Olivier Sentieys and P.Paolo Rech. Characterizing a Neutron-Induced Fault Model for Deep Neural Networks.IEEE Transactions on Nuclear ScienceNovember 2022
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• 15 articleC.Corentin Ferry, T.Tomofumi Yuki, S.Steven Derrien and S.Sanjay Rajopadhye. Increasing FPGA Accelerators Memory Bandwidth with a Burst-Friendly Memory Layout.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2023, 1-1
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• 16 articleJ.-M.Jean-Michel Gorius, S.Simon Rokicki and S.Steven Derrien. SpecHLS: Speculative Accelerator Design using High-Level Synthesis.IEEE Micro2022, 1-10
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• 17 articleM.Martin Kumm, A.Anastasia Volkova and S.-I.Silviu-Ioan Filip. Design of Optimal Multiplierless FIR Filters with Minimal Number of Adders.IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsMay 2022
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• 18 articleJ.Jaechul Lee, C.Cédric Killian, S.Sebastien Le Beux and D.Daniel Chillet. Distance-aware Approximate Nanophotonic Interconnect.ACM Transactions on Design Automation of Electronic Systems272March 2022, 1-30
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• 19 articleX.Xinmei Li, L.Lei Mo, A.Angeliki Kritikakou and O.Olivier Sentieys. Approximation-aware Task Deployment on Heterogeneous Multi-core Platforms with DVFS.IEEE Transactions on Computer-Aided Design of Integrated Circuits and SystemsNovember 2022, 1-15
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• 20 articleR.Rafail Psiakis, A.Angeliki Kritikakou and O.Olivier Sentieys. Dynamic fault-tolerant VLIW processor with heterogeneous Function Units.Microprocessors and Microsystems: Embedded Hardware Design 93May 2022, 104564
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• 21 articleJ.Josie Rodriguez Condia, P.Paolo Rech, F.Fernando Fernandes dos Santos, L.Luigi Carro and M.Matteo Sonza Reorda. An Effective Method to Identify Microarchitectural Vulnerabilities in GPUs.IEEE Transactions on Device and Materials ReliabilityMarch 2022, 1-14
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• 22 articleA.Annachiara Ruospo, E.Ernesto Sanchez, L.Lucas Matana Luza, L.Luigi Dilillo, M.Marcello Traiola and A.Alberto Bosio. A Survey on Deep Learning Resilience Assessment Methodologies.Computer2022
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International peer-reviewed conferences

• 23 inproceedingsT.Thibault Allenet, D.David Briand, O.Olivier Bichler and O.Olivier Sentieys. Disentangled Loss for Low-Bit Quantization-Aware Training.CVPR 2022 - IEEE / CVF Computer Vision and Pattern Recognition ConferenceProceedings of the IEEE/CVF Conference on Computer Vision and Pattern Recognition (CVPR) WorkshopsNew Orleans, United States2022, 2788-2792
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• 24 inproceedingsM.Mario Barbareschi, A.Alberto Bosio, I.Ian O'Connor, P.Petr Fiser and M.Marcello Traiola. A Design Space Exploration Framework for Memristor-Based Crossbar Architecture.DDECS 2022 - 25th International Symposium on Design and Diagnostics of Electronic Circuits and SystemsPrague, Czech RepublicIEEEApril 2022, 38-43
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• 25 inproceedingsN.Nicolas Bellec, G.Guillaume Hiet, S.Simon Rokicki, F.Frédéric Tronel and I.Isabelle Puaut. RT-DFI: Optimizing Data-Flow Integrity for Real-Time Systems.ECRTS 2022 - 34th Euromicro Conference on Real-Time Systems34Modène, ItalyJune 2022, 1-24
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• 26 inproceedingsA.Alberto Bosio, M.Moreno Bragaglio, S.Samuele Germiniani, S.Samuele Mori, G.Graziano Pravadelli and M.Marcello Traiola. Assertion-aware approximate computing design exploration on behavioral models.LATS 2022 - IEEE 23rd Latin American Test SymposiumMontevideo, UruguayIEEESeptember 2022, 1-6
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• 27 inproceedingsA.Alberto Bosio, S.Samuele Germiniani, G.Graziano Pravadelli and M.Marcello Traiola. Exploiting assertions mining and fault analysis to guide RTL-level approximation.DATE 2023 – 26th IEEE/ACM Design, Automation and Test in EuropeAntwerp, BelgiumApril 2023
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• 28 inproceedingsM.Minyu Cui, A.Angeliki Kritikakou, L.Lei Mo and E.Emmanuel Casseau. Near-optimal Energy-Efficient Partial-Duplication Mapping of Real-Time Parallel Applications.AEiC 2022 - 26th Ada-Europe International Conference on Reliable Software TechnologiesGhent, BelgiumJune 2022, 1-26
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• 29 inproceedingsN.Nikolaos Deligiannis, R.Riccardo Cantoro, M. S.Matteo Sonza Reorda, M.Marcello Traiola and E.Emanuele Valea. Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms.DSN-S 2022 - 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks - Supplemental VolumeBaltimore, United StatesIEEEJune 2022, 23-24
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• 30 inproceedingsF.Fernando Fernandes dos Santos, A.Angeliki Kritikakou and O.Olivier Sentieys. Experimental evaluation of neutron-induced errors on a multicore RISC-V platform.IOLTS 2022 - 28th IEEE International Symposium on OnLine Testing and Robust System DesignTorino, ItalyIEEESeptember 2022, 1-7
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• 31 inproceedingsF.Fernando Fernandes dos Santos and P.Paolo Rech. Performance-Reliability Trade-Off in Graphics Processing Units.RADiation Effects on Components and Systems (RADECS)Venice, ItalyOctober 2022
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• 32 inproceedingsJ.-M.Jean-Michel Gorius, S.Simon Rokicki and S.Steven Derrien. Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis.2022 International Conference on Field-Programmable Technology (ICFPT)FPT 2022 - International Conference on Field Programmable TechnologyHonk Kong / Hybrid, Hong Kong SAR ChinaIEEE2022, 1-6
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• 33 inproceedingsV.-P.Van-Phu Ha and O.Olivier Sentieys. Maximizing Computing Accuracy on Resource-Constrained Architectures.DATE 2023 - 26th IEEE/ACM Design, Automation and Test in EuropeAntwerp, BelgiumApril 2023
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• 34 inproceedingsI.Ibrahim Krayem, R.Romain Mercier, C.Cédric Killian, A.Angeliki Kritikakou and D.Daniel Chillet. Data and Fault Aware Routing Algorithm for NoC Based Approximate Computing.NANOARCH 2022 - 17th ACM International Symposium on Nanoscale ArchitecturesVirtual, FranceACMDecember 2022, 1-6
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• 35 inproceedingsA.Angeliki Kritikakou, P.Panagiota Nikolaou, I.Ivan Rodriguez-Ferrandez, J.Joseph Paturel, L.Leonidas Kosmidis, M. K.Maria K. Michael, O.Olivier Sentieys and D.David Steenari. Functional and Timing Implications of Transient Faults in Critical Systems.IOLTS 2022 – 28th IEEE International Symposium on OnLine Testing and Robust System DesignTorino, ItalyIEEESeptember 2022, 1-10
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• 36 inproceedingsA.Angeliki Kritikakou, O.Olivier Sentieys, G.Guillaume Hubert, Y.Youri Helen, J.-F.Jean-Francois Coulon and P.Patrice Deroux-Dauphin. FLODAM: Cross-Layer Reliability Analysis Flow for Complex Hardware Designs.DATE 2022 - 25th IEEE/ACM Design, Automation and Test in EuropeAntwerp, BelgiumIEEEMarch 2022, 1-6
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• 37 inproceedingsR.Romain Mercier, C.Cédric Killian, A.Angeliki Kritikakou, Y.Youri Helen and D.Daniel Chillet. Tolerating Errors in NoC: A Lightweight Region-Based Fault-Mitigation Method.SELSE 2022 - IEEE Workshop on Silicon Errors in Logic – System Effects[Virtual], FranceIEEEMay 2022, 1-7
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• 38 inproceedingsL.Lei Mo, Q.Qi Zhou, A.Angeliki Kritikakou and J.Ji Liu. Energy Efficient, Real-time and Reliable Task Deployment on NoC-based Multicores with DVFS.DATE 2022 - IEEE/ACM Design, Automation and Test in EuropeAntwerp, BelgiumIEEEMarch 2022, 1-6
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• 39 inproceedingsV. L.Van Long Nguyen Huu, J.Julien Lallet, E.Emmanuel Casseau and L.Laurent d'Orazio. Cache management in MASCARA-FPGA: from coalescing heuristic to replacement policy.DaMoN 2022 - 18th International Workshop on Data Management on New HardwarePhiladelphia, United StatesACMJune 2022, 1-5
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• 40 inproceedingsA.Ali Piri, S.Sepide Saeedi, M.Mario Barbareschi, B.Bastien Deveautour, S. D.Stefano Di Carlo, I.Ian O'Connor, A.Alessandro Savino, M.Marcello Traiola and A.Alberto Bosio. Input-Aware Approximate Computing.AQTR 2022 - IEEE International Conference on Automation, Quality and Testing, RoboticsCluj-Napoca, RomaniaIEEEMay 2022, 1-6
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• 41 inproceedingsM.Manju Rajan, A.Abhijit Das and J.John Jose. LOKI: A Hardware Trojan Affecting Multiple Components of an SoC.2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)Paphos, CyprusJuly 2022
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• 42 inproceedingsA.Annachiara Ruospo, G.Gabriele Gavarini, I.Ilaria Bragaglia, M.Marcello Traiola, A.Alberto Bosio and E.Ernesto Sanchez. Selective Hardening of Critical Neurons in Deep Neural Networks.DDECS 2022 - 25th International Symposium on Design and Diagnostics of Electronic Circuits and SystemsPrague, Czech RepublicIEEEApril 2022, 136-141
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• 43 inproceedingsF. F.Fernando Fernandes dos Santos, P.Paolo Rech, A.Angeliki Kritikakou and O.Olivier Sentieys. Evaluating the Impact of Mixed-Precision on Fault Propagation for Deep Neural Networks on GPUs.ISVLSI 2022 - IEEE Computer Society Annual Symposium on VLSINicosia, ItalyIEEEJuly 2022, 327-327
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• 44 inproceedingsM.Mariko Tatsumi, S.-I.Silviu-Ioan Filip, C.Caroline White, O.Olivier Sentieys and G.Guy Lemieux. Mixing Low-Precision Formats in Multiply-Accumulate Units for DNN Training.FPT 2022 - IEEE International Conference on Field Programmable TechnologyHong Kong, Hong Kong SAR ChinaIEEEDecember 2022, 1-9
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• 45 inproceedingsM.Marcello Traiola, A.Angeliki Kritikakou and O.Olivier Sentieys. harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of Deep Neural Networks.DATE 2023 – 26th IEEE/ACM Design, Automation and Test in EuropeAntwerp, BelgiumApril 2023
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• 46 inproceedingsP.Parya Zolfaghari, J.Joel Ortiz, C.Cédric Killian and S.Sébastien Le Beux. Non-Volatile Phase Change Material based Nanophotonic Interconnect.DATE 2022 - IEEE/ACM Design, Automation and Test in EuropeIEEE/ACM Design, Automation and Test in Europe (DATE) 2022Antwerp, BelgiumIEEEDecember 2021, 1-6
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National peer-reviewed Conferences

• 47 inproceedingsR.Romain Mercier, C.Cédric Killian, A.Angeliki Kritikakou, Y.Youri Helen and D.Daniel Chillet. Atténuation des Défauts dans les Réseaux sur Puce avec une Approche de Brassage de Bits Basée sur des Régions.GRETSI 2022 - XXVIIIème Colloque Francophone de Traitement du Signal et des ImagesNancy, FranceSeptember 2022, 1-4
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Conferences without proceedings

• 48 inproceedingsF.Fernando Fernandes dos Santos, A.Angeliki Kritikakou, O.Olivier Sentieys and P.Paolo Rech. Characterizing Deep Neural Networks Neutrons-Induced Error Model.NSREC 2022 - IEEE Nuclear & Space Radiation Effects ConferenceProvo, United StatesIEEEJuly 2022, 1-5
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Scientific books

• 49 bookA.Alberto Bosio, D.Daniel Menard and O.Olivier Sentieys. Approximate Computing Techniques: From Component- to Application-Level.Springer2022
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Scientific book chapters

• 50 inbookA.Alberto Bosio, S.Stefano Di Carlo, P.Patrick Girard, A.Annachiara Ruospo, E.Ernesto Sanchez, A.Alessandro Savino, L.Lukas Sekanina, M.Marcello Traiola, Z.Zdeněk Vašíček and A.Arnaud Virazel. Design, Verification, Test, and In-Field Implications of Approximate Digital Integrated Circuits.Approximate Computing TechniquesSpringer International PublishingJanuary 2022, 349-385
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• 51 inbookE.Etienne Dupuis, S.-I.Silviu-Ioan Filip, O.Olivier Sentieys, D.David Novo, I.Ian O'Connor and A.Alberto Bosio. Approximations in Deep Learning.Approximate Computing Techniques - From Component- to Application-Level2022, 467-512
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• 52 inbookO.Olivier Sentieys and D.Daniel Menard. Customizing Number Representation and Precision.Approximate Computing Techniques - From Component- to Application-LevelSpringer2022
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• 53 inbookM.Marcello Traiola, B.Bastien Deveautour, A.Alberto Bosio, P.Patrick Girard and A.Arnaud Virazel. Test and Reliability of Approximate Hardware.Approximate ComputingSpringer International PublishingMarch 2022, 233-266
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Doctoral dissertations and habilitation theses

• 54 thesisM.Minyu Cui. Energy-Quality-Time Fault Tolerant Task Mapping on Multicore Architectures.École normale supérieure de RennesJune 2022
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• 55 thesisC.Cédric Killian. Energy efficiency, fault tolerance, and emerging on-chip interconnects for manycore architectures.Université de Rennes 1 (UR1)June 2022
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• 56 thesisA.Angeliki Kritikakou. Real-time and reliable design for safety-critical embedded systems.Rennes 1November 2022
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• 57 thesisJ.Jaechul Lee. Approximate communication techniques exploration for efficient nano-photonics interconnects.Université Rennes 1December 2022
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• 58 thesisT.Thibaut Marty. Temporal Speculation for hardware accelerators.Université de Rennes 1March 2022
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• 59 thesisD.Davide Pala. Microarchitectures for Robust and Efficient Incremental Backup in Intermittently-Powered Systems.Université de Rennes 1November 2022
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Reports & preprints

• 60 miscN.Niccolò Cavagnero, F.Fernando Fernandes dos Santos, M.Marco Ciccone, G.Giuseppe Averta, T.Tatiana Tommasi and P.Paolo Rech. Fault-Aware Design and Training to Enhance DNNs Reliability with Zero-Overhead.June 2022
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Other scientific publications

• 61 inproceedingsF.Fernando Fernandes, A.Angeliki Kritikakou and O.Olivier Sentieys. Experimental evaluation of neutron-induced errors on a RISC-V processor.RISC-V Week 2022Paris, FranceMay 2022
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• 62 inproceedingsS.Simon Rokicki, J.Joseph Paturel and O.Olivier Sentieys. Comet: a RISC-V Core Synthesized from C++ Specifications.Spring 2022 RISC-V WeekParis, FranceMay 2022
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