Moore’s Law is Running Out of Steam

: The limits of traditional transistor process technology have been known for a long time. We are now approaching these limits while alternative technologies are still in early stages of development. The economical drive for more performance will persist, and we expect a surge in specialized architectures in the mid-term to squeeze performance out of CMOS technology. Use of Non-Volatile Memory (NVM), Processing-in-Memory (PIM), and various work on approximate computing are all examples of such architectures.

Specialization is the Common Denominator

: Specialization, which has been a small niche in the past, is now widespread 78. The main driver today is energy efficiency—small embedded devices need specialized hardware to operate under power/energy constraints. In the next ten years, we expect specializations to become even more common to meet increasing demands for performance. In particular, high-throughput workloads traditionally run on servers (e.g., computational science and machine learning) will offload (parts of) their computations to accelerators. We are already seeing some instances of such specialization, most notably accelerators for neural networks that use clusters of nodes equipped with FPGAs and/or ASICs.

The Need for Abstractions

: The main drawback of hardware specialization is that it comes with significant costs in terms of productivity. Although High-Level Synthesis tools have been steadily improving, design and implementation of custom hardware (HW) are still time consuming tasks that require significant expertise. As specializations become inevitable, we need to provide programmers with tools to develop specialized accelerators and explore their large design spaces. Raising the level of abstraction is a promising way to improve productivity, but also introduces additional challenges to maintain the same levels of performance as manually specified counterparts. Taking advantage of domain knowledge to better automate the design flow from higher level specifications to efficient implementations is necessary for making specialized accelerators accessible.

Language/Programming Model

: This is the main interface to the programmer that has two (sometimes conflicting) goals. One is that the programmer should be able to concisely specify the computation. The other is that the domain knowledge of the programmer must also be expressed such that the other layers can utilize it.

Compiler

: The compiler is an important component for both productivity and performance. It improves productivity by allowing the input language to be more concise by recovering necessary information through compiler analysis. It is also where the first set of analyses and transformations are performed to realize efficient custom hardware.

Runtime

: Runtime complements adjacent layers with its dynamicity. It has access to more concrete information about the input data that static analyses cannot use. It is also responsible for coordinating various processing elements, especially in heterogeneous settings.

Hardware Design

: There are many design knobs when building an accelerator: the amount/type of parallelism, communication and on-chip storage, number representation and computer arithmetic, and so on. The key challenge is in navigating through this design space with the help of domain knowledge passed through the preceding layers.

Emerging Technology

: Use of non-conventional hardware components (e.g., NVM or optical interconnects) opens further avenues to explore specialized designs. For a domain where such emerging technologies make sense, this knowledge should also be taken into account when designing the HW.

Key Investigators:

E. Casseau, F. Charot, D. Chillet, S. Derrien, A. Kritikakou, B. Le Gal, P. Quinton, S. Rokicki, O. Sentieys.

Accelerators are custom hardware that primarily aim to provide high-throughput, energy-efficient, computing platforms. Custom hardware can give much better performance compared to more general architectures simply because they are specialized, at the price of being much harder to “program.” Accelerator designers need to explore a massive design space, which includes many hardware parameters that a software programmer has no control over, to find a suitable design for the application at hand.

Our first objective in this context is to further enlarge the design space and enhance the performance of accelerators. The second, equally important, objective is to provide the designers with the means to efficiently navigate through the ever-expanding design space. Cross-layer expertise is crucial in achieving these goals—we need to fully utilize available domain knowledge to improve both the productivity and the performance of custom hardware design.

Positioning:

Hardware acceleration has already proved its efficiency in many datacenter, cloud-computing or embedded high-performance computing (HPC) applications: machine learning, web search, data mining, database access, information security, cryptography, financial, image/signal/video processing, etc. For example, the work at Microsoft in accelerating the Bing web search engine with large-scale reconfigurable fabrics has shown to improve the ranking throughput of each server by 95% 88, and the increasing need for acceleration of deep learning workloads 91.

Hardware accelerators still lack efficient and standardized compilation toolflows, which makes the technology impractical for large-scale use. Generating and optimizing hardware from high-level specifications is a key research area with considerable interest 79, 86. On this topic, we have been pursuing our efforts to propose tools whose design principles are based on a tight coupling between the compiler and the target hardware architectures.

Key Investigators:

S. Filip, S. Derrien, O. Sentieys, M. Traiola.

An important design knob in accelerators is the number representation—digital computing is by nature some approximation of real world behavior. Appropriately selecting the number representation that respects a given quality requirement has been a topic of study for many decades in signal/image processing: a process known as Word-Length Optimization (WLO). We are now seeing the scope of number format-centered approximations widen beyond these traditional applications. This gives us many more approximation opportunities to take advantage of, but introduces additional challenges as well.

Earlier work on arithmetic optimizations has primarily focused on low-level representations of the computation (i.e., signal-flow graphs) that do not scale to large applications. Working on higher level abstractions of the computation is a promising approach to improve scalability and to explore high-level transformations that affect accuracy. Moreover, the acceptable degree of approximation is decided by the programmer using domain knowledge, which needs to be efficiently utilized.

Positioning:

Traditionally, fixed-point (FxP) arithmetic is used to relax accuracy, providing important benefits in terms of delay, power and area 15. There is also a large body of work on carefully designing efficient arithmetic operators/functions that preserve good numerical properties. Such numerical precision tuning leads to a massive design space, necessitating the development of efficient and automatic exploration methods.

The need for further improvements in energy efficiency has led to renewed interest in approximation techniques in the recent years 87. This field has emerged in the last years, and is very active recently with deep learning as its main driver. Many applications have modest numerical accuracy requirements, allowing for the introduction of approximations in their computations 80.

Key Investigators:

E. Casseau, D. Chillet, F. Fernandes dos Santos, A. Kritikakou, O. Sentieys, M. Traiola.

With advanced technology nodes and the emergence of new devices pressured by the end of Moore's law, manufacturing problems and process variations strongly influence electrical parameters of circuits and architectures 85, leading to dramatically reduced yield rates 89. Transient errors caused by particles or radiations will also more and more often occur during execution 92, 90, and process variability will prevent predicting chip performance (e.g., frequency, power, leakage) without a self-characterization at run time. On the other hand, many systems are under constant attacks from intruders and security has become of utmost importance.

In this research direction, we will explore techniques to protect architectures against faults, errors, and attacks, which have not only a low overhead in terms of area, performance, and energy 17, 16, 12, but also a significant impact on improving the resilience of the architecture under consideration. Such protections require to act at most layers of the design stack.

Key Investigators:

D. Chillet, S. Derrien, O. Sentieys, M. Traiola.

Domain specific accelerators have more exploratory freedom to take advantage of non-conventional technologies that are too specialized for general purpose use. Examples of such technologies include optical interconnects for Network-on-Chip (NoC) and Non-Volatile Memory (NVM) for low-power sensor nodes. The objective of this research direction is to explore the use of such technologies, and find appropriate application domains. The primary cross-layer interaction is expected from Hardware Design to accommodate non-conventional Technologies. However, this research direction may also involve Runtime and Compilers.

6.1.1 Gecos

• Name:
  Generic Compiler Suite
• Keywords:
  Source-to-source compiler, Model-driven software engineering, Retargetable compilation
• Scientific Description:
  The Gecos (Generic Compiler Suite) project is a source-to-source compiler infrastructure targeted at program transformations mainly for High-Level-Synthesis tools. Gecos uses the Eclipse Modeling Framework (EMF) as an underlying infrastructure. Gecos is open-source and is hosted on the Inria gitlab. The Gecos infrastructure is still under very active development and serves as a backbone infrastructure to several research projects of the group.
• Functional Description:
  GeCoS provides a programme transformation toolbox facilitating parallelisation of applications for heterogeneous multiprocessor embedded platforms. In addition to targeting programmable processors, GeCoS can regenerate optimised code for High Level Synthesis tools.
• News of the Year:
  With the recent work on the Speculative HLS project and the new ANR LOTR, we have extended the tool to integrate some new analysis and transformation based on the Circt project (https://circt.llvm.org). We are also moving toward generating verilog for a subset of input C code. The objective is to be able to generate hardware with a fully open-source toolchain.
• URL:
  https://­gitlab.­inria.­fr/­gecos
• Publication:
  hal-03714101
• Contact:
  Steven Derrien
• Participants:
  Simon Rokicki, Dylan Leothaud, Jean-Michel Gorius, Steven Derrien
• Partner:
  Université de Rennes 1

6.1.2 SmartSense

• Name:
  Sensor-Aided Non-Intrusive Load Monitoring
• Keywords:
  Wireless Sensor Networks, Smart building, Non-Intrusive Appliance Load Monitoring
• Functional Description:
  To measure energy consumption by equipment in a building, NILM techniques (Non-Intrusive Appliance Load Monitoring) are based on observation of overall variations in electrical voltage. This avoids having to deploy watt-meters on every device and thus reduces the cost. SmartSense goes a step further to improve on these techniques by combining sensors (light, temperature, electromagnetic wave, vibration and sound sensors, etc.) to provide additional information on the activity of equipment and people. Low-cost sensors can be energy-autonomous too.
• URL:
  https://­smartsense.­inria.­fr/
• Contact:
  Olivier Sentieys
• Participants:
  Olivier Sentieys, Guillermo Enrique Andrade Barroso, Mickael Le Gentil, Sonia Barrios Pereira

6.1.3 TypEx

• Name:
  Type Exploration Tool
• Keywords:
  Embedded systems, Fixed-point arithmetic, Floating-point, Low power consumption, Energy efficiency, FPGA, ASIC, Accuracy optimization, Automatic floating-point to fixed-point conversion
• Scientific Description:
  The main goal of TypEx is to explore the design space spanned by possible number formats in the context of High-Level Synthesis. TypEx takes a C code written using floating-point datatypes specifying the application to be explored. The tool also takes as inputs a cost model as well as some user constraints and generates a C code where the floating-point datatypes are replaced by the wordlengths found after exploration. The best set of wordlengths is the one found by the tool that respects the accuracy constraint given and that minimizes a parametrized cost function.
• Functional Description:
  TypEx is a tool designed to automatically determine custom number representations and word-lengths (i.e., bit-width) for FPGAs and ASIC designs at the C source level. TypEx is available open-source at https://gitlab.inria.fr/gecos/gecos-float2fix. See README.md for detailed instructions on how to install the software.
• URL:
  https://­gitlab.­inria.­fr/­gecos/­gecos-float2fix
• Contact:
  Olivier Sentieys
• Participants:
  Olivier Sentieys, Van Phu Ha, Tomofumi Yuki, Ali Hassan El Moussawi

6.2.1 MPTorch: a PyTorch-based framework for simulating custom precision DNN training

Participants: Silviu-Ioan Filip.

Keywords: Computer architecture, Arithmetic, Custom Floating-point, Deep learning, Multiple-Precision

Scientific description: MPTorch is a wrapper framework built atop PyTorch that is designed to simulate the use of custom/mixed precision arithmetic in PyTorch, especially for DNN training.

Functional description: MPTorch reimplements the underlying computations of commonly used layers for CNNs (e.g. matrix multiplication and 2D convolutions) using user-specified floating-point formats for each operation (e.g. addition, multiplication). All the operations are internally done using IEEE-754 32-bit floating-point arithmetic, with the results rounded to the specified format.

• Contact: Silviu-Ioan Filip
• URL: MPTorch on github

6.2.2 rminimax: a tool for designing machine-efficient rational approximations of mathematical functions

Participants: Silviu-Ioan Filip.

Keywords: Computer Arithmetic, Function Approximation, Rational and Polynomial Functions, Mathematical Libraries

Scientific description: rminimax is a C++ library for designing $L^{\infty }$-based rational approximations of mathematical function, with both real and machine-representable coefficients (such as IEEE-754 floating-point formats). The output of the tool is intended for use inside custom mathematical function accelerators (both hardware and software-based), for instance in an FPGA context or for mathematical libraries like the libm of the C language.

• Contact: Silviu-Ioan Filip
• Partners: Univ Rennes
• URL: rminimax on gitlab

6.2.3 Hybrid-DBT

Participants: Simon Rokicki, Louis Savary, Steven Derrien.

Keywords: Dynamic Binary Translation, hardware acceleration, VLIW processor, RISC-V

Scientific description: Hybrid-DBT is a hardware/software Dynamic Binary Translation (DBT) framework capable of translating RISC-V binaries into VLIW binaries. Since the DBT overhead has to be as small as possible, our implementation takes advantage of hardware acceleration for performance critical stages (binary translation, dependency analysis and instruction scheduling) of the flow. Thanks to hardware acceleration, our implementation is two orders of magnitude faster than a pure software implementation and enables an overall performance increase of 23% on average, compared to a native RISC-V execution.

• Contact: Simon Rokicki
• Partners: Univ Rennes
• URL: HybridDBT on github

6.2.4 Comet

Participants: Simon Rokicki, Olivier Sentieys, Joseph Paturel.

Keywords: Processor core, RISC-V instruction-set architecture

Scientific description: Comet is a RISC-V pipelined processor with data/instruction caches, fully developed using High-Level Synthesis. The behavior of the core is defined in a small C++ code which is then fed into a HLS tool to generate the RTL representation. Thanks to this design flow, the C++ description can be used as a fast and cycle-accurate simulator, which behaves exactly like the final hardware. Moreover, modifications in the core can be done easily at the C++ level.

Comet is still in active development. Our roadmap includes 64-bit version, Linux compatible, support for vector ISA extension, out-of-order superscalar microarchitecture. Comet is used in many ongoing research projects (PEPR Arsene, Cyberpros, Foch, CocoRISCo Inria Challenge, EuroHPC DARE (Digital Autonomy with RISC-V in Europe)) and is used as support to several PhD theses.

• Contact: Simon Rokicki
• Partners: Univ Rennes
• URL: Comet on gitlab

6.2.5 MMAlpha

Participants: Patrice Quinton.

Keywords: High-level synthesis, polyhedral model

Scientific description:MMAlpha is a software for the high-level synthesis of parallel architectures from high-level specifications written using the Alpha language. Developed over years, it is currently able to generate automatically synthesizable Vhdl programs for various examples. MMAlpha was recently used to generate Vhdl code for the simulation of electrical circuits.

• Contact: Patrice Quinton
• Partners: Univ Rennes
• URL: none

9.1.1 Inria associate team

9.1.2 Participation in other International Programs

9.3.1 Horizon Europe

9.3.2 Other european programs/initiatives

9.4.1 ANR RAKES

Participants: Olivier Sentieys, Cédric Killian, Abhijit Das.

• Program: ANR PRC
• Project acronym: RAKES
• Project title: Radio Killed an Electronic Star: speed-up parallel programming with broadcast communications based on hybrid wireless/wired network on chip
• Duration: June 2019 - June 2024
• Coordinator: TIMA
• Other partners: TIMA, TARAN, Lab-STICC

The efficient exploitation by software developers of multi/many-core architectures is tricky, especially when the specificities of the machine are visible to the application software. To limit the dependencies to the architecture, the generally accepted vision of the parallelism assumes a coherent shared memory and a few, either point to point or collective, synchronization primitives. However, because of the difference of speed between the processors and the main memory, fast and small dedicated hardware controlled memories containing copies of parts of the main memory (a.k.a caches) are used. Keeping these distributed copies up-to-date and synchronizing the accesses to shared data, requires to distribute and share information between some if not all the nodes. By nature, radio communications provide broadcast capabilities at negligible latency, they have thus the potential to disseminate information very quickly at the scale of a circuit and thus to be an opening for solving these issues. In the RAKES project, we intend to study how wireless communications can solve the scalability of the abovementioned problems, by using mixed wired/wireless Network on Chip. We plan to study several alternatives and to provide (a) a virtual platform for evaluation of the solutions and (b) an actual implementation of the solutions.

9.4.2 ANR Opticall2

Participants: Olivier Sentieys, Cédric Killian, Daniel Chillet.

• Program: ANR PRCE
• Project acronym: Opticall2
• Project title: on-chip OPTIcal interconnect for ALL to ALL communications
• Duration: Dec. 2018 - May 2024
• Coordinator: INL
• Other partners: INL, TARAN, C2N, CEA-LETI, Kalray

The aim of Opticall2 is to design broadcast-enabled optical communication links in manycore architectures at wavelengths around 1.3um. We aim to fabricate an optical broadcast link for which the optical power is equally shared by all the destinations using design techniques (different diode absorption lengths, trade-off depending on the current point in the circuit and the insertion losses). No optical switches will be used, which will allow the link latency to be minimized and will lead to deterministic communication times, which are both key features for efficient cache coherence protocols. The second main objective of Opticall2 is to propose and design a new broadcast-aware cache coherence communication protocol allowing hundreds of computing clusters and memories to be interconnected, which is well adapted to the broadcast-enabled optical communication links. We expect better performance for the parallel execution of benchmark programs, and lower overall power consumption, specifically that due to invalidation or update messages.

9.4.3 ANR SHNOC

Participants: Cédric Killian, Daniel Chillet, Olivier Sentieys, Emmanuel Casseau, Ibrahim Krayem.

• Program: ANR JCJC (young researcher)
• Project acronym: SHNOC
• Project title: Scalable Hybrid Network-on-Chip
• Duration: Feb. 2019 - Apr. 2024
• P.I.: C. Killian, TARAN

The goal of the SHNoC project is to tackle one of the manycore interconnect issues (scalability in terms of energy consumption and latency provided by the communication medium) by mixing emerging technologies. Technology evolution has allowed for the integration of silicon photonics and wireless on-chip communications, creating Optical and Wireless NoCs (ONoCs and WNoCs, respectively) paradigms. The recent publications highlight advantages and drawbacks for each technology: WNoCs are efficient for broadcast, ONoCs have low latency and high integrated density (throughput/sqcm) but are inefficient in multicast, while ENoCs are still the most efficient solution for small/average NoC size. The first contribution of this project is to propose a fast exploration methodology based on analytical models of the hybrid NoC instead of using time consuming manycore simulators. This will allow exploration to determine the number of antennas for the WNoC, the amount of embedded lasers sources for the ONoC and the routers architecture for the ENoC. The second main contribution is to provide quality of service of communication by determining, at run-time, the best path among the three NoCs with respect to a target, e.g. minimizing the latency or energy. We expect to demonstrate that the three technologies are more efficient when jointly used and combined, with respect to traffic characteristics between cores and quality of service targeted.

9.4.4 ANR FASY

Participants: Angeliki Kritikakou, Marcello Traiola, Olivier Sentieys.

• Program: ANR JCJC (young researcher)
• Project acronym: FASY
• Project title: FAult-aware timing behaviour for safety-critical multicore SYstems
• Duration: Jan. 2022 - Dec. 2025
• P.I.: K. Kritikakou, TARAN

The safety-critical embedded industries, such as avionics, automobile, robotics and health-care, require guarantees for hard real-time, correct application execution, and architectures with multiple processing elements. While multicore architectures can meet the demands of best-effort systems, the same cannot be stated for critical systems, due to hard-to-predict timing behaviour and susceptibility to reliability threats. Existing approaches design systems to deal with the impact of faults regarding functional behaviors. FASY extends the SoA by answering the two-fold challenge of time-predictable and reliable multicore systems through functional and timing analysis of applications behaviour, fault-aware WCET estimation and design of cores with time-predictable execution, under faults.

9.4.5 ANR Re-Trusting

Participants: Olivier Sentieys, Angeliki Kritikakou, Marcello Traiola, Silviu-Ioan Filip.

• Program: ANR PRC
• Project acronym: Re-Trusting
• Project title: REliable hardware for TRUSTworthy artificial INtelliGence
• Duration: Oct. 2021 - Sep. 2025
• Coordinator: INL
• Other partners: LIP6, TARAN, THALES

To be able to run Artificial Intelligence (AI) algorithms efficiently, customized hardware platforms for AI (HW-AI) are required. Reliability of hardware becomes mandatory for achieving trustworthy AI in safety-critical and mission-critical applications, such as robotics, smart healthcare, and autonomous driving. The RE-TRUSTING project develops fault models and performs failure analysis of HW-AIs to study their vulnerability with the goal of “explaining” HW-AI. Explaining HW-AI means ensuring that the hardware is error-free and that the AI hardware does not compromise the AI prediction accuracy and does not bias AI decision-making. In this regard, the project aims at providing confidence and trust in decision-making based on AI by explaining the hardware wherein AI algorithms are being executed.

9.4.6 Labex CominLabs - LeanAI (2021-2024)

Participants: Silviu-Ioan Filip (PI), Olivier Sentieys, Steven Derrien.

Recent developments in deep learning (DL) are putting a lot of pressure on and pushing the demand for intelligent edge devices capable of on-site learning. The realization of such systems is, however, a massive challenge due to the limited resources available in an embedded context and the massive training costs for state-of-the-art deep neural networks. In order to realize the full potential of deep learning, it is imperative to improve existing network training methodologies and the hardware being used. LeanAI will attack these problems at the arithmetic and algorithmic levels and explore the design of new mixed numerical precision hardware architectures that are at the same time more energy-efficient and offer increased performance in a resource-restricted environment. The expected outcome of the project includes new mixed-precision algorithms for neural network training, together with open-source tools for hardware and software training acceleration at the arithmetic level on edge devices. Partners: TARAN, LS2N/OGRE, INRIA-LIP/DANTE.

9.4.7 ANR LOTR

Participants: Steven Derrien, Simon Rokicki.

• Program: ANR PRC
• Project acronym: LOTR
• Project title: Lord Of The RISCs
• Duration: Oct. 2023 - Sep. 2027
• Coordinator: Steven Derrien
• Other partners: CEA, TARAN, PACAP

Lord Of The RISCs (LOTR) is a novel flow for designing highly customized RISC-V processor microarchitectures for embedded and IoT platforms. The LOTR flow operates on a description of the processor Instruction Set Architecture (ISA). It can automatically infer synthesizable Register Transfer Level (RTL) descriptions of a large number of microarchitecture variants with different performance/cost trade-offs. In addition, the flow integrates two domain-specific toolboxes dedicated to the support of timing predictability (for safety-critical systems) and security (through hardware protection mechanisms).

9.4.8 CYBERPROS

Participants: Olivier Sentieys.

• Program: BPI France
• Project title: Fault Injection Emulator for Cyberattacks and System Security Evaluation processeurs
• Duration: Oct. 2023 - Sep. 2026
• Coordinator: Patrice Deroux-Dauphin
• Other partners: TEMENTO, IROC

The objective of the CYBERPROS project is to be able to predict the behavior of a circuit subjected to to cyberattacks by fault injection. The research work consists of developing a active attack emulator and associated simulation tools. A hardened processor core will be developed as a test vehicle. Test results will be digitized for editing of learning algorithms underlying the creation of a database and tools for predictive behavior.

9.4.9 PEPR ARSENE

Participants: Louis Savary, Herinomena Andrianatrehina, Simon Rokicki, Steven Derrien, Ronan Lashermes, Olivier Sentieys.

• Program: PEPR Cyber
• Project title: Secure architectures for embedded digital systems
• Duration: Jul. 2022 - Jun. 2028
• Coordinator: CEA
• Other partners: CEA, PACAP, TARAN, LHC, Lab-STICC, LIRMM, Verimag, TIMA, LCIS, EMSE, Telecom Paris

The main objectives of the ARSENE project are to allow the French community to make significant advances in the field to strengthen the community’s expertise and visibility on the international stage. Taran's contribution is on the study and implementation of two families of RISC-V processors: 32-bit RISC-V for low power secure circuits against physical attacks for IoT applications and 64-bit RISC-V secure circuits against micro-architectural attacks.

9.4.10 ANR RADYAL

Participants: Marcello Traiola, Olivier Sentieys.

• Program: ANR PRC
• Project acronym: RADYAL
• Project title: Resource-Aware DYnamically Adaptable machine Learning
• Duration: Oct 2023 – Apr 2027
• Coordinator: Stefan Duffner, LIRIS, Lyon
• Other partners: TARAN, LIRIS, CTRL-A (Inria Grenoble), GIPSA-LAB

Nowadays, for many applications, the performance requirements of a DNN model deployed on a given hardware platform are not static but evolving dynamically as its operating conditions and environment change. RADYAL studies original interdisciplinary approaches that allow DNN models to be dynamically configurable at run-time on a given reconfigurable hardware accelerator architecture, depending on the external environment, following an approach based on feedback loops and control theory.

9.4.11 ANR SEC-V

Participants: Bertrand Le Gal.

• Program: ANR PRCE
• Project acronym: SEC-V
• Project title: open-source, secure and high-performance processor core based on the RISC-V ISA
• Duration: Oct 2021 – Apr 2025
• Coordinator: Sebastien Pillement, IETR, Nantes
• Other partners: TARAN, LS2N, THALES TRT, THALES INVIA

In recent years, attacks exploiting optimization mechanisms have appeared. Exploiting, for example, flaws in cache memories, performance counters or speculation units, they call into question the safety and security of processors and the industrial systems that use them. SEC-V studies original interdisciplinary approaches that rely on RISC-V open-hardware architectures and CISC paradigm to prodive runtime flexibility and adaptability. The originality of the approach lies in the integration of a dynamic code transformation unit covering 4 of the 5 NIST functions of cybersecurity, notably via monitoring (identify, detect), obfuscation (protect), and dynamic adaptation (react). This dynamic management paves the way for on-line optimizations to improve the security and safety of the microarchitecture, without reworking either the software or the chip architecture.

9.4.12 PEPR HOLIGRAIL

Participants: Nesrine Sfar, Rémi Garcia, Mehdi El Arar, Silviu Filip, Olivier Sentieys.

• Program: PEPR IA
• Project acronym: HOLIGRAIL
• Project title: HOLIistic approaches to GReener model Archi-tectures for Inference and Learning
• Duration: Oct 2023 – Dec 2029
• Coordinator: Olivier Sentieys, Taran
• Other partners: CEA List, INSA Lyon, Inria Corse, Grenoble-INP

Accelerators of artificial intelligence algorithms currently consume much more power than they should, in particular in the learning phase. The many aspects of this question are too often considered in isolation. Based on the complementary expertise of the partners, and thanks to the integration into the rich community build by the PEPR on foundation of frugal AI, we will instead systematically look at a holistic, global comprehension of all these issues in established and upcoming AI algorithms. We will therefore combine more compact and efficient number representations, hard-ware-aware training algorithms that enhance structured sparsity, coding compactness and tensor transformations, with their adaptation to efficient hardware mechanisms and compiler optimizations. Our ambition is to provide breakthroughs in efficiency when running inference and training algorithms on specialized hardware. The results are intended to be integrated into development solutions for embedded systems, in particular within the DeepGreen national platform for the deployment of deep learning in embedded systems.

9.4.13 PEPR ARCHI-SESAM

Participants: Marcello Traiola, Olivier Sentieys.

• Program: PEPR Cloud
• Project acronym: ARCHI-SESAM
• Project title: Converged, Efficient and Safe Architecture based on Near Memory Accelerators
• Duration: Oct 2023 – Dec 2029
• Coordinator: Denis Dutoit, CEA, Grenoble
• Other partners: Taran, CEA List, IMT, Inria Convecs, Grenoble-INP

European sovereignty in the cloud also means sovereignty over hardware, especially processors and accelerators. Improvement of processor performance requires hardware architectures that evolve towards more parallelism (multi-core), more specialization (accelerators), a closer relationship between computing and memory and new types of interconnections between components. On the other hand, by dissociating hardware resources (computing, memory, interconnection) from logical resources, virtualization facilitates the deployment of converged architectures that bring together the computing, storage and network infrastructure. The cloud gains in modularity, speed and agility for the deployment of new services with optimal use of resources. Hardware disaggregation on the one hand and resource virtualization on the other are making the intermediate adaptation layer increasingly complex, difficult to validate and prone to failure. The Archi-CESAM project proposes to rethink the hardware (computing, memory and interconnection) so that it is co-designed with the application in a perspective of converged architecture and trust, in an environment known for its abundance of data to be processed. The Archi-CESAM project addresses this major evolution of the Cloud in a global and coordinated approach between distributed architectures, acceleration, interconnection and security bricks, without forgetting the design methods.

9.4.14 Inria Challenge CocoRISCo

Participants: Simon Rokicki, Ronan Lashermes, Olivier Sentieys.

• Program: Inria Challenge
• Project acronym: CocoRISCo
• Project title: Hardware-software interface for general purpose computing with RISC-V
• Duration: Oct 2024 – Sep 2028
• Coordinator: Olivier Sentieys, Taran, Arthur Pérais, TIMA
• Other partners: CEA List, Inria (Corse, Benagil, Pacap, Sushi, Madmax, Taran)

CocoRISCo focuses on the hardware and low-level software aspects of computer systems. Specifically, those systems have dramatically evolved in the past decades, yet many interfaces between hardware and software layers have remained in place with little changes. Indeed, hardware has become heavily multithreaded (e.g., multi-, many-cores, GPUs), heterogeneous (e.g., dedicated accelerators attached to CPUs), and open to vulnerabilities caused by increased complexity (e.g., speculation-based attacks à la Spectre). We aim to leverage the RISC-V open Instruction Set Architecture (ISA) – the interface between software and the CPU – to revisit and improve those aspects, for instance by exposing more hardware features to the programmer. CocoRISCo will gather 5 Inria teams that have a background in architecture, microarchitecture, compilation, operating systems, and security, along with the SLS team of the TIMA laboratory and the DSCIN of laboratory CEA List.

9.4.15 RAPID FOCH

Participants: Joseph Paturel, Olivier Sentieys.

• Program: RAPID
• Project acronym: FOCH
• Project title: Development of a fault-tolerant FPGA with tests in high-radiation environments
• Duration: Jan 2023 – Dec 2025
• Coordinator: NanoXplore
• Other partners: Taran, Onera, Nucletudes

FPGA components are widely used in aerospace and military applications. This project aims to consider constrained radiative environments and to develop a fault-tolerant FPGA IP. A RISC-V processor will be used as a test case for implementation on the FPGA IP and for evaluation in high-radiation environments.

9.4.16 Inria Challenge OmicFinder

Participants: Bertrand Le Gal, Olivier Sentieys.

• Program: Inria Challenge
• Project acronym: OmicFinder
• Project title: Biological data indexation
• Duration: Oct 2023 – Dec 2027
• Coordinator: Pierre Peterlongo, Genscale
• Other partners: Taran, Dyliss, Zenith, CEA-GenoScope, Elixir, Pasteur Institute, CEA-CNRGH, Mediterranean Institute of Oceanography

Genomic data enable critical advances in medicine, ecology, ocean monitoring, and agronomy. Precious sequencing data accumulate exponentially in public genomic data banks such as the ENA. A major limitation is that it is impossible to query these entire data (petabytes of sequences). OmicFinder aims to provide a novel global search engine making it possible to query nucleotidic sequences against the vast amount of publicly available genomic data. The central algorithmic idea of a genomic search engine is to index and query small exact words (hundreds of billions over millions of datasets), as well as the associated metadata. In addition to the creation of fundamental novel algorithms and data structures, the project develops new approaches to improve the query experience and the answer information by integrating the Semantic Web technologies framework. In view of the considered volume of data, a part of the research focuses on clever index distribution. Throughout the project, we are committed to proposing methods that minimize the environmental impact generated by the massive use of the tools that will be produced, in particular through the use of specialized hardware.

10.1.1 Scientific events: organisation

10.1.2 Scientific events: selection

10.1.3 Journal

10.1.4 Invited talks

• O. Sentieys gave an invited talk on Design and Exploration of RISC-V Cores from High-Level Specifications at the 2nd Sino-European RISC-V Workshop, Hong-Kong, 27-29 Nov. 2024.

10.1.5 Leadership within the scientific community

• D. Chillet is a member of the French National University Council in Signal Processing and Electronics (CNU - Conseil National des Universites, 61ème section) since 2019.
• D. Chillet is member of the Board of Directors of Gretsi Association.
• A. Kritikakou is a member of the French National University Council in Computer Science (CNU - Conseil National des Universites, 27ème section) since 2022.
• A. Kritikakou is co-animator of the "High performance embedded computing" topic of GDR SoC2.
• O. Sentieys is a member of the steering committee of a CNRS Spring School for graduate students on embedded systems architectures and associated design tools (ARCHI).
• O. Sentieys is a member of the steering committee of GDR SoC2.

10.1.6 Scientific expertise

• S. Derrien was a member of the ANR Scientific Evaluation Committee CE25 "Software science and engineering - Multi-purpose communication networks, high-performance infrastructure".
• D. Chillet has done a scientific expertise for a research project submitted to German Research Foundation.

10.1.7 Research administration

• S. Derrien was the head of the D3 "Computer Architecture" Department of IRISA Lab until Aug. 2024.

10.1.8 Standardization activities

• S. Filip and O. Sentieys are members of the IEEE P3109 Standardization Group on Arithmetic Formats for Machine Learning.

10.2.1 Teaching administration

• A. Kritikakou is a member of the Examination Committee of Industrial Engineering Sciences and Computer Engineering (SII) Aggregation.
• E. Casseau is in charge of the Department of “Digital Systems” at ENSSAT Engineering Graduate School.
• B. Le Gal is associate director of studies at ENSSAT Engineering Graduate School since Nov 2024.
• D. Chillet was associate director of studies at ENSSAT Engineering Graduate School until Sept 2024.
• S. Rokicki is responsible of the second year of the computer science department at ENS Rennes

10.2.2 Teaching

• D. Chillet: embedded processor architecture, 20h, Enssat (M1)
• D. Chillet: multimedia processor architectures, 30h, Enssat (M2)
• D. Chillet: advanced processor architectures, 20h, Enssat (M2)
• D. Chillet: advanced processor architectures, 15h, Embedded Systems Master (M2)
• D. Chillet: micro-controller, 32h, Enssat (L3)
• D. Chillet: low-power digital CMOS circuits, 4h, UBO (M2)
• A. Kritikakou: Tools and programming in C, 24.75h, istic (L3)
• A. Kritikakou: Computer programming, 22.5h, istic (L3)
• A. Kritikakou: Unix commands and programming, 6.75h, istic (L3)
• A. Kritikakou: Fault tolerant embedded systems, 6h, INSA (M2)
• A. Kritikakou: Energy sobriety of digital architectures, 7.5h, INSA (M2)
• B. Le Gal: Digital fundamentals, 24h, ENSSAT (L3)
• B. Le Gal: VHDL design, 32h, ENSSAT (M1)
• B. Le Gal: Hardware & software verification, 12h, ENSSAT (M1)
• B. Le Gal: Processor design (RISC-V), 26h, ENSSAT (M1)
• B. Le Gal: Real-time programming, 26h, ENSSAT (M1)
• B. Le Gal: Software compilation, 16h, ENSSAT (M2)
• B. Le Gal: System on Chip design, 18h, ENSSAT (M2)
• B. Le Gal: High performance computing, 16h, ENSSAT (M2)
• S. Rokicki: Compilers, 24h, ENS Rennes
• S. Rokicki: Advanced Compilers, 10h, ENS Rennes
• O. Sentieys: Hardware Accelerators for Deep Neural Networks, 54h, Master of Embedded Systems, istic (M2)
• O. Sentieys, High-Level synthesis, 20h, Master of Computer Science, istic (M2)
• M. Traiola: Operating Systems, 24h, ENS Rennes (Aggregation Mecatronique)
• M. Traiola: Hardware Accelerators for Deep Neural Networks, 12h TP, Master of Embedded Systems, istic (M2)
• F. Fernandes dos Santos: TinyML at Master SE istic(6h).
• F. Fernandes dos Santos: C/Unix for L3 (39h TPs)

10.2.3 Educational class

• M. Traiola gave a 2-hour educational class on "Efficient Neural Networks: from SW optimization to specialized HW accelerators" at Embedded System Week 2024 34

10.2.4 PhD Supervision

• PhD defended: Jean-Michel Gorius, High-Level Synthesis of Instruction Set Processors, Dec. 2024, S. Derrien, S. Rokicki.
• PhD defended: Corentin Ferry, CAutomating the derivation of memory allocations for acceleration of polyhedral programs, Feb. 2024, S. Derrien, T. Yuki and S. Rajopadhye (co-tutelle between Univ Rennes and Colorado State University).
• PhD defended: Cédric Gernigon, Neural Network Quantization Methods for FPGA On-Board Processing of Satellite Image, Dec. 2024, O. Sentieys, S. Filip.
• PhD defended: Ibrahim Krayem, Methods for fast exploration of manycore architectures based network-on-chip with emerging technologies, Feb. 2024, C. Killian, D. Chillet.
• PhD defended: Leo Pradels, Efficient CNN Inference Acceleration on FPGAs: A Pattern Pruning-Driven Approach, CIFRE Thesis with Safran, Dec. 2024, D. Chillet, S. Filip.
• PhD defended: Louis Narmour, Optimizations of Polyhedral Reductions and their use in Algorithm-Based Fault Tolerance, Dec. 2024, S. Derrien, T. Yuki and S. Rajopadhye (co-tutelle between Université de Rennes and Colorado State University).
• PhD in progress: Sohaib Errabii, Dynamically Configurable Deep Neural Network Hardware Accelerators, April 2024, M. Traiola, O. Sentieys.
• PhD in progress: Anis Yagoub, Exploring dynamically reconfigurable floating-point units for transprecision computation in deep learning, CIFRE Thesis with Keysom SAS, Sep. 2024, B. Le Gal, O. Sentieys.
• PhD in progress: Lucas Roquet, Dependability Evaluation and Enhancing Methods for Large Machine Learning Models, Oct. 2024, F. Fernandes dos Santos, A. Kritikakou.
• PhD in progress: Romain Facq, Exploring low precision arithmetic for continual learning tasks on edge devices, Oct. 2024, O. Sentieys, S. Filip.
• PhD in progress: Nesrine Sfar, Compression, fine-tuning, and hardware acceleration of Transformer-based models, Dec. 2024, O. Sentieys, S. Filip.
• PhD in progress: Dylan Leothaud, Automatic synthesis of secure and predictable processors for the Internet of Thing, Oct. 2023, S. Derrien, S. Rokicki.
• PhD in progress: Leo Pajot, Soft-core processor with dynamic binary execution exploiting instruction-level parallelism, CIFRE Thesis with Keysom SAS, Sep. 2023, B. Le Gal, S. Rokicki.
• PhD in progress: Oussama Ait Sidi Ali, Virtualisation of a multi-mission telemetry receiver, CIFRE Thesis with Safran, Apr. 2022, B. Le Gal.
• PhD in progress: Hamza Amara, Detection and countermeasures for DoS attack in Noc-based SoC using machine learning, Oct. 2022, E. Casseau, D. Chillet, C. Killian.
• PhD in progress: Herinomena Andrianatrehina, Ensuring confidentiality in modern Out-of-Order cores, Nov 2022, S. Rokicki, R. Lashermes.
• PhD in progress: Gaetan Barret, Predictive model of energy consumption of cloud-native applications, Nov. 2022, D. Chillet.
• PhD in progress: Sami Ben Ali, Efficient Low-Precision Training for Deep Learning Accelerators, Jan. 2022, O. Sentieys, S. Filip.
• PhD in progress: Benoit Coqueret, Physical Security Attacks Against Artificial Intelligence Based Algorithms, CIFRE Thesis with Thales, Nov. 2022, O. Sentieys, M. Carbone (Thales), G. Zaid (Thales).
• PhD in progress: Wilfread Guilleme, Fault Tolerant Hardware Architectures for Artificial Intelligence, Oct. 2022, D. Chillet, C. Killian, A.Kritikakou.
• PhD in progress: Guillaume Lomet, Guess What I'm Learning: Side-Channel Analysis of Edge AI Training Accelerators, Oct. 2022, C. Killian, R. Salvador, O. Sentieys
• PhD in progress: Romaric (Pegdwende) Nikiema, Time-guaranteed and reliable execution for real-time multicore architectures, Oct. 2022, A. Kritikakou, M. Traiola
• PhD in progress: Baptiste Rossigneux, Adapting sparsity to hardware in neural networks, Nov. 2022, E. Casseau, I. Kucher (CEA), V. Lorrain (CEA).
• PhD in progress: Louis Savary, Security of DBT-based processors, Sept 2022, S. Rokicki, S. Derrien.
• PhD in progress: Léo De La Fuente, In-Memory Computing for Ultra Low Power Architectures, Nov. 2021, O. Sentieys, J.-F. Christmann (CEA).
• PhD in progress: Seungah Lee, Efficient Designs of On-Board Heterogeneous Embedded Systems for Space Applications, Nov. 2021, A. Kritikakou, E. Casseau, R. Salvador, O. Sentieys.
• PhD in progress: Amélie Marotta, Emp-error: EMFI-Resilient RISC-V Processor, Oct. 2021, O. Sentieys, R. Lashermes (LHS), Rachid Dafali (DGA).

International journals

• 21 articleP.Pavitra Bhade, J.Joseph Paturel, O.Olivier Sentieys and S.Sharad Sinha. Lightweight Hardware-Based Cache Side-Channel Attack Detection for Edge Devices (Edge-CaSCADe).ACM Transactions on Embedded Computing Systems (TECS)23June 2024, 1 - 27HALDOIback to text
• 22 articleP. R.Pablo R Bodmann, M.Matteo Saveriano, A.Angeliki Kritikakou and P.Paolo Rech. Neutrons Sensitivity of Deep Reinforcement Learning Policies on EdgeAI Accelerators.IEEE Transactions on Nuclear Science718August 2024, 1480-1486HALDOIback to text
• 23 articleA.Alberto Bosio, S.Samuele Germiniani, G.Graziano Pravadelli and M.Marcello Traiola. Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs.Journal of Electronic Testing: : Theory and Applications402April 2024, 199-214HALDOIback to text
• 24 articleF.Fernando Fernandes dos Santos, L.Luigi Carro, F.Flavio Vella and P.Paolo Rech. Assessing the Impact of Compiler Optimizations on GPUs Reliability.ACM Transactions on Architecture and Code Optimization212January 2024, 1-22HALDOIback to text
• 25 articleF.Fernando Fernandes dos Santos, N.Niccolò Cavagnero, M.Marco Ciccone, G.Giuseppe Averta, A.Angeliki Kritikakou, O.Olivier Sentieys, P.Paolo Rech and T.Tatiana Tommasi. Improving Deep Neural Network Reliability via Transient-Fault-Aware Design and Training.IEEE Transactions on Emerging Topics in Computing2024, 1-12In press. HALback to text
• 26 articleF.Fernando Fernandes dos Santos and P.Paolo Rech. Can GPU Performance Increase Faster Than the Code Error Rate?Journal of SupercomputingApril 2024, 1-32In press. HALDOIback to text
• 27 articleF.Fernando Fernandes dos Santos and P.Paolo Rech. Challenges in Assessing and Improving Deep Neural Networks Reliability.IEEE Design & Test2024, 1-6In press. HALback to text
• 28 articleP.Prachi Kashikar, O.Olivier Sentieys and S.Sharad Sinha. Combining Weight Approximation, Sharing and Retraining for Neural Network Model Compression.ACM Transactions on Embedded Computing Systems (TECS)23September 2024, 1 - 23HALDOIback to text
• 29 articleB.Bruno Loureiro Coelho, F.Fernando Fernandes dos Santos, M.Matteo Saveriano, G.Gregory Allen, A.Andrew Daniel, S.Steven Guertin, S.Sergeh Vartania, E.Edward Wyrwas, C.Christopher Frost and P.Paolo Rech. Impact of Radiation-Induced Effects on Embedded GPUs Executing Large Machine Learning Models.IEEE Transactions on Nuclear Science2025. In press. HAL
• 30 articleL.Lei Mo, X.Xinmei Li, A.Angeliki Kritikakou and X.Xiaojun Zhai. Contention and Reliability-Aware Energy Efficiency Task Mapping on NoC-Based MPSoCs.IEEE Transactions on Reliability2024, 1-16HALDOIback to text
• 31 articleM.Mael Tourres, C.Cyrille Chavet, B. L.Bertrand Le Gal and P.Philippe Coussy. Specialized Scalar and SIMD Instructions for Error Correction Codes Decoding on RISC-V Processors.IEEE Access132025, 6964-6976HALDOI
• 32 articleM.Marcello Traiola, F. F.Fernando Fernandes dos Santos, P.Paolo Rech, C.Carlo Cazzaniga, O.Olivier Sentieys and A.Angeliki Kritikakou. Impact of High-Level-Synthesis on Reliability of Artificial Neural Network Hardware Accelerators.IEEE Transactions on Nuclear Science2024, 1-9HALDOIback to text

Invited conferences

• 33 inproceedingsB.Benoît Coqueret, M.Mathieu Carbone, O.Olivier Sentieys and G.Gabriel Zaid. When Side-Channel Attacks Break the Black-Box Property of Embedded Artificial Intelligence.ESSAI 2024 - 1st edition European Symposium on Security and Artificial Intelligence (ESSAI)Rennes, France2024HALback to text
• 34 inproceedingsM.Marcello Traiola, A.Angeliki Kritikakou, S.-I.Silviu-Ioan Filip and O.Olivier Sentieys. Efficient Neural Networks: from SW optimization to specialized HW accelerators.2024 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)Raleigh (NC), United StatesIEEE; IEEESeptember 2024, 1-2HALDOIback to text

International peer-reviewed conferences

• 35 inproceedingsH.Hamza Amara, C.Cédric Killian, D.Daniel Chillet and E.Emmanuel Casseau. Mitigation of Hardware Trojan in NoC using Delta-Based Compression.SOCC 2024 - 37th IEEE International System-on-Chip ConferenceDresden, GermanyIEEE2024, 1-5HALDOIback to text
• 36 inproceedingsM.Mario Barbareschi, A.Alberto Bosio, P.Patrick Girard, B.Bastien Deveautour, M.Marcello Traiola and A.Arnaud Virazel. Approximate Computing for Test and Test of Approximate Computing.IEEE Workshop on Top Picks in VLSI Test and ReliabilitySan Diego, United States2024, 1-2HALback to text
• 37 inproceedingsS.Sami Ben Ali, S.-I.Silviu-Ioan Filip and O.Olivier Sentieys. A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training.DATE 2024 - 27th IEEE/ACM Design, Automation and Test in EuropeValencia, Spain2024, 1-6HALback to text
• 38 inproceedingsS.Sami Ben Ali, S.-I.Silviu-Ioan Filip, O.Olivier Sentieys and G.Guy Lemieux. MPTorch-FPGA: a Custom Mixed-Precision Framework for FPGA-based DNN Training.28th IEEE/ACM Design, Automation and Test in Europe (DATE)Lyon, France2025, 1-6HALback to text
• 39 inproceedingsJ.Junchao Chen, G.Giuseppe Esposito, F.Fernando Fernandes dos Santos, J.-D.Juan-David Guerrero-Balaguera, A.Angeliki Kritikakou, M.Milos Krstic, R.Robert Limas, J. E.Josie E Rodriguez Condia, M.Matteo Sonza Reorda, M.Marcello Traiola and A.Alessandro Veronesi. Reliability Assessment of Large DNN Models: Trading Off Performance and Accuracy.VLSI-SoC 2024 - IFIP/IEEE International Conference on Very Large Scale IntegrationTanger, MoroccoIEEE2024, 1-10HALDOIback to text
• 40 inproceedingsF.Fernando Fernandes dos Santos, M.Marcello Traiola and A.Angeliki Kritikakou. Combining Fault Simulation and Beam Data for CNN Error Rate Estimation on RISC-V Commercial Platforms.IOLTS 2024 - 30th IEEE International Symposium on On-Line Testing and Robust System DesignRennes, France2024, 1-8HALback to text
• 41 inproceedingsL.Léo de la Fuente, J.-F.Jean-Frédéric Christmann, M.Manuel Pezzin, M.Matthias Remars and O.Olivier Sentieys. A Hardware Instruction Generation Mechanism for Energy-Efficient Computational Memories.2024 IEEE International Symposium on Circuits and Systems (ISCAS)ISCAS 2024 - IEEE International Symposium on Circuits and SystemsISCASSingapour, SingaporeIEEE2024HALDOIback to text
• 42 inproceedingsC.Cédric Gernigon, S.-I.Silviu-Ioan Filip, O.Olivier Sentieys, C.Clément Coggiola and M.Mickael Bruno. AdaQAT: Adaptive Bit-Width Quantization-Aware Training.IEEE 6th International Conference on AI Circuits and Systems (AICAS)Abu Dhabi, United Arab Emirates2024HALback to text
• 43 inproceedingsD.Dennis Gnad, J.Jonas Krautter, A.Angeliki Kritikakou, V.Vincent Meyers, P.Paolo Rech, J.Josie Esteban Rodriguez Condia, A.Annachiara Ruospo, E.Ernesto Sanchez, F.Fernando Fernandes dos Santos, O.Olivier Sentieys, M. B.Mehdi B. Tahoori, R.Russell Tessier and M.Marcello Traiola. Reliability and Security of AI Hardware.ETS 2024 - 29th IEEE European Test SymposiumThe Hague, NetherlandsIEEE2024, 1-10HALback to text
• 44 inproceedingsJ.-M.Jean-Michel Gorius, S.Simon Rokicki and S.Steven Derrien. A Unified Memory Dependency Framework for Speculative High-Level Synthesis.CC 2024 - ACM SIGPLAN International Conference on Compiler ConstructionEdinburgh (Ecosse), United Kingdom2024, 1-13HALDOIback to text
• 45 inproceedingsW.Wilfread Guilleme, A.Angeliki Kritikakou, Y.Youri Helen, C.Cédric Killian and D.Daniel Chillet. HTAG-eNN: Hardening Technique with AND Gates for Embedded Neural Networks.DAC 2024 - IEEE/ACM Design Automation ConferenceSan Francisco, United States2024HALDOIback to text
• 46 inproceedingsW.Wilfread Guillemé, A.Angeliki Kritikakou, Y.Youri Helen, C.Cedric Killian and D.Daniel Chillet. VANDOR: Mitigating SEUs into Quantized Neural Networks.IOLTS 2024 - IEEE 30th International Symposium on On-Line Testing and Robust System DesignRennes, FranceIEEE2024, 1-6HALDOIback to text
• 47 inproceedingsM.Mohammad Hasan Ahmadilivani, A.Alberto Bosio, B.Bastien Deveautour, F.Fernando Fernandes dos Santos, J.Juan David Guerrero Balaguera, M.Maksim Jenihhin, A.Angeliki Kritikakou, R.Robert Limas Sierra, S.Salvatore Pappalardo, J.Jaan Raik, J.Josie Esteban Rodriguez Condia, M.Matteo Sonza Reorda, M.Mahdi Taheri and M.Marcello Traiola. Special Session: Reliability Assessment Recipes for DNN Accelerators.VTS 2024 - IEEE VLSI Test Symposium10Tempe AZ USA, United StatesIEEE2024, 131788 - 131828HALDOIback to text
• 48 inproceedingsL.Leonardo Iurada, N.Niccolò Cavagnero, F.Fernando Fernandes dos Santos, G.Giuseppe Averta, P.Paolo Rech and T.Tatiana Tommasi. Transient Fault Tolerant Semantic Segmentation for Autonomous Driving.UNCV 2024 - 3rd Workshop on Uncertainty Quantification for Computer VisionMilano, Italy2024, 1-6HALback to text
• 49 inproceedingsS.Seungah LEE, E.Emmanuel Casseau, A.Angeliki Kritikakou, O.Olivier Sentieys, R.Ruben Salvador and J.Julien Galizzi. On-board Payload Data Processing Combined with the Roofline Model for Hardware/Software Design.AeroConf 2024 - IEEE Aerospace ConferenceBig Sky, Montana, United States2024, 1-12HALDOIback to text
• 50 inproceedingsD.Dylan Leothaud, J.-M.Jean-Michel Gorius, S.Simon Rokicki and S.Steven Derrien. Efficient Design Space Exploration for Dynamic & Speculative High-Level Synthesis.FPL 2024 - 34th International Conference on Field-Programmable Logic and ApplicationsTurin, ItalyIEEE2024, 1-9HALDOIback to text
• 51 inproceedingsA.Amélie Marotta, R.Ronan Lashermes, G.Guillaume Bouffard, O.Olivier Sentieys and R.Rachid Dafali. Characterizing and Modeling Synchronous Clock-Glitch Fault Injection.COSADE 2024 - Constructive Side-Channel Analysis and Secure Design14595Lecture Notes in Computer ScienceGardanne, FranceSpringer Nature SwitzerlandApril 2024, 3-21HALDOIback to text
• 52 inproceedingsR. P.Romaric Pegdwende Nikiema, M.Marcello Traiola and A.Angeliki Kritikakou. Impact of Compiler Optimizations on the Reliability of a RISC-V-based Core.DFT 2024 - 37th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology SystemsOxfordshire, United Kingdom2024, 1-1HALback to text
• 53 inproceedingsJ.Juliette Pottier, T.Thomas Nieddu, B.Bertrand Le Gal, S.Sébastien Pillement and M.Maria Mendez Real. RISC-V processor enhanced with a dynamic micro-decoder unit.IEEE International Conference on Electronics, Circuits and SystemsNancy, FranceNovember 2024, paper #4224HAL
• 54 inproceedingsL.Léo Pradels, S.-I.Silviu-Ioan Filip, O.Olivier Sentieys, D.Daniel Chillet and T. L.Thibaut Le Calloch. FPGA-based CNN Acceleration using Pattern-Aware Pruning.AICAS 2024 - IEEE 6th International Conference on AI Circuits and SystemsAbu Dhabi, United Arab EmiratesIEEE2024, 228-232HALDOIback to text
• 55 inproceedingsL.Lucas Roquet, F.Fernando Fernandes dos Santos, P.Paolo Rech, M.Marcello Traiola, O.Olivier Sentieys and A.Angeliki Kritikakou. Cross-Layer Reliability Evaluation and Efficient Hardening of Large Vision Transformers Models.Design Automation Conference (DAC)San Francisco, United StatesJune 2024HALback to text
• 56 inproceedingsB.Baptiste Rossigneux, V.Vincent Lorrain, I.Inna Kucher and E.Emmanuel Casseau. Importance Resides In Activations: Fast Input-Based Nonlinearity Pruning.ICONIP 2024 Conference ProceedingsInternational Conference on Neural Information Processing (ICONIP)Auckland, New ZealandMarch 2025HAL
• 57 inproceedingsM.Marcello Traiola, S.Salvatore Pappalardo, A.Ali Piri, A.Annachiara Ruospo, B.Bastien Deveautour, E.Ernesto Sanchez, A.Alberto Bosio, S.Sepide Saeedi, A.Alessio Carpegna and A.Alessandro Savino. Approximate Fault-Tolerant Neural Network Systems.ETS 2024 - 29th IEEE European Test Symposium2024 IEEE European Test Symposium (ETS)La Haye, NetherlandsIEEE2024, 1-10HALDOIback to text
• 58 inproceedingsA.Anastasia Volkova, R.Rémi Garcia, F.Florent de Dinechin and M.Martin Kumm. Hardware-optimal digital FIR filters: one ILP to rule them all and in faithfulness bind them.Proceedings of the Asilomar conference2023 Asilomar Conference on Signals, Systems, and ComputersAsilomar, United StatesMarch 2024HAL

Conferences without proceedings

• 59 inproceedingsW.Wilfread Guilleme, Y.Youri Helen, R.Rémy Priem, A.Angeliki Kritikakou, C.Cedric Killian and D.Daniel Chillet. Hardening a Neural Network on FPGA through Selective Triplication and Training Optimization.RADECS 2024 - RADiation and its Effects on Components and Systems ConferenceToulouse, France2024, 1-4HAL
• 60 inproceedingsM.Michel Lemaire, D.Daniel Massicotte, J.Jeremy Poupart, P.Patrice Quinton and S.Sanjay Rajopadhye. Polyhedra at Work: Automatic Generation of VHDL Code for the Sherman-Morrison Formula.Impact 2024 - 14th International Workshop on Polyhedral Compilation TechniquesMunich, GermanyJanuary 2024, 1-10HAL
• 61 inproceedingsD.Dylan Leothaud, J.-M.Jean-Michel Gorius, S.Simon Rokicki, S.Simon Rokicki and S.Steven Derrien. Exploration efficace d'espace de conception pour la synthèse de haut niveau dynamique et spéculative.COMPAS 2024 - Conférence francophone d'informatique en Parallélisme, Architecture et SystèmeNantes, France2024, 1-8HALback to text
• 62 inproceedingsL.Lucas Roquet, F.Fernando Fernandes dos Santos, P.Paolo Rech, M.Marcello Traiola, O.Olivier Sentieys and A.Angeliki Kritikakou. MaxiMals: A Low-cost Hardening Technique for Large Vision Transformers.RADECS 2024 - Conference is an annual on RADiation Effects on Components and SystemsMaspalomas, Canary Islands, Spain2024, 1-5HAL
• 63 inproceedingsL.Louis Savary, S.Simon Rokicki and S.Steven Derrien. Hardware/Software Runtime for GPSA Protection in RISC-V Embedded Cores.DATE 2025Lyon, France2025HAL

Scientific book chapters

• 64 inbookM.Mario Barbareschi, S.Salvatore Barone, A.Alberto Bosio and M.Marcello Traiola. Automatic Approximation of Computer Systems Through Multi-objective Optimization.Design and Applications of Emerging Computer SystemsSpringer Nature SwitzerlandAugust 2024, 383-420HALDOIback to text

Doctoral dissertations and habilitation theses

• 65 thesisC.Corentin Ferry. Automating the derivation of memory allocations for acceleration of polyhedral programs.Université de Rennes; Colorado state universityFebruary 2024HAL
• 66 thesisC.Cédric Gernigon. Neural Network Quantization Methods for FPGA On-Board Pro- cessing of Satellite Images.Université de RennesDecember 2024HALback to text
• 67 thesisJ.-M.Jean-Michel Gorius. High-Level Synthesis of Instruction Set Processors.Université de RennesDecember 2024HAL
• 68 thesisI.Ibrahim Krayem. Methods for fast exploration of manycore architectures based network-on-chip with emerging technologies.Université de RennesFebruary 2024HAL
• 69 thesisL.Léo Pradels. Efficient CNN Inference Acceleration on FPGAs: A Pattern Pruning-Driven Approach.Université de RennesDecember 2024HAL

Reports & preprints

• 70 reportE.Elise Bannier, S.Simon Castellan, S.Steven Derrien, F.Francesca Galassi, L.Laurent Garnier, L.Ludovic Hoyet, A.Antoine l'Azou, N.Noé Lahaye, M.-M. J.Marc J.-M. Macé, O.Olivier Martineau, A.Arthur Masson, T.Thomas Maugey, B.Benjamin Ninassi, E.Erven Rohou, M.Matthieu Simonin and F.François Taïani. Reducing GHG emissions from business travel: A collaborative approach at IRISA/Inria.Groupe de travail « missions » IRISA / Centre Inria de l’Université de RennesMarch 2024, 1-16HALback to text
• 71 miscE.-M.El-Mehdi El Arar, M.Massimiliano Fasi, S.-I.Silviu-Ioan Filip and M.Mantas Mikaitis. Probabilistic error analysis of limited-precision stochastic rounding.2024, 1-21HALback to text
• 72 miscR.Rémi Garcia and A.Alexandre Goldsztejn. A computer-assisted proof that e is rational.March 2024HAL
• 73 miscR.Rémi Garcia. Reproducibility Limits of Mixed-Integer Linear Programming-based methods.2024HAL
• 74 miscP.Pablo de Oliveira Castro, E.-M.El-Mehdi El Arar, E.Eric Petit and D.Devan Sohier. Error Analysis of Sum-Product Algorithms under Stochastic Rounding.November 2024HAL

Other scientific publications

• 75 inproceedingsD.Dylan Leothaud, J.-M.Jean-Michel Gorius, S.Steven Derrien and S.Simon Rokicki. Speculative High-Level Synthesis of RISC-V Processors.RISC-V Summit Europe 2024Munich, Germany2024HALback to text
• 76 inproceedingsJ.Juliette Pottier, M.Maria Mendez Real, B.Bertrand Le Gal and S.Sébastien Pillement. Dynamic insertion of instructions dedicated to sidechannel attacks detection.2024 - Colloque National du GDR SoC2Toulouse, FranceJune 2024HAL
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