2025​​Activity reportProject-TeamEMERAUDE​​​‌

Audio-to-fixed​​ easier than float-to-fixed

In​​​‌ audio processing, we know​ that the inputs and​‌ outputs are fixed-point data,​​ and we also have​​​‌ a lot of domain​ knowledge about audio physics.​‌ This gives serious hope​​ that Faust audio can​​​‌ be compiled directly to​ fixed-point. This is a​‌ requirement for FPGAs, but​​ it will also reduce​​​‌ the latency and power​ consumption on software targets​‌ if we can use​​ their integer units. It​​ will also enable the​​​‌ compilation of Faust to‌ ultra-low-power microcontrollers without floating-point‌​‌ hardware.

“Domain-specific” is the​​ key word here making​​​‌ us confident that a‌ problem that is generally‌​‌ intractable (float-to-fixed conversion) can​​ be addressed with little​​​‌ or no modification to‌ a Faust program. The‌​‌ challenge here is to​​ keep this additional work​​​‌ so high-level and sound-related‌ that it is not‌​‌ a burden for a​​ musician or a sound​​​‌ engineer. A central objective‌ is that Faust programmers‌​‌ should not need to​​ become fixed-point experts. They​​​‌ should actually not be‌ anymore aware of the‌​‌ underlying arithmetic than they​​ currently are with floating-point.​​​‌ Being high-level is a‌ key reason for the‌​‌ success of Faust .​​

Automated error analysis for​​​‌ hardware computing just right‌

The main issue is‌​‌ to understand how arithmetic​​ errors propagate, are amplified,​​​‌ are accumulated, etc. in‌ a computation and in‌​‌ a circuit. This is​​ called error analysis.​​​‌ Then a general technique‌ 57 is to add‌​‌ enough bits to the​​ right of internal fixed-point​​​‌ formats so that errors‌ accumulate in these bits‌​‌ and the overall error​​ accumulation does not hinder​​​‌ the final quality of‌ the result. Error analysis‌​‌ is also managed by​​ a worst-case combination, but​​​‌ here there is nothing‌ implicit or hidden. This‌​‌ is therefore a comparatively​​ well understood problem, and​​​‌ there is no reason‌ to believe it cannot‌​‌ be fully automated in​​ a compiler that is​​​‌ already able to derive‌ the format information, building‌​‌ on the experience accumulated​​ when designing complex FloPoCo​​​‌ operators 56, 55‌, 47, 102‌​‌, 109.

Digital​​ filters as arithmetic objects​​​‌

Digital filters are essential‌ components of everyday electronics‌​‌ like radios, mobile phones,​​ etc., but also in​​​‌ audio systems of course.‌ Their design is a‌​‌ core topic in digital​​ signal processing and control​​​‌ theory, one that has‌ received significant research interest‌​‌ for the better part​​ of the last half​​​‌ century. A lot of‌ effort has gone into‌​‌ constructing flexible filter design​​ methods. For designing software-based​​​‌ digital filters with floating-point‌ coefficients, there are many‌​‌ powerful approaches that are​​ relatively easy to use​​​‌ by the filter designer‌ (all the more as‌​‌ they rely on over-dimensioned​​ floating-point operators). When designing​​​‌ hardware, things are not‌ that simple for several‌​‌ reasons:

• algorithms developed for​​ software-implemented filters cannot be​​​‌ transferred directly to hardware:‌ what is a constraint‌​‌ in software (e.g., “use​​ a 32-bit fixed-point format”)​​​‌ becomes a degree of‌ freedom in hardware design‌​‌ (“What is the smallest​​ fixed-point format that can​​​‌ be used?”);
• another degree‌ of freedom comes from‌​‌ different available realization techniques​​ to implement the arithmetic​​​‌ itself, for instance the‌ construction of multipliers by‌​‌ constants.

A consequence is​​ that popular tools, such​​​‌ as the popular fdatool‌ (filter design and analysis‌​‌ tool) from Matlab's Signal​​ Processing toolbox, offer a​​​‌ complex interface, requiring a‌ tedious hand-tuning process, and‌​‌ expect some domain expertise.​​ Such tools input a​​​‌ frequency response, and decompose‌ the filter implementation problem‌​‌ in three steps: 1/​​​‌ the filter design (FD)​ step consists in finding​‌ a filter with ideal​​ (high precision) coefficients that​​​‌ adheres to the frequency​ response; 2/ the quantization​‌ (Q) step converts the​​ obtained coefficients to hardware-friendly​​​‌ fixed-point values ; 3/​ the implementation (I) step​‌ generates a valid hardware​​ description (e.g., a VHDL​​​‌ or Verilog description) using​ the quantized coefficients.

The​‌ objective of this research​​ axis is to offer​​​‌ an optimal solution to​ the global FD +​‌ Q + I problem.​​ Optimal techniques exist for​​​‌ each of the FD,​ Q and I steps​‌ in isolation. The combination​​ of the FD &​​​‌ Q steps have been​ studied since the 1960's​‌  69, and can​​ even be regarded as​​​‌ solved for certain practical​ instances of fixed-point Finite​‌ Impulse Response (FIR) design​​ 70. A large​​​‌ body of work also​ exists for the I​‌ step, with recent optimal​​ approaches 40, 71​​​‌, 72. However,​ these approaches are only​‌ optimal for a given​​ set of coefficients, and​​​‌ therefore strongly depend on​ the FD and Q​‌ steps.

Arithmetic-oriented scheduling and​​ tiling for low-latency audio​​​‌

Finally, we also want​ to formally insert arithmetic​‌ considerations in the global​​ problem of distributing a​​​‌ very heavy computation between​ space (we have up​‌ to several thousands multipliers​​ in an FPGA, and​​​‌ many more if we​ multiply by a constant)​‌ and time (we have​​ thousands of FPGA cycles​​​‌ within one audio cycle).​ These are well-researched compilation​‌ issues, called the scheduling​​ and tiling problems. There​​​‌ is local expertise in​ Lyon (in particular in​‌ the CASH team and​​ its spin-off XtremLogic21​​​‌) who have worked​ on these problems for​‌ FPGAs. However, scheduling and​​ tiling techniques so far​​​‌ consider each operation as​ having a standard, constant​‌ cost (e.g., multiplication costs​​ $c_m$ and has​​​‌ latency $t_m$,​ addition costs $c_{\mathrm{a‌}}$ in space and ${\mathrm{t}}_a$ in time). This​​​‌ is a very crude​ simplification if one attempts​‌ to optimize each operator,​​ think for multiplications by​​​‌ constant for instance. The​ availability of many audio-related​‌ case studies in Emeraude​​ will allow us (hopefully​​​‌ in collaboration with CASH)​ to develop arithmetic-aware scheduling​‌ and tiling techniques that​​ will eventually prove useful​​​‌ well beyond the world​ of digital audio.

Towards​‌ provably optimal solutions

Recent​​ arrivals of Christine Solnon​​​‌ and Anastasia Volkova into​ the team bring more​‌ focus into the optimization.​​ Given a mathematical object​​​‌ to implement in hardware​ (for instance the 2D​‌ norm $\sqrt{x^2+y^2}$), the​​​‌ standard practice so far​ has been to 1/​‌ define a family of​​ hardware algorithms parameterized by​​​‌ architectural parameters (typically the​ number of bits for​‌ the intermediate results), 2/​​ express the constraints for​​​‌ a given solution to​ be acceptable (typically that​‌ the hardware should provide​​ a faithful or correct​​​‌ rounding of the exact​ result), and 3/ finally​‌ define a heuristic that​​ provides the parameters for​​​‌ an acceptable solution with​ good performance (performance being,​‌ for instance, area or​​ delay of the hardware).​​ The shift is to​​​‌ replace the heuristic in‌ the third step with‌​‌ a mathematical model that​​ can be solved with​​​‌ standard solvers (ILP, SAT‌ or CP) to provide‌​‌ hardware operators with provably​​ optimal performance. This approach​​​‌ was pioneered by Martin‌ Kumm about ten years‌​‌ ago, and used in​​ Emeraude recently for squarers​​​‌ 44, elementary function‌ evaluators 53, and‌​‌ digital filters 108.​​ In the coming years​​​‌ we will apply this‌ approach more broadly to‌​‌ operators for digital signal​​ processing (in collaboration with​​​‌ axes 1 and 3)‌ and artificial intelligence accelerators‌​‌ (in collaboration with other​​ members of the PEPR​​​‌ IA). We will also‌ use optimization for core‌​‌ classical arithmetic problems such​​ as function approximation and​​​‌ evaluation, compressor tree synthesis,‌ or word-length optimization, again‌​‌ in collaboration with Axis​​ 3.

The​​ Faust language and its​​​‌ compiler

A large part‌ of Emeraude's research results‌​‌ is visible thanks to​​ the Faust ecosystem development.​​​‌ Faust has gained an‌ international recognition, especially since‌​‌ it is used for​​ teaching at Stanford University​​​‌ (in the context of‌ courses on signal processing,‌​‌ physical interaction design, etc.)​​ and for developing new​​​‌ audio plugins 83.‌ The efforts needed to‌​‌ keep Faust as the​​ most efficient language for​​​‌ real-time audio processing involve‌ research in: language design,‌​‌ compiler design, and development​​ of DSP libraries.

One​​​‌ of the reason of‌ Faust 's success is‌​‌ that it is both​​ a language and an​​​‌ environment for audio signal‌ processing. The Faust compiler‌​‌ typically generates high-level codes​​ (in languages such as​​​‌ C, C++, etc.), following‌ every compiler's goal: providing‌​‌ better code than manually​​ written code. For that,​​​‌ it has to stick‌ to the most recent‌​‌ compiler technologies and processors​​ evolutions 77. For​​​‌ instance, a back-end for‌ WebAssembly was recently added‌​‌ to the Faust compiler​​ 76. An important​​​‌ deployment step was the‌ embedding of the Faust‌​‌ compiler in a web​​ browser 75 which makes​​​‌ it easily accessible on‌ all computers.

Faust language‌​‌ design research in Emeraude​​

The current design of​​​‌ Faust , inspired by‌ lambda-calculus, combinatory logic and‌​‌ John Backus’ functional programming,​​ has to be extended​​​‌ to face new challenges,‌ in particular multi-dimensional and‌​‌ multi-rate signals and linear​​ algebra.

Faust allows for​​​‌ the description of synchronous‌ mono-rate scalar DSP computations.‌​‌ This is sufficient to​​​‌ implement most time-domain algorithms​ such as filters, oscillators,​‌ waveguides, etc. However, this​​ makes the implementation of​​​‌ frequency-domain algorithms (i.e. based​ on FFT) very inefficient,​‌ not to say impossible.​​ One of our goals​​​‌ is to extend the​ language to enable multi-rate​‌ as well as vector​​ computations. While we already​​​‌ have a working prototype​ for this, some challenges​‌ have yet to be​​ overcome.

Along the lines​​​‌ of the previous point,​ Faust currently doesn't provide​‌ any support for efficient​​ matrix operations and more​​​‌ generally linear algebra. This​ prevents the implementation of​‌ some classes of DSP​​ algorithms such as Finite-Difference​​​‌ Time-Domain (FDTD) method for​ physical modeling. The skills​‌ of former Socrate members​​ on seminal Alpha language​​​‌ 58 and polyhedral optimization​ are very useful here.​‌

Support for the main​​ target programming languages in​​​‌ Faust is essential. Recently​ added languages (WebAssembly, Rust,​‌ and CMajor) have opened​​ many new opportunities. The​​​‌ FPGA target, studied in​ §3.1, introduces​‌ new challenges such as​​ the ability to use​​​‌ fixed-point arithmetic or the​ use of HLS for​‌ targeting hardware platforms (e.g.,​​ VHDL, Verilog, etc.). Other​​​‌ “exotic” architectures such as​ GPUs or MPSoCs should​‌ be studied for compute-bound​​ algorithms.

Musicians have to​​​‌ deal with a large​ variety of operating systems,​‌ software environments and hardware​​ architectures. Faust is designed​​​‌ to favor an easy​ deployment of DSP programs​‌ on all these targets​​ by making a clear​​​‌ separation between computation itself,​ as described by the​‌ program code, and how​​ this computation should be​​​‌ related to the external​ world. This relation (with​‌ audio drivers, GUIs, sensors,​​ etc.) is described in​​​‌ specific architecture files62​. Architecture files concern​‌ both hardware (i.e., audio​​ interfaces/sound cards) as well​​​‌ as software control interfaces​ (e.g., GUI, OSC,22​‌ MIDI), new luthieries (e.g.,​​ SmartFaust, Gramophone), Web platforms​​​‌ (Web audio Plugin), etc.​ One of the goal​‌ of the work of​​ Emeraude on Faust is​​​‌ to ease the programming​ of these audio systems.​‌

Faust ecosystem and DSP​​ libraries

Faust users are​​​‌ very attached to its​ ecosystem, including native applications,​‌ online and “embedded” audio​​ applications, Just In Time​​​‌ (JIT) compiler, etc. Recent​ developments include a JIT​‌ Faust compiler on the​​ Web, a JIT compiler​​​‌ in the Max/MSP environment,​ tools to find the​‌ best compilation parameters and​​ ease compilation for multiple​​​‌ CPUs. This is constantly​ evolving to answer to​‌ users' demand.

The Faust​​ DSP libraries currently implement​​​‌ hundreds of functions/objects ranging​ from simple oscillators and​‌ filters to advanced filter​​ architectures, physical models, and​​​‌ complete ready-to-use audio plugins.​ These libraries are at​‌ the heart of Faust​​ 's success and international​​​‌ position. Julius Smith23​ (Stanford professor) is one​‌ of the most respected​​ figures in the field​​​‌ of audio DSP and​ one of the main​‌ contributors to the Faust​​ libraries. One of the​​​‌ ambitions of the Emeraude​ team is to maintain​‌ and extend this tool​​ to make it as​​​‌ exhaustive and as universal​ as possible. Along these​‌ lines, new developments made​​ to the language presented​​ above (e.g., multi-rate, linear​​​‌ algebra, etc.) should be‌ ported to the libraries.‌​‌ Finally, dedicated libraries targeting​​ specific hardware platforms (e.g.,​​​‌ microcontrollers, FPGAs) should be‌ made available too.

Machine‌​‌ learning for digital signal​​ processing

Machine learning and​​​‌ deep learning in particular,‌ are playing an increasingly‌​‌ important role in the​​ field of audio DSP.​​​‌ Researchers are revisiting the‌ algorithmic techniques of signal‌​‌ synthesis and processing in​​ the light of machine​​​‌ learning, for instance for‌ speech processing 64.‌​‌ Recent breakthroughs such as​​ the use of machine​​​‌ learning use in the‌ context of Differentiable Digital‌​‌ Signal Processing (DDSP) 61​​ demonstrate its power. The​​​‌ extension of Faust applications‌ to artificial intelligence began‌​‌ with the PhD work​​ of Benjamin Quiédeville, expanding​​​‌ the scope of Faust‌ in the field of‌​‌ AI. The objective is​​ the introduction of an​​​‌ autodifferentiation primitive for Faust‌ programs, aimed at machine‌​‌ learning applications. The development​​ of new backends is​​​‌ planned, particularly for MLIR,‌ MOJO, and GPUs, as‌​‌ well as support for​​ emerging architectures, especially in​​​‌ the context of game‌ engines and VR/AR applications.‌​‌

Embedded systems for audio​​ processing

As Emeraude's name​​​‌ suggests it, the implementation‌ of audio Digital Signal‌​‌ Processing on embedded hardware​​ is at the heart​​​‌ of the project. We‌ naturally rely on the‌​‌ Faust language for these​​ implementations. The skills of​​​‌ Emeraude members in compilation‌ and embedded systems are‌​‌ used to add new​​ embedded target for audio​​​‌ processing, in particular FPGAs,‌ as explained previously. This‌​‌ action is a mix​​ of research and engineering​​​‌ work, it should be‌ very useful for the‌​‌ dissemination of audio processing​​ programming.

Haptics is a​​​‌ huge topic, especially in‌ the field of New‌​‌ Interfaces for Musical Expression​​ (NIME), which has been​​​‌ studied for many years‌ 51, 105.‌​‌ It has always been​​ tightly coupled to physical​​​‌ modeling because this sound‌ synthesis technique provides natural‌​‌ connections to the physical​​ world. A big part​​​‌ of the challenge is‌ technological because haptics require‌​‌ ultra low-latency and high​​ sampling resolution in order​​​‌ to be accurate. This‌ is at the heart‌​‌ of Emeraude 's goals.​​

Virtual and Augmented Reality​​​‌ (VR/AR) is not limited‌ to immersive 3D graphics,‌​‌ sound also has an​​ important role to play​​​‌ in that emerging field.‌ Lots of work have‌​‌ been done around using​​ VR environments as a​​​‌ creative tool for audio‌ 74, 49,‌​‌ 48. While many​​ VR-based musical instruments have​​​‌ been created in the‌ past 97, little‌​‌ work has been done​​ around implementing interfaces specifically​​​‌ targeting VR/AR audio environments,‌ especially in the context‌​‌ of 3D sound. This​​ is something that we​​​‌ plan to explore as‌ part of Emeraude.

Finally,‌​‌ beside ergonomic and HCI​​ aspects, the design of​​​‌ musical interfaces is impacted‌ by various kinds of‌​‌ technical limitations that we​​ plan to address as​​​‌ part of Emeraude. First,‌ just like for real-time‌​‌ audio processing, latency plays​​ a crucial role in​​​‌ this context. Similarly, the‌ “time resolution” (e.g., the‌​‌ sampling rate of the​​​‌ interfaces) can have a​ huge impact, especially when​‌ targeting specific kinds of​​ instruments such as drums.​​​‌ Finally, the “spatial resolution”​ (e.g., the number of​‌ sensor points per squared​​ centimeters on a tabletop​​​‌ interface) also impacts its​ quality. In this context,​‌ we would like to​​ develop an embedded, high-resolution,​​​‌ high-sampling-rate, multi-touch multi-dimensional (X​ and Y + pressure)​‌ interface/instrument leveraging the development​​ carried out in the​​​‌ previous axes. This work​ would be followed by​‌ a user study to​​ measure the impact of​​​‌ this type of advanced​ system on perception.

6.1.1 FloPoCo​​​‌

• Name:
  Floating-Point Cores, but​ not only
• Keyword:
  Synthesizable​‌ VHDL generator
• Functional Description:​​
  The purpose of the​​​‌ open-source FloPoCo project is​ to explore the many​‌ ways in which the​​ flexibility of the FPGA​​​‌ target can be exploited​ in the arithmetic realm.​‌
• URL:
  http://­flopoco.­org
• Contact:
  Florent​​ De Dinechin
• Participant:
  2​​​‌ anonymous participants
• Partners:
  ENS​ Lyon, Insa de Lyon,​‌ Inria, Fulda University of​​ Applied Science

6.1.2 Syfala​​​‌

• Name:
  Low-Latency Synthesizer on​ FPGA
• Keywords:
  FPGA, Compilers,​‌ High-level synthesis, Audio signal​​ processing
• Functional Description:

  The​​​‌ goal of Syfala is​ to design an FPGA-based​‌ platform for multichannel ultra-low-latency​​ audio Digital Signal Processing​​​‌ programmable at a high-level​ with Faust and C++​‌ and usable for various​​ applications ranging from sound​​​‌ synthesis and processing to​ active sound control and​‌ artificial sound field/room acoustics.​​

  A series of tools​​​‌ are currently being developed​ around SyFaLa. SyFaLa is​‌ freely accessible on GitHub:​​ https://github.com/inria-emeraude/syfala.

• URL:
  https://­faust.­grame.­fr/­syfala/
• Contact:​​​‌
  Tanguy Risset

6.1.3 FAUST​

• Name:
  Functional Audio Stream​‌
• Keywords:
  Audio, Functional programming​​
• Functional Description:

  The core​​ component of Faust is​​​‌ its compiler. It allows‌ to "translate" any Faust‌​‌ digital signal processing (DSP)​​ specification to a wide​​​‌ range of non-domain specific‌ languages such as C++,‌​‌ C, LLVM bit code,​​ WebAssembly, Rust, etc. In​​​‌ this regard, Faust can‌ be seen as an‌​‌ alternative to C++ but​​ is much simpler and​​​‌ intuitive to learn.

  Thanks‌ to a wrapping system‌​‌ called "architectures," codes generated​​ by Faust can be​​​‌ easily compiled into a‌ wide variety of objects‌​‌ ranging from audio plug-ins​​ to standalone applications or​​​‌ smartphone and web apps,‌ etc.

• URL:
  https://­faust.­grame.­fr/
• Contact:‌​‌
  Yann Orlarey
• Partners:
  GRAME,​​ Insa de Lyon, Inria​​​‌

7.2.1‌​‌ Distributing spatial audio

Participants:​​ Thomas Rushton, Romain​​​‌ Michon, Tanguy Risset‌.

In 21,‌​‌ we introduced a low-cost,​​ open, and scalable platform​​​‌ for distributed spatial audio‌ rendering. It seeked to‌​‌ reduce the financial and​​ technical barriers imposed by​​​‌ conventional immersive audio systems.‌ For that we proposed‌​‌ a distributed architecture in​​ which sound field synthesis​​​‌ algorithms, such as Wave‌ Field Synthesis (WFS) or‌​‌ ambisonics, are parallelized across​​ many inexpensive, networked embedded​​​‌ audio processors (see Fig.‌ 6). We focused‌​‌ on the central technical​​ challenge of achieving sufficiently​​​‌ precise time synchronization between‌ physically separate audio devices‌​‌ to preserve wavefront integrity.​​ To address this, we​​​‌ demonstrated how the IEEE‌ 1588 Precision Time Protocol‌​‌ (PTP), implemented using open-source​​ software on low-cost microcontroller​​​‌ platforms (specifically the Teensy‌ 4.1), can be used‌​‌ both to align audio​​ start times and to​​​‌ continuously correct sampling frequency‌ drift by conditioning each‌​‌ device's audio phase-locked loop.​​ Using an experimental setup​​​‌ with multiple microcontroller-based audio‌ nodes synchronized via a‌​‌ PTP-capable Ethernet switch, we​​​‌ show that without correction,​ clock drift accumulates to​‌ the millisecond range, whereas​​ with PTP-derived sampling frequency​​​‌ conditioning, relative timing errors​ are reduced by three​‌ orders of magnitude to​​ the microsecond level, corresponding​​​‌ to sub-millimeter acoustic discrepancies.​ These results demonstrate that​‌ accurate, synchronous audio reproduction​​ is feasible using inexpensive​​​‌ hardware and standard networking​ infrastructure, validating our approach​‌ as a practical foundation​​ for accessible distributed spatial​​​‌ audio systems and motivating​ future work on scalability,​‌ integration with conventional audio​​ workflows, and more computationally​​​‌ demanding applications such as​ real-time virtual acoustics and​‌ auralization.

Microcontroller-based WFS.

7.2.2 Real-Time Auralization on​​ FPGA

Participants: Rémi Jeunehomme​​​‌, Romain Michon,​ Tanguy Risset, Pierre​‌ Cochard, Stéphane Letz​​.

In 15,​​​‌ we investigated the feasibility​ of real-time auralization on​‌ FPGAs by implementing and​​ evaluating convolution-based artificial reverberation​​​‌ algorithms tailored to FPGA​ architectures. We focused on​‌ the computational challenges posed​​ by long room impulse​​​‌ responses and explored FPGA-based​ solutions as an alternative​‌ to traditional CPU- and​​ GPU-based approaches, motivated by​​​‌ the low latency, parallelism,​ and scalability offered by​‌ reconfigurable hardware. Using Syfala​​ 91 and High-Level Synthesis​​​‌ (HLS), we implemented two​ uniformly partitioned overlap-save convolution​‌ algorithms in C: a​​ time-domain approach (TUPOLS) based​​​‌ on direct convolution, and​ a frequency-domain approach (FUPOLS)​‌ relying on FFT-based circular​​ convolution. We analyzed their​​​‌ architectural suitability, detailing memory​ organization, dataflow pipelining, numerical​‌ format choices, and hardware-specific​​ optimizations required to meet​​​‌ real-time constraints on a​ Xilinx Zynq-based FPGA platform.​‌ We showed that while​​ the time-domain approach is​​​‌ severely limited by latency​ and resource consumption for​‌ impulse responses longer than​​ about one second, the​​​‌ frequency-domain approach achieved real-time​ performance for impulse responses​‌ exceeding ten seconds with​​ acceptable FPGA resource usage.​​​‌ This work opens the​ way to potential large-scale​‌ multichannel auralization applications on​​ FPGA.

7.2.3 Auralization of​​​‌ Paleoacoustics landscapes in Chauvet​ Cave

Participants: Romain Michon​‌.

In 22,​​ we reported on an​​​‌ ongoing interdisciplinary study carried​ out in the context​‌ of the MIRAGES associate​​ team (see §9.1.1​​​‌) aimed at measuring,​ analyzing, and auralizing the​‌ paleoacoustic landscapes of Chauvet​​ Cave (south of France),​​​‌ in order to better​ understand how sound may​‌ have shaped human experiences​​ of the cave during​​​‌ the Upper Paleolithic. We​ described the methodological and​‌ conservation-driven constraints that governed​​ our work, including restricted​​​‌ access to the cave,​ limitations on equipment, and​‌ the fact that measurements​​ were confined to modern​​ walkways, leaving large portions​​​‌ of the cave acoustically‌ undocumented. To address these‌​‌ challenges, we carried out​​ several field campaigns between​​​‌ 2022 and 2024, during‌ which we collected thousands‌​‌ of impulse responses using​​ low-impact measurement protocols based​​​‌ on exponential sine sweeps,‌ omnidirectional and Ambisonic microphones,‌​‌ and portable loudspeakers. We​​ analyzed the resulting data​​​‌ to assess signal quality‌ and extract room-acoustic parameters‌​‌ such as reverberation time,​​ clarity, and definition, showing​​​‌ that despite logistical constraints,‌ most measurements achieved sufficiently‌​‌ high signal-to-noise ratios for​​ reliable analysis. We then​​​‌ discussed how these measurements‌ informed multiple auralization frameworks,‌​‌ including offline convolution, web-based​​ interactive tools, real-time multichannel​​​‌ installations, virtual reality environments,‌ and museum exhibits, each‌​‌ offering different balances between​​ realism, interactivity, and accessibility.​​​‌ This work opens the‌ way to future research‌​‌ directions, including predictive acoustic​​ modeling based on reconstructed​​​‌ Paleolithic geometries, improved material‌ characterization, and expanded interactive‌​‌ auralization platforms, positioning this​​ work as a foundational​​​‌ step toward scientifically grounded‌ yet explicitly speculative reconstructions‌​‌ of prehistoric soundscapes for​​ both research and public​​​‌ engagement.

Measurements in the‌ Chauvet cave.

7.2.4‌ The Space Bar, an‌​‌ Embedded WFS Sound System​​

Participants: Benjamin Quiedeville,​​​‌ Romain Michon, Pierre‌ Cochard, Stéphane Letz‌​‌.

From November to​​ March, an embedded WFS​​​‌ system was designed and‌ built at the laboratory‌​‌ in the context of​​ an exhibition at the​​​‌ Grenoble INRIA centre, based‌ on an earlier prototype‌​‌ created by the Emeraude​​ team. It leverages the​​​‌ Syfala toolchain 91 developed‌ in the Emeraude team‌​‌ to create an FPGA​​ based, frugal and autonomous​​​‌ device capable of spatialising‌ a high number of‌​‌ audio sources on 32​​ speakers using a Wave​​​‌ Field Synthesis (WFS) 100‌ algorithm and controlled via‌​‌ a standard game controller.​​

The construction involved the​​​‌ building of the casing‌ and the electronic wiring‌​‌ of the FPGA board​​ on special multi channel​​​‌ audio interfaces 90 and‌ the programming of the‌​‌ integrated ARM CPU using​​ a custom Alpine Linux​​​‌ distribution provided by Syfala.‌ The role of this‌​‌ program is to open​​ audio files and send​​​‌ the audio data alongside‌ position control signals to‌​‌ the FPGA. The project​​ involved the publication of​​​‌ an article in the‌ proceeding of the Journées‌​‌ de l'Informatique Musicale conference​​ in Lyon in June​​​‌ 2025.

The composer Frédéric‌ Khan has worked in‌​‌ collaboration with GRAME on​​ the production of a​​​‌ musical piece to be‌ integrated in the device‌​‌ in march 2026, a​​ special version of the​​​‌ control program was implemented‌ to accomodate for composers‌​‌ for enhanced creativity and​​ ease of writting. Additional​​​‌ resources used during the‌ work were 92,‌​‌ 107, 104.​​

7.3.1 HAtorch: Hardware-aware‌ quantization-aware training for CNNs‌​‌

Participants: Bastien Barbe,​​ Romain Bouarah, Anastasia​​​‌ Volkova, Florent de‌ Dinechin.

Popular machine‌​‌ learning frameworks like PyTorch​​ and TensorFlow provide complete​​​‌ toolchains to design, train,‌ quantize and deploy convolutional‌​‌ neural networks (CNNs) on​​​‌ standard hardware (CPUs, GPUs,​ TPUs, NPUs, microcontrollers). However,​‌ custom hardware targets like​​ FPGAs, ASICs and research​​​‌ accelerators typically use non-standard​ number representations as well​‌ as limited operator sets,​​ and are poorly served​​​‌ by current lowering backends.​ Existing backend-driven approaches rigidly​‌ force training to their​​ internal formats and often​​​‌ hide lowering choices behind​ opaque layers and closed​‌ software development kits. Conversely,​​ unconstrained quantization that permits​​​‌ arbitrary numeric and operator​ freedom often produces models​‌ that are difficult to​​ implement efficiently, leading to​​​‌ an hardware gap between​ the trained and deployed​‌ model. This work introduces​​ HATorch, a PyTorch-based hardware-aware​​​‌ training framework that reduces​ this gap by enhancing​‌ quantization with hardware architecture​​ model on the arithmetic​​​‌ operator/format level. HATorch supports​ custom hardware-friendly quantization flows,​‌ exposing lowering decisions for​​ transparent model-hardware co-design. We​​​‌ demonstrate the toolflow on​ the new hardware-friendly multipliers​‌ based on 9.​​

This QAT framework is​​​‌ a shared contribution of​ two PhD students from​‌ the team, Bastien Barbe​​ and Romain Bouarah .​​​‌ The conference paper was​ accepted in 2025 and​‌ will be presented in​​ early 2026 at the​​​‌ 8th AccML Accelerated Machine​ Learning Workshop at the​‌ HiPEAC conference in Krakow.​​

HATorch is also being​​​‌ used for the exploration​ of other type of​‌ neural network architectures, based​​ on Kolmogorov-Arnlodi Networks (KANs)​​​‌ in the preliminary work​ 33.

From training​‌ to deplyment

7.3.2 Towards​​ frugality in Natural Language​​​‌ Processing classification models

Participants:​ Anastasia Volkova.

This​‌ line of work is​​ part of a broader​​​‌ collaboration on mixed-precision quantization-aware​ training (QAT) for NLP​‌ models, involving Anastasia Volkova,​​ Cédric Gernigon, Richard Dufour,​​​‌ and Xavier Pillet from​ Nantes University.

The first​‌ contribution, based on 14​​ and to be published​​​‌ at DASIP 2026, investigates​ mixed-precision quantization for BERT​‌ inference, with the goal​​ of reducing memory and​​​‌ computational costs while preserving​ accuracy. Unlike most prior​‌ work, the study jointly​​ considers mixed-precision quantization of​​​‌ both weights and activations​ (see Fig. 9),​‌ integrates knowledge distillation into​​ the quantization pipeline, and​​​‌ evaluates the impact of​ quantizing the embedding layer​‌ beyond token weights. Experiments​​ on the SQuAD and​​​‌ GLUE benchmarks show that​ mixed-precision configurations achieve substantial​‌ reductions in resource usage​​ without degrading performance.

Example​​​‌ of a mixed-precision configuration​ learned by AdaQAT

The second​‌ contribution (to be presented​​ at HiPEAC AccML workshop)​​​‌ extends this work to​ the question of whether​‌ low-bitwidth representations can be​​ learned jointly with new​​​‌ domain-specific knowledge during fine-tuning.​ Focusing on biomedical NLP​‌ under strong hardware constraints,​​ it studies the interaction​​ between domain-adaptive pre-training, fine-tuning,​​​‌ and extreme quantization. Experiments‌ on French biomedical data‌​‌ show that domain-specialized models​​ are more robust to​​​‌ aggressive quantization than generalist‌ ones, and that structural‌​‌ ternary quantization enables stable​​ training in very low-precision​​​‌ regimes. Even limited domain‌ adaptation significantly improves convergence,‌​‌ indicating that domain learning​​ and adaptation to low​​​‌ numerical precision can be‌ achieved simultaneously.

7.4.1​​ Double-Word Decomposition in a​​​‌ Combined FP16, BF16 and‌ FP32 Dot Product Add‌​‌ Operator

Participants: Oregane Desrentes​​, Florent de Dinechin​​​‌.

This work 12‌ introduces a fused Dot‌​‌ Product Add (DPA) operator​​ that supports mixed-precision operations​​​‌ for both machine learning‌ and numerical computing by‌​‌ combining FP16, BF16, and​​ FP32 multiplicands within a​​​‌ single hardware unit. The‌ key technical innovation is‌​‌ the use of an​​ intermediate floating-point format (E9S12)—with​​​‌ a 9-bit exponent and‌ 12-bit significand—that enables an‌​‌ exact double-word decomposition of​​ FP32 multiplicands and efficient​​​‌ internal representation of lower-precision‌ inputs. The resulting operator‌​‌ is correctly rounded for​​ FP16 products accumulated into​​​‌ FP32 and also emulates‌ the IEEE-compliant FP32 fused‌​‌ multiply-add when operating on​​ decomposed FP32 inputs, simplifying​​​‌ hardware compared to traditional‌ double-word software techniques. Synthesis‌​‌ results for a 4​​ nm technology node show​​​‌ that this combined operator‌ improves both performance and‌​‌ accuracy over software decomposition​​ approaches.

This contribution was​​​‌ recognised with the Best‌ Paper Award at the‌​‌ ARITH 2025 conference, highlighting​​ its significance in understanding​​​‌ and optimising the trade-offs‌ inherent in mixed-precision hardware‌​‌ design.

7.4.2 Reconfigurable constant​​ multiplication

Participants: Bastien Barbe​​​‌, Louis Ledoux,‌ Anastasia Volkova, Florent‌​‌ de Dinechin.

This​​ work 9 has been​​​‌ done in the context‌ of the PhD thesis‌​‌ of Bastien Barbe in​​ collaboration with the team's​​​‌ postdoc Xiao Peng .‌ It addresses the design‌​‌ of efficient hardware multipliers​​ in the context of​​​‌ extremely quantized deep neural‌ networks, where multiplications are‌​‌ performed with constants drawn​​ from a small, fixed​​​‌ set. Rather than relying‌ on standard numerical formats‌​‌ (e.g. int4), which constrain​​ both representation and hardware​​​‌ design, the approach assumes‌ that only a carefully‌​‌ chosen set of integer​​ constants needs to be​​​‌ supported. It proposes dedicated‌ reconfigurable shift-and-add architectures capable‌​‌ of implementing these constants​​ efficiently by switching between​​​‌ pre-computed computation graphs. In‌ this setting, constants are‌​‌ represented implicitly through configuration​​ bits that select the​​​‌ appropriate circuit, allowing values‌ of larger magnitude to‌​‌ be handled with fewer​​ bits than standard encodings.​​​‌ Experimental results show that‌ the proposed algorithms outperform‌​‌ existing heuristics, support a​​ larger number of constants​​​‌ simultaneously, and lead to‌ more efficient multiplier designs‌​‌ in terms of hardware​​ cost.

Example of a​​​‌ two-adder RSCM.

7.4.3 Constraint programming models​​​‌ for multiple constant multiplication‌

Participants: Anastasia Volkova,‌​‌ Christine Solnon, Theo​​ Cantaloube.

The Multiple​​​‌ Constant Multiplication (MCM) problem‌ arises in many applications‌​‌ such as, for example,​​ digital signal processing. Given​​​‌ a set $T$ of‌ target constants, the goal‌​‌ of MCM is to​​​‌ find the most efficient​ way for multiplying an​‌ input number with each​​ constant in $T$,​​​‌ where multiplications are realized​ through bit-shifts and additions,​‌ and where intermediate results​​ may be shared to​​​‌ produce different target constants.​ State-of-the-art methods are based​‌ on Integer Linear Programming​​ (ILP), and suffer from​​​‌ numerous performance and scalability​ bottlenecks.

In 11 we​‌ have proposed for the​​ first time a Constraint​​​‌ Programming (CP) model for​ minimizing the number of​‌ adders for the MCM.​​ Compared to the state-of-the-art​​​‌ ILP approach, CP does​ not suffer from the​‌ curse of linearization, hence​​ permits significantly simpler formulations​​​‌ of the mathematical model.​ It is also more​‌ efficient, especially for the​​ hardest instances. We have​​​‌ also introduced a pseudo-polynomial​ time algorithm which is​‌ able to efficiently solve​​ some instances.

Performance comparison​​​‌ of MCM models.

This​ work has been done​‌ in the context of​​ a 6-month internship of​​​‌ Theo Cantaloube , co-supervised​ by Anastasia Volkova and​‌ Christine Solnon . Theo​​ Cantaloube has started a​​​‌ PhD thesis in October​ 2025. The goal of​‌ this thesis is to​​ investigate the capabilities of​​​‌ CP for solving this​ kind of problems.

7.4.4​‌ Optimization for other application​​ domains

Participants: Romain Fontaine​​​‌, Xiao Peng,​ Christine Solnon.

Beyond​‌ the application to arithmetic,​​ which is at the​​​‌ core of the research​ topics of Emeraude, we​‌ have also applied optimization​​ and constraint programming techniques​​​‌ to other problems: surface​ coverage by tethered robots​‌ 4, the travelling​​ salesman problem with time​​​‌ windows 5, 7​, and graph generation​‌ 19.

7.6.1‌​‌ The Faust programming language​​

Faust is a synchronous​​​‌ functional programming language inspired‌ by lambda calculus, combinatory‌​‌ logic, and John Backus'​​ FP. Its semantics is​​​‌ centered around the concept‌ of audio circuits. Programming‌​‌ in Faust primarily involves​​ constructing new audio circuits​​​‌ by assembling primitive ones‌ using an algebra of‌​‌ five composition operations. During​​ the period, however, Faust​​​‌ has evolved beyond simple‌ circuit assembly.

7.6.2 The‌​‌ Faust compiler

To support​​ Faust 's evolving functionality​​​‌ and optimize performance across‌ a wider range of‌​‌ platforms, recent advancements in​​ the Faust compiler—driven in​​​‌ part by the Syfala‌ project—have introduced innovative compilation‌​‌ techniques that now target​​ not only CPUs but​​​‌ also FPGAs, enabling efficient‌ code generation and dynamic‌​‌ processing capabilities on diverse​​ hardware architectures.

7.6.3 The Faust‌ ecosystem

9.1.1 Associate Teams in​ the framework of an​‌ Inria International Lab or​​ in the framework of​​​‌ an Inria International Program​

9.2.1 ANR‌ DIStrib

Interest around spatial‌​‌ audio has been booming​​ in recent years. An​​​‌ increasingly high number of‌ movie theaters, concert halls,‌​‌ Virtual Reality (VR) platforms​​ in museums, attractions in​​​‌ amusement parks, etc. are‌ equipped with advanced spatial‌​‌ audio systems involving a​​ large number of speakers.​​​‌ The automotive industry has‌ also recently shown interest‌​‌ in spatial audio for​​ its applications in the​​​‌ context of active noise‌ cancellation. When considering interactive‌​‌ applications (i.e., virtual acoustics,​​ soundscape rendering in VR,​​​‌ noise canceling, speaker correction,‌ speech intelligibility enhancement, etc.)‌​‌ involving real-time operations and​​ the ability the reprogram/customize​​​‌ the system, managing a‌ large number of individual‌​‌ audio channels requires a​​ tremendous amount of computational​​​‌ power and incredibly high‌ bandwidths, which current systems‌​‌ fail to provide. The​​ norm to implement such​​​‌ systems is to rely‌ on a centralized software-based‌​‌ approach: a powerful computer​​ connected to one or​​​‌ multiple audio interfaces providing‌ a limited number of‌​‌ audio outputs. In that​​ case, the bottleneck is​​​‌ the computer's throughput and‌ hence its ability to‌​‌ manage a large number​​ of audio streams in​​​‌ parallel with potential computations‌ applied to each of‌​‌ them.

The goal of​​ DIStrib is to rethink​​​‌ the way we approach‌ spatial audio systems by‌​‌ relying on a distributed​​ computing approach leveraging the​​​‌ computational power of large‌ Field-Programmable Gate Arrays (FPGA).‌​‌ In this system, each​​ FPGA is in charge​​​‌ of computing the sound‌ of a limited set‌​‌ of speakers. Conversely, the​​ distributed approach allows for​​​‌ a very large number‌ of speakers to be‌​‌ targeted. In order to​​ reach this goal, multiple​​​‌ challenges ranging from transmitting‌ audio streams to a‌​‌ large number of audio​​ devices with perfect synchronicity​​​‌ to running complex audio‌ Digital Signal Processing (DSP)‌​‌ algorithms on FPGAs must​​ be tackled. We believe​​​‌ that such a system‌ has the potential to‌​‌ be highly disruptive in​​ the field of spatial​​​‌ audio. DIStrib is also‌ the occasion to explore‌​‌ the potential of artificial​​ intelligence in the context​​​‌ of immersive sound and‌ virtual acoustics rendering by‌​‌ relying on emerging platforms​​ such as embedded NPUs​​​‌ (Neural Processing Unit).

DIStrib‌ is a 42 months‌​‌ JCJC ANR project that​​​‌ started in October 2025.​ Romain Michon is the​‌ Principal Investigator (PI) of​​ DIStrib.

9.2.2 PEPR HoliGrail​​​‌

A key challenge to​ reach the maximal efficiency​‌ is to match algorithms​​ with the underlying hardware.​​​‌ As the end of​ Moore’s law steadily approaches,​‌ hardware becomes increasingly heterogeneous,​​ and the interplay between​​​‌ algorithms and hardware even​ more important. From this​‌ point of view, artificial​​ intelligence algorithms are not​​​‌ efficient when run on​ commodity hardware such as​‌ microprocessors and GPUs. The​​ last decade has seen​​​‌ a boom of accelerators​ for common inference tasks​‌ (first in line was​​ Google’s TPU, followed by​​​‌ many others), now embedded​ in many consumer products.​‌ These accelerators offer hardware​​ that better matches the​​​‌ algorithms, but are still​ far from achieving the​‌ “inference per joule” performance​​ of the Human brain.​​​‌ Training deep neural networks​ (DNNs) is even less​‌ efficient, requiring orders of​​ magnitude more computation operations​​​‌ than inference.

We believe​ that there is a​‌ significant room for improvements​​ in both “inference per​​​‌ joule" and "training per​ joule”. The vision of​‌ this action is to​​ create a synergy with​​​‌ the research on the​ foundations of AI frugality​‌ (as proposed in SHARP​​ action) to propose cutting-edge​​​‌ methods that significantly improve​ the energy efficiency of​‌ both inference and training​​ of a model. We​​​‌ will propose (i) more​ compact and efficient number​‌ representations that still maintain​​ a quality of inference​​​‌ or training close to​ the reference, (ii) hardware-aware​‌ training algorithms that enhance​​ certain types of sparsity​​​‌ (e.g., more structured), coding​ compactness (aggressive quantization, maximum​‌ entropy) and tensor transformations.​​ Most state-of-the-art solutions are​​​‌ agnostic of the hardware​ they run on. By​‌ taking advantage of this​​ interplay between the hardware​​​‌ and the algorithms, we​ can achieve breakthroughs beyond​‌ current solutions, in particular​​ by developing (iii) efficient​​​‌ hardware mechanisms, especially optimized​ to take advantage of​‌ sparsity, extreme quantization and​​ ad-hoc number representations, together​​​‌ with (iv) compiler optimizations,​ to demonstrate the effectiveness​‌ of the proposed methods.​​ Our approaches are holistic​​​‌ in the sense that​ they will jointly optimize​‌ the whole computing stack​​ of AI, i.e., at​​​‌ the algorithm, arithmetic, compiler​ and hardware levels.

PEPR​‌ HOLIGRAIL kicked off in​​ March 2024 and will​​​‌ end in 2029 (extension​ has been anticipated). The​‌ project combines following partners:​​ Inria/IRISA Taran (Univ. Rennes,​​​‌ Inria, CNRS), List /LIAE​ (Université Paris Saclay, CEA),​‌ Inria Corse (Université Grenoble​​ Alpes), TIMA SLS (CNRS,​​​‌ Université Grenoble Alpes), CITI​ lab (INSA Lyon /​‌ Inria), List / LVML​​ (Université Paris Saclay, CEA).​​​‌ The scientific leaders are​ Olivier Bichler (CEA List)​‌ and Olivier Sentieys (Inria​​ Taran).

10.1.1 Scientific​​ events: organisation

10.1.2 Scientific events: selection​​

10.1.3 Journal

10.1.4 Invited‌ talks

• Romain Michon was‌​‌ an invited keynote speaker​​ at the Lambda Days​​​‌ conference36 which took‌ place in Krakow on‌​‌ June 12-13, 2025.
• Christine​​ Solnon was an invited​​​‌ keynote speaker at the‌ 31st International Conference on‌​‌ Principles and Practice of​​ Constraint Programming (CP 2025),​​​‌ the 14th IAPR-TC15 Workshop‌ on Graph-based Representations in‌​‌ Pattern Recognition (GBR 2025),​​ and the GreenDays 2025​​​‌
• Florent de Dinechin was‌ an invited keynote speaker‌​‌ at the ARITH 2025​​ conference and at the​​​‌ national meeting of the‌ GDR SoC2. He‌​‌ was also invited to​​ present one of his​​​‌ 2007 papers in a‌ retrospective session of ASAP‌​‌ 2025: ASAP since​​ the Millennium: A Selection​​​‌ of Most Representative Papers‌13.

10.1.5 Leadership‌​‌ within the scientific community​​

• Christine Solnon is member​​​‌ of the executive committee‌ of GDR RADIA.‌​‌
• Anastasia Volkova is a​​ part of the organizing​​​‌ comittee for the "Embedded‌ HPC" axis of GDR‌​‌ SoC2.
• Romain Michon is​​ the president of the​​​‌ Sound and Music Computing‌ (SMC) Network that steers‌​‌ the planning of the​​ SMC conference, one of​​​‌ the most prestigious scientific‌ event in the sound‌​‌ and music technology community.​​
• Romain Michon is a​​​‌ board member the Association‌ Française d'Informatique Musicale (AFIM)‌​‌ and of GRAME-CNCM, both​​ as secretary.

10.2.1 Juries​​​‌

• Anastasia Volkova was in​ the PhD jury of:​‌
  • Sami Ben Ali (Univ.​​ de Rennes), as examiner.​​​‌
• Romain Michon was in​ the PhD jury of:​‌
  • David Fiero (U. Paris​​ 8), as reviewer,
  • Alexandre​​​‌ d'Hooge (U. of Lille),​ as reviewer,
  • Daniel Picciola​‌ (U. Paris 8), as​​ reviewer.
• Christine Solnon was​​​‌ in the PhD jury​ of:
  • Jean-Baptiste Sciau (IMT​‌ Albi) as president,
  • Jorge​​ Mortes Alcaraz (IMT Atlantique)​​​‌ as president,
  • Stevan Stanovic​ (ENSICAEN) as president,
  • Guillaume​‌ Ghienne (IMT Atlantique) as​​ president,
  • Léon Fauste (U.​​​‌ Grenoble Alpes) as co-director,​
  • Fei Ge (ENTPE) as​‌ president,
  • Bachtiar Herdianto (IMT​​ Atlantique) as examiner,
  • Julien​​​‌ Rouzot (U. Toulouse) as​ examiner,
  • Djawad Bekkoucha (U.​‌ Caen) as examiner,
  • Alexandre​​ Ronsain (ENAC) as reviewer​​​‌ and president,
  • Fayad Ali​ Banna (U. Saint Etienne)​‌ as president,
  • Antoine Lhomme​​ (U. Grenoble Alpes) as​​​‌ president,
  • Arsène Marzorati (INSA​ Lyon) as president.
• Florent​‌ de Dinechin was in​​ the PhD jury of:​​​‌
  • Cheolyong Bae (Linköping University,​ Suède),
  • Jonas Bertels (KULeuven,​‌ Belgique),
  • Quentin Milot (Université​​ de Rennes).

10.3.1 Productions (articles, videos,​ podcasts, serious games, ...)​‌

Romain Michon served in​​ the scientific committee of​​​‌ the “Ça résonne37​” exhibit at the​‌ Maison des Mathématiques et​​ de l'Informatique (MMI) of​​​‌ Lyon University.

Christine Solnon​ wrote a paper on​‌ women in computation 28​​, and a column​​​‌ for La Recherche 39​.

10.3.2 Participation in​‌ Live events

Several concerts​​ where organized during the​​​‌ JIMLAC-25 conference which was​ mainly organized by Emeraude,​‌ the concert list can​​ be seen on JIMLAC​​​‌ program 38

10.3.3 Others​ science outreach relevant activities​‌

• Benjamin Quiedeville proposed a​​ demonstration of the spacebar​​​‌ 20 at the "fête​ de la science" in​‌ October 2025.
• Romain Michon​​ actively took part in​​​‌ the Chiche! program in​ 2025.
• Christine Solnon actively​‌ took part in the​​ Chiche! program in 2025,​​​‌ and she gave a​ conference on AI for​‌ the staff of ENSSIB​​
• Anastasia Volkova actively participated​​​‌ in Comptoire des Sciences​ and Déclic programs in​‌ 2025.

  

  The image is​​ a promotional poster with​​​‌ a green, high-tech aesthetic​ featuring a complex network​‌ of wires and electronic​​ components. The text reads​​​‌ "Exposant: Grame INRIA/INSA Lyon"​ at the top, indicating​‌ the exhibitors. It mentions​​ the event date as​​​‌ 15.11 (November 15) in​ Lyon, with the location​‌ specified as "@Périscope, Lyon."​​ At the bottom right,​​​‌ the phrase "Media Land"​ is partially visible, suggesting​‌ the event's theme or​​ name. (Description generated at​​​‌ February 2nd, 2026 by​ Albert AI with the​‌ model Mistral-Small-3.2-24B)

• Louis Ledoux participated in​‌ the first edition of​​ the Moduland electronic arts​​​‌ festival, organized by Le​ Séquenceur, by representing the​‌ Émeraude research team (INSA–Inria–GRAME).​​ He presented an experimental​​​‌ electronic instrument during a​ long public demonstration, leading​‌ to numerous exchanges with​​ festival attendees and practitioners.​​​‌ This highly successful inaugural​ edition offered strong visibility​‌ and contributed to the​​ promotion of the team’s​​​‌ work, emphasizing its concrete​ artistic realizations and the​‌ close articulation between research,​​ digital instrument design, and​​ contemporary electronic art practices.​​​‌ 3940

International journals

• 2‌ articleL.Louis Ledoux‌​‌, P.Pierre Cochard​​ and F.Florent de​​​‌ Dinechin. Towards Optimized‌ Arithmetic Circuits with MLIR‌​‌.Works in Progress​​ in Embedded Computing Journal​​​‌111September 2025‌, 4HALDOI‌​‌back to text
• 3​​ articleR.Romain Michon​​​‌, M.Michele Ducceschi‌, P.Pierre Cochard‌​‌, T.Travis Skare​​, C. J.Craig​​​‌ J Webb and R.‌Riccardo Russo. Evaluating‌​‌ CPU, GPU, and FPGA​​ Performance In the Context​​​‌ of Modal Reverberation: a‌ Comparative Analysis.Frontiers‌​‌ in Signal Processing5​​April 2025HALDOI​​​‌
• 4 articleX.Xiao‌ Peng, F.François‌​‌ Schwarzentruber, O.Olivier​​ Simonin and C.Christine​​​‌ Solnon. Spanning-tree based‌ coverage for a tethered‌​‌ robot.IEEE Robotics​​ and Automation LettersJanuary​​​‌ 2025, 1-8In‌ press. HALback to‌​‌ text
• 5 articleO.​​Omar Rifki and C.​​​‌Christine Solnon. On‌ the Phase Transition of‌​‌ the Euclidean Travelling Salesman​​ Problem with Time Windows​​​‌.Journal of Artificial‌ Intelligence Research82April‌​‌ 2025, 2167-2188HAL​​DOIback to text​​​‌
• 6 articleC.Christine‌ Solnon. LAD2025, A‌​‌ constraint-based solver for the​​ subgraph isomorphism problem.​​​‌Artificial Intelligence (AIJ)352‌March 2026, 104474‌​‌HALDOI

Invited conferences​​

• 7 inproceedings C.Christine​​​‌ Solnon. Anytime and‌ exact search for planning‌​‌ problems: How to explore​​ a DP-based state transition​​​‌ graph with A*, CP‌ and LS? 31st International‌​‌ Conference on Principles and​​ Practice of Constraint Programming​​​‌ (CP 2025) 41 2‌ Glasgow, United Kingdom 2025‌​‌ HAL DOI back to​​ text

International peer-reviewed conferences​​​‌

• 8 inproceedingsB.Bastien‌ Barbe, R.Romain‌​‌ Bouarah, F.Florent​​ de Dinechin and A.​​​‌Anastasia Volkova. Reducing‌ the Hardware Gap for‌​‌ Custom Accelerators through Quantization​​ Aware Training.AccML​​​‌ 2026 - 8th Workshop‌ on Accelerated Machine Learning‌​‌Krakow (Cracovie), PolandJanuary​​ 2026HAL
• 9 inproceedings​​​‌B.Bastien Barbe,‌ X.Xiao Peng,‌​‌ A.Anastasia Volkova and​​ F.Florent de Dinechin​​​‌. Towards optimal reconfigurable‌ constant multipliers.28th‌​‌ Euromicro Conference on Digital​​ System Design (DSD)28th​​​‌ Conference on Digital System‌ Design (DSD)Salerno, Italy‌​‌IEEESeptember 2025,​​ 418-425HALDOIback​​​‌ to textback to‌ textback to text‌​‌
• 10 inproceedingsR.Romain​​ Bouarah and F.Florent​​​‌ de Dinechin. Hardware‌ Fixed-Point 2D and 3D‌​‌ norms.32nd IEEE​​ International Symposium on Computer​​​‌ Arithmetic - ARITH 2025‌El Paso, Texas, United‌​‌ StatesMay 2025HAL​​
• 11 inproceedingsT.Théo​​​‌ Cantaloube, X.Xiao‌ Peng, C.Christine‌​‌ Solnon and A.Anastasia​​ Volkova. A new​​​‌ Constraint Programming model for‌ the Multiple Constant Multiplication‌​‌.ModRef 2025 -​​ 24th workshop on Constraint​​​‌ Modelling and ReformulationGlasgow,‌ United Kingdom2025HAL‌​‌back to textback​​​‌ to text
• 12 inproceedings​O.Orégane Desrentes,​‌ B.Benoît Dupont de​​ Dinechin and F.Florent​​​‌ de Dinechin. Double-Word​ Decomposition in a Combined​‌ FP16, BF16 and FP32​​ Dot Product Add Operator​​​‌.ARITH 2025 -​ IEEE 32nd International Symposium​‌ on Computer ArithmeticEl-Paso,​​ Texas, United StatesMay​​​‌ 2025HALback to​ textback to text​‌
• 13 inproceedingsF.Florent​​ de Dinechin. RETROSPECTIVE:​​​‌ Table-based polynomials for fast​ hardware function evaluation.​‌36th IEEE International Conference​​ on Application-specific Systems, Architectures​​​‌ and ProcessorsASAP 2025​ - 36th IEEE International​‌ Conference on Application-specific Systems,​​ Architectures and ProcessorsVancouver​​​‌ (British Columbia), CanadaJuly​ 2025HALback to​‌ text
• 14 inproceedingsC.​​Cédric Gernigon, X.​​​‌Xavier Pillet, A.​Anastasia Volkova and R.​‌Richard Dufour. Training​​ for Mixed-Precision Integer Weights,​​​‌ Activations and Embeddings in​ BERT.DASIP 2026:​‌ Workshop on Design and​​ Architectures for Signal and​​​‌ Image ProcessingKrakow (Cracovie),​ Poland2026HALback​‌ to text
• 15 inproceedings​​R.Rémi Jeunehomme,​​​‌ R.Romain Michon,​ T.Tanguy Risset,​‌ P.Pierre Cochard and​​ S.Stéphane Letz.​​​‌ TOWARDS REAL-TIME AURALIZATION ON​ FPGAS.SMC 2025​‌ - 22nd Sound and​​ Music Computing ConferenceGratz,​​​‌ AustriaInstitute of Electronic​ Music and Acoustics, University​‌ of Music and Performing​​ Arts Graz2025HAL​​​‌DOIback to text​
• 16 inproceedingsH.Hugues​‌ Kadi, M.Mathis​​ Devidal, R.Romain​​​‌ Michon and J.Johan​ Erbani. Real-Time Musical​‌ Instruments Recognition for Scenography​​ Purposes.Proceedings of​​​‌ the 19th Linux Audio​ ConferenceLinux Audio Conference​‌ 2025Lyon, FranceJune​​ 2025HAL
• 17 inproceedings​​​‌L.Louis Ledoux.​ Design-Space Exploration of Serialized​‌ Floating-Point Division for DLP​​ Architectures.DSD 2025​​​‌ - 28th Euromicro Conference​ on Digital System Design​‌Salerno, ItalySeptember 2025​​HAL
• 18 inproceedingsS.​​​‌Stéphane Letz and J.​Jeanne Ribeau. Applications​‌ audio web avec Faust​​ : innovations techniques au​​​‌ service de la transmission​.Proceedings of the​‌ 32th Journées d’Informatique Musicale​​Journées d'Informatique MusicaleLyon,​​​‌ FranceJune 2025HAL​back to text
• 19​‌ inproceedingsX.Xiao Peng​​ and C.Christine Solnon​​​‌. BFS-Based Canonical Codes​ for Generating Graphs with​‌ Constraint Programming.31st​​ International Conference on Principles​​​‌ and Practice of Constraint​ Programming (CP 2025)340​‌41Glasgow, United Kingdom​​August 2025HALDOI​​​‌back to text
• 20​ inproceedingsB.Benjamin Quiédeville​‌, R.Romain Michon​​, T.Tanguy Risset​​​‌ and S.Stéphane Letz​. The Space Bar:​‌ An Embedded WFS Sound​​ System.Proceedings of​​​‌ the 32th Journées d’Informatique​ MusicaleJIMLAC 2025 -​‌ Journées de l'Informatique Musicale​​Lyon, FranceJune 2025​​​‌HALback to text​
• 21 inproceedingsT.Thomas​‌ Rushton, R.Romain​​ Michon and T.Tanguy​​​‌ Risset. All Together​ Now: A Synchronous Platform​‌ for Distributed Spatial Audio​​.22nd Sound and​​​‌ Music Computing Conference (SMC2025)​Graz, AustriaInstitute of​‌ Electronic Music and Acoustics,​​ University of Music and​​​‌ Performing Arts GrazJuly​ 2025HALDOIback​‌ to text
• 22 inproceedings​​L.Luna Valentin,​​ J.Jonathan Abel,​​​‌ J.Jonathan Berger,‌ C.Chris Chafe,‌​‌ J.John Chowning,​​ C.Carole Fritz,​​​‌ N.Nima Farzaneh,‌ M.Miriam Kolar,‌​‌ R.Romain Michon,​​ S.Sara Martin,​​​‌ P.Peter Svensson and‌ M.Matthew Wright.‌​‌ Measurement and Auralization of​​ Paleoacoustics landscapes in Chauvet​​​‌ Cave.Proceedings of‌ Forum Acusticum11th Convention‌​‌ of the European Acoustics​​ Association Forum Acusticum /​​​‌ EuroNoise 2025Forum Acusticum‌ / EuroNoise 2025Málaga,‌​‌ SpainEuropean Acoustics Association​​December 2025, 3855-3864​​​‌HALDOIback to‌ text

National peer-reviewed Conferences‌​‌

• 23 inproceedingsO.Odile​​ Bellenguez, N.Nadia​​​‌ Brauner, C.Christine‌ Solnon and A.Alexis‌​‌ Tsoukias. Enseigner les​​ enjeux sociétaux et environnementaux​​​‌ des algorithmes à travers‌ un outil de navigation‌​‌ routière.ROADEF 2025​​ : 26ème congrès annuel​​​‌ de la Société Française‌ de Recherche Opérationnelle et‌​‌ d’Aide à la Décision​​Champs sur Marme, France​​​‌February 2025HAL

Conferences‌ without proceedings

• 24 inproceedings‌​‌A.Aurélien Delage and​​ C.Christine Solnon.​​​‌ Un modèle de théorie‌ des jeux pour l’étude‌​‌ de stratégies de réduction​​ de l’impact environnemental humain​​​‌.26ème congrès annuel‌ de la société française‌​‌ de recherche opérationnelle et​​ d’aide à la décision​​​‌ (ROADEF)Marne-la-Vallée, FranceFebruary‌ 2025, 226-227HAL‌​‌DOI
• 25 inproceedingsO.​​Orégane Desrentes, F.​​​‌Florent de Dinechin and‌ B.Benoît Dupont de‌​‌ Dinechin. Reciprocal Square​​ Root Accelerated Using Hardware​​​‌ and Software Techniques.‌RAIM Meeting 2025: 16th‌​‌ Rencontres de l'Arithmétique en​​ Informatique Mathématique – A​​​‌ Tribute to Jean-Michel Muller‌Lyon, FranceNovember 2025‌​‌HAL
• 26 inproceedingsR.​​Romain Fontaine and C.​​​‌Christine Solnon. Large-scale‌ experiments on the Traveling‌​‌ Salesman Problem with Time​​ Windows.ROADEF 2025​​​‌ - 26ème congrès annuel‌ de la Société Française‌​‌ de Recherche Opérationnelle et​​ d’Aide à la Décision​​​‌Champs-sur-Marne, FranceFebruary 2025‌HAL
• 27 inproceedingsX.‌​‌Xavier Pillet, C.​​Cédric Gernigon, A.​​​‌Anastasia Volkova, R.‌Richard Dufour, A.‌​‌Adeline Granet and N.​​Nicolas Greffard. Quantization-aware​​​‌ training: a tradeoff between‌ training and fine-tuning for‌​‌ domain-specific language models.​​AccML 2026 - 8th​​​‌ Workshop on Accelerated Machine‌ LearningKrakow (Cracovie), Poland‌​‌January 2026HAL

Scientific​​ book chapters

• 28 inbook​​​‌C.Christine Solnon.‌ Le calcul, une histoire‌​‌ de femmes.Le​​ calcul à découvertCNRS​​​‌ Editions2025HALback‌ to text

Edition (books,‌​‌ proceedings, special issue of​​ a journal)

• 29 proceedings​​​‌Proceedings of the 32nd‌ Journées d'Informatique Musicale.‌​‌Journées d'Informatique MusicaleLyon,​​ FranceJuly 2025HAL​​​‌
• 30 proceedingsR.Romain‌ Michon and P.Pierre‌​‌ Lecomte, eds. Proceedings​​ of the 19th Linux​​​‌ Audio Conference.Proceedings‌ of the 19th Linux‌​‌ Audio ConferenceLyon, France​​June 2025HAL

Reports​​​‌ & preprints

• 31 misc‌O.Odile Bellenguez,‌​‌ N.Nadia Brauner,​​ C.Christine Solnon and​​​‌ A.Alexis Tsoukias.‌ Integrating ethical, societal and‌​‌ environmental issues into algorithm​​ design courses.January​​​‌ 2026HAL
• 32 misc‌O.Odile Bellenguez,‌​‌ N.Nadia Brauner,​​​‌ C.Christine Solnon and​ A.Alexis Tsoukias.​‌ Integrating ethical, societal and​​ environmental issues into algorithm​​​‌ design courses.January​ 2026HAL
• 33 misc​‌R.Romain Bouarah,​​ B.Bastien Barbe,​​​‌ A.Anastasia Volkova and​ F.Florent de Dinechin​‌. KANHard: Training Hardware-Friendly​​ Kolmogorov-Arnold Networks.November​​​‌ 2025HALback to​ text
• 34 reportP.​‌Pierre Cochard and L.​​Louis Ledoux. FloPoCo​​​‌ and MLIR: A Multi-Level​ Compilation Framework for Many​‌ Intents.Inria Lyon;​​ INSA lyon; CITI -​​​‌ Centre d'Innovation en Télécommunications​ et Intégration de services​‌September 2025HALback​​ to textback to​​​‌ text
• 35 miscM.​ L.Maria L. Reyna​‌ Cruz, K.Kristalys​​ Ruiz-Rohena, Y.Yahriel​​​‌ I. Guel, H.​Henry Salgado, L.​‌Lisa Taldir, E.​​Elian Pena Ramos,​​​‌ N.Natalia Cervantes,​ T.Tzetzaith Rivero,​‌ M.Martine Ceberio,​​ C.Christoph Lauter and​​​‌ A.Anastasia Volkova.​ Contribution to Error Analysis​‌ of Deep Neural Networks:​​ Case of the Activation​​​‌ Functions.November 2025​HAL

Other scientific publications​‌

• 36 inproceedingsP.Pierre​​ Cochard, L.Luc​​​‌ Forget, F.Florent​ de Dinechin and L.​‌Louis Ledoux. Towards​​ Multi-Level Arithmetic Optimizations.​​​‌EuroLLVM 2025 -Berlin,​ GermanyApril 2025HAL​‌
• 37 inproceedingsL.Louis​​ Ledoux, F.Florent​​​‌ de Dinechin and P.​Pierre Cochard. Arithmetic​‌ Lowering with Emeraude-MLIR: Bridging​​ Tensor and DSP Kernels​​​‌ to Silicon Datapaths.​PEPR IA Embarquée Workshop​‌Aussois (France), FranceJanuary​​ 2026HAL
• 38 article​​​‌M.Maxime Popoff,​ R.Romain Michon,​‌ T.Tanguy Risset,​​ P.Pierre Cochard,​​​‌ L.Louis Ledoux,​ S.Stéphane Letz,​‌ Y.Yann Orlarey and​​ F.Forent de Dinechin​​​‌. Frugalité et conception​ de circuits pour le​‌ traitement du signal audio​​ numérique.Revue Francophone​​​‌ d'Informatique et Musique11​December 2025HALDOI​‌back to text

Scientific​​ popularization

• 39 article C.​​​‌Christine Solnon. Peut-on​ remplacer le raisonnement humain​‌ par des algorithmes ?​​ La Recherche 580 January​​​‌ 2025 HAL back to​ text