Section: New Results

Logical time in Model-Based embedded design

Participants : Charles André, Frédéric Mallet, Julien Deantoni, Robert de Simone, Marie-Agnès Peraldi Frati, Régis Gascon, Calin Glitia, Kelly Garces Pernett, Benoît Ferrero, Nicolas Chleq, Arda Goknil.

The foundational basis of our approach to modeling and analysis of embedded systems using logical time and logical clock specification contraints (CCSL) is recalled in 3.2 , and was surveyed in [2] . This year we conducted a number of works exploiting this approach and promoting its introduction to various application domains.

Charles André presented the general approach in an invited lecture at the French Summer School on Real-Time, in Brest [21] .

The HDR manuscript of Frédéric Mallet, where the MARTE Time Model is deeply considered, also in relation with other standards such as AADL, was published in book format [39] .

In the article [19] we showed how CCSL observers could be encoded in the synchronous language Esterel, using crucial features of simultaneity, and how otherwise simultaneity could be obtained in simulation. This work was also presented internally as deliverable of the FUI Lambda project (see 8.2.3 ).

We drew a definite link with our activities on Process Network analysis (see 6.3 ), by showing how the CCSL primitives could be used to provide the loose timing semantic constraints of exiting PN models such as SDF (Synchronous Data-Flow domain of UC Berkeley's Ptolemy), and its Multi-Dimensionla extension (MD-SDF). This resulted in a journal publication [38] . Existing static schedules can then be obtained by analysis with K-Passa 5.2 , or simulated using TimeSquare 5.1 (with an ASAP strategy).

In a collaboration with researchers at East China Normal University (ECNU Shanghai), we showed how CCSL constraints could be translated towards the PROMELA language implemented in the SPIN model-checker, which once again raises the issues of faithfully modeling simultaneity. This work resulted in a communication at the ICECCS conference [33] . Following this work one of our co-author, Yin Ling, earned a one-year scholarship from the Chinese government to visit us as part of her PhD.

The usage of CCSL expressions in the role of predicate property formulas, and their comparison with the more classical temporal formalisms such as PSL (Property Specification Language), was investigated in [24] . A longer internal report version can be found at [42] .

In [23] we tackle the issue of recovering global information from multiple execution traces living in distinct logical time bases, with polychronous constraints relating them. The use for efficient debug of embedded systems from distributed traces is examplified on a case study of terrestrial robot. This work was conducted in the framework of the ANR RT-Simex project, see 8.2.1 .

A case study in modeling with logical time and CCSL, from requirements to implementation, based on an automotive spark ignition system, is provided in [31] . We worked more generally on the introduction of our approach to existing formalism in the automotive domain, such as EAST-ADL2 and AutoSar, as part of our contribution to the new ITEA2 Timmo2U project. Premises of this effort are described in [32] .

The use of CCSL constraints in general requirement engineering was also studied and demonstrated in a conference article, jointly with colleagues at ECNU Shanghai, presented at APSEC'2011 [22] .

The use and modeling of priorities amongst timed events (i.e., logical clock ticks), which has strong impacts on efficient logical clock based simulations and scheduling (as the choice of next event), is still a topic of ongoing work. Several advanced considerations are to be found as part of jean-François Le Tallec PhD thesis, to be defended in January 2012 [16] .