EN FR
EN FR
CORSE - 2016
Research Program
Application Domains
Bilateral Contracts and Grants with Industry
Bibliography
Research Program
Application Domains
Bilateral Contracts and Grants with Industry
Bibliography


Bibliography

Publications of the year

Doctoral Dissertations and Habilitation Theses

Articles in International Peer-Reviewed Journals

  • 4A. Bauer, Y. Falcone.

    Decentralised LTL Monitoring, in: Formal Methods in System Design, May 2016, vol. 48, no 1-2, 48 p. [ DOI : 10.1007/s10703-016-0253-8 ]

    https://hal.inria.fr/hal-01313730
  • 5M. Castro, E. Francesquini, F. Dupros, H. Aochi, P. Navaux, J.-F. Mehaut.

    Seismic Wave Propagation Simulations on Low-power and Performance-centric Manycores, in: Parallel Computing, 2016. [ DOI : 10.1016/j.parco.2016.01.011 ]

    https://hal.archives-ouvertes.fr/hal-01273153
  • 6C. Colombo, Y. Falcone.

    Organising LTL Monitors over Distributed Systems with a Global Clock, in: Formal Methods in System Design, May 2016, vol. 49, no 1-2, 50 p. [ DOI : 10.1007/s10703-016-0251-x ]

    https://hal.inria.fr/hal-01315776
  • 7Y. Falcone, M. Jaber.

    Fully-automated Runtime Enforcement of Component-based Systems with Formal and Sound Recovery, in: Software Tools for Technology Transfer (STTT), February 2016.

    https://hal.inria.fr/hal-01262658
  • 8Y. Falcone, T. Jéron, H. Marchand, S. Pinisetty.

    Runtime Enforcement of Regular Timed Properties by Suppressing and Delaying Events, in: Science of Computer Programming, March 2016. [ DOI : 10.1016/j.scico.2016.02.008 ]

    https://hal.inria.fr/hal-01281727
  • 9P. H. Penna, M. Castro, H. C. Freitas, F. Broquedis, J.-F. Méhaut.

    Design methodology for workload-aware loop scheduling strategies based on genetic algorithm and simulation, in: Concurrency and Computation: Practice and Experience, 2016. [ DOI : 10.1002/cpe.3933 ]

    https://hal.archives-ouvertes.fr/hal-01354028
  • 10P. Ramos, V. Vargas, M. Baylac, F. Villa, S. Rey, J. A. Clemente, N.-E. Zergainoh, J.-F. Méhaut, R. Velazco.

    Evaluating the SEE sensitivity of a 45nm SOI Multi-core Processor due to 14 MeV Neutrons, in: IEEE Transactions on Nuclear Science, March 2016, vol. 63, no 4, pp. 2193 - 2200. [ DOI : 10.1109/TNS.2016.2537643 ]

    https://hal.archives-ouvertes.fr/hal-01280648
  • 11M. A. Souza, P. H. Penna, M. M. Queiroz, A. D. Pereira, L. F. W. Góes, H. C. Freitas, M. Castro, P. O. Navaux, J.-F. Méhaut.

    CAP Bench: a benchmark suite for performance and energy evaluation of low-power many-core processors, in: Concurrency and Computation: Practice and Experience, 2016. [ DOI : 10.1002/cpe.3892 ]

    https://hal.archives-ouvertes.fr/hal-01330543

Invited Conferences

  • 12C. Colombo, Y. Falcone.

    First International Summer School on Runtime Verification: as part of the ArVi COST Action 1402, in: Sixteenth International Conference on Runtime Verification, Madrid, Spain, September 2016.

    https://hal.inria.fr/hal-01428838
  • 13G. Reger, S. Hallé, Y. Falcone.

    Third International Competition on Runtime Verification CRV 2016, in: Sixteenth International Conference on Runtime Verification, Madrid, Spain, September 2016.

    https://hal.inria.fr/hal-01428834

International Conferences with Proceedings

  • 14W. Bao, K. Sriram, L.-N. Pouchet, F. Rastello, S. Ponnuswamy.

    PolyCheck: Dynamic Verification of Iteration Space Transformations on Affine Programs, in: Proceedings of the 43nd Annual ACM SIGPLAN-SIGACT Symposium on Principles of Programming Languages, POPL 2016, St Petersburg, United States, ACM, January 2016.

    https://hal.inria.fr/hal-01234104
  • 15A. El-Hokayem, Y. Falcone, M. Jaber.

    Modularizing Crosscutting Concerns in Component-Based Systems, in: 14th International Conference on Software Engineering and Formal Methods, Vienne, Austria, July 2016.

    https://hal.inria.fr/hal-01305083
  • 16F. Gindraud, F. Rastello, A. Cohen, F. Broquedis.

    A bounded memory allocator for software-defined global address spaces, in: ISMM 2016 - 2016 ACM SIGPLAN International Symposium on Memory Management, Santa Barbara, United States, June 2016.

    https://hal.inria.fr/hal-01412919
  • 17S. Hallé, R. Khoury, A. El-Hokayem, Y. Falcone.

    Decentralized Enforcement of Artifact Lifecycles, in: EDOC 2016, Vienne, Austria, Proceedings of the twentieth entreprise computing conference, September 2016.

    https://hal.inria.fr/hal-01365315
  • 18H. Nazarpour, Y. Falcone, S. Bensalem, M. Bozga, J. Combaz.

    Monitoring Multi-Threaded Component-Based Systems, in: 12th International Conference on integrated Formal Methods, Reykjavik, Finland, Proceedings of the 12th International Conference on integrated Formal Methods, June 2016.

    https://hal.inria.fr/hal-01285579
  • 19S. Pinisetty, V. Preoteasa, S. Tripakis, T. Jéron, Y. Falcone, H. Marchand.

    Predictive Runtime Enforcement *, in: SAC 2016 31st ACM Symposium on Applied Computing, Pisa, Italy, ACM, April 2016, 6 p. [ DOI : 10.1145/2851613.2851827 ]

    https://hal.inria.fr/hal-01244369
  • 20R. Samyam, K. Jinsung, K. Sriram, F. Rastello, L.-N. Pouchet, R. J. Harrison, S. Ponnuswamy.

    A domain-specific compiler for a parallel multiresolution adaptive numerical simulation environment, in: SC 2016 - International Conference for High Performance Computing, Networking, Storage and Analysis, Salt-Lake City, United States, November 2016.

    https://hal.inria.fr/hal-01412903
  • 21P. Silva, C. Pérez, F. Desprez.

    Efficient Heuristics for Placing Large-Scale Distributed Applications on Multiple Clouds, in: 16th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid'16), Cartagena, Colombia, 2016 16th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (CCGrid), May 2016. [ DOI : 10.1109/CCGrid.2016.77 ]

    https://hal.archives-ouvertes.fr/hal-01301382
  • 22P. Virouleau, F. Broquedis, T. Gautier, F. Rastello.

    Using data dependencies to improve task-based scheduling strategies on NUMA architectures, in: Euro-Par 2016, Grenoble, France, Euro-Par 2016, August 2016.

    https://hal.inria.fr/hal-01338761
  • 23P. Virouleau, A. Roussel, F. Broquedis, T. Gautier, F. Rastello, J.-M. Gratien.

    Description, Implementation and Evaluation of an Affinity Clause for Task Directives, in: IWOMP 2016, Nara, Japan, IWOMP 2016 - LLCS 9903, October 2016.

    https://hal.inria.fr/hal-01343442
  • 24N. Zhou, G. Delaval, B. Robu, E. Rutten, J.-F. Méhaut.

    Autonomic Parallelism and Thread Mapping Control on Software Transactional Memory , in: 13th IEEE International Conference on Autonomic Computing (ICAC 2016), Wuerzburg, Germany, July 2016, pp. 189 - 198. [ DOI : 10.1109/ICAC.2016.54 ]

    https://hal.archives-ouvertes.fr/hal-01309681
  • 25N. Zhou, G. Delaval, B. Robu, E. Rutten, J.-F. Méhaut.

    Control of Autonomic Parallelism Adaptation on Software Transactional Memory, in: International Conference on High Performance Computing & Simulation (HPCS 2016), Innsbruck, Austria, July 2016, pp. 180-187. [ DOI : 10.1109/HPCSim.2016.7568333 ]

    https://hal.archives-ouvertes.fr/hal-01309195
  • 26N. Zhou, G. Delaval, B. Robu, É. Rutten, J.-F. Méhaut.

    Autonomic Parallelism Adaptation for Software Transactional Memory, in: Conférence d’informatique en Parallélisme, Architecture et Système (COMPAS), Lorient, France, July 2016.

    https://hal.inria.fr/hal-01312786

National Conferences with Proceedings

  • 27R. Jakse, Y. Falcone, J.-F. Méhaut, K. Pouget.

    Vérification interactive de propriétés à l'exécution d'un programme avec un débogueur, in: Compas’2016, Lorient, France, Compas’2016 : Parallélisme / Architecture / Système Lorient, France, du 5 au 8 juillet 2016, July 2016.

    https://hal.inria.fr/hal-01331973

Conferences without Proceedings

  • 28Ł. Domagała, D. van Amstel, F. Rastello.

    Generalized cache tiling for dataflow programs, in: Conference on Languages, Compilers, Tools, and Theory for Embedded Systems, Santa Barbara, United States, Proceedings of the 17th ACM SIGPLAN/SIGBED Conference on Languages, Compilers, Tools, and Theory for Embedded Systems, June 2016, 10 p. [ DOI : 10.1145/2907950.2907960 ]

    https://hal.inria.fr/hal-01336172
  • 29C. Hong, W. Bao, A. Cohen, S. Krishnamoorthy, L.-N. Pouchet, F. Rastello, J. Ramanujam, S. Ponnuswany.

    Effective padding of multidimensional arrays to avoid cache conflict misses, in: PLDI 2016: Proceedings of the 37th ACM SIGPLAN Conference on Programming Language Design and Implementation, Santa Barbara, United States, June 2016.

    https://hal.inria.fr/hal-01335346
  • 30K. Pouget, M. Santana, J.-F. Méhaut.

    Programming-Model Centric Debugging for OpenMP, in: 2nd OpenMPCon Developpers Conference, Nara, Japan, October 2016.

    https://hal.archives-ouvertes.fr/hal-01351561
  • 31N. Rajovic, A. Rico, F. Mantovani, D. Ruiz, J. Vilarrubi, C. Gomez, D. Nieto, H. Servat, X. Martorell, J. Labarta, C. Adeniyi-Jones, S. Derradji, H. Gloaguen, P. Lanucara, N. Sanna, J.-F. Méhaut, K. Pouget, B. Videau, E. Boyer, M. Allalen, A. Auweter, D. Brayford, D. Tafani, V. Weinberg, D. Brömmel, R. Halver, J. Meinke, R. Beivide, M. Benito, E. Vallejo, M. Valero, A. Ramirez.

    The Mont-Blanc prototype: An Alternative Approach for HPC Systems, in: International Conference for High Performance Computing, Networking, Storage and Analysis (SC), Salt Lake City, United States, November 2016.

    https://hal.archives-ouvertes.fr/hal-01354939
  • 32R. Samyam, K. Jinsung, S. Krishnamoorthy, L.-N. Pouchet, F. Rastello, R. J. Harrison, S. Ponnuswany.

    On fusing recursive traversals of K-d trees, in: Proceedings of the 25th International Conference on Compiler Construction, CC 2016, Barcelona, Spain, March 2016.

    https://hal.inria.fr/hal-01335355
  • 33P. Virouleau.

    Amélioration des stratégies d'ordonnancement sur architectures NUMA à l'aidedes dépendances de données, in: Compas 2016, Lorient, France, July 2016.

    https://hal.inria.fr/hal-01338750

Scientific Books (or Scientific Book chapters)

  • 34L. Genovese, B. Videau, D. Caliste, J.-F. Méhaut, S. Goedecker, T. Deutsch.

    Wavelet-Based Density Functional Theory on Massively Parallel Hybrid Architectures, in: Electronic Structure Calculations on Graphics Processing Units: From Quantum Chemistry to Condensed Matter Physics, R. Walker (editor), Wiley-Blackwell, February 2016.

    https://hal.archives-ouvertes.fr/hal-01239245

Internal Reports

  • 35C. Alias, F. Rastello, A. Plesco.

    High-Level Synthesis of Pipelined FSM from Loop Nests, Inria, April 2016, no 8900, 18 p.

    https://hal.inria.fr/hal-01301334
  • 36N. Zhou, G. Delaval, B. Robu, É. Rutten, J.-F. Méhaut.

    Autonomic Parallelism Adaptation on Software Transactional Memory, Univ. Grenoble Alpes ; Inria Grenoble, March 2016, no RR-8887, 24 p.

    https://hal.inria.fr/hal-01279599

Other Publications