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Section: Highlights of the Year

Highlights of the Year

André Seznec was elevated as an ACM Fellow in December 2016 with the citation: “For contributions to branch prediction and cache memory design”.

André Seznec won the three tracks of the 5th Championship on Branch Prediction.

Awards

Sajith Kalathingal, Sylvain Collange, Bharath Swamy and André Seznec received the Best Paper award of the SBAC-PAD 2016 conference.

Damien Hardy, Isabelle Puaut, Yiannakis Sazeides won the best paper award of the Embedded Systems Software track at DATE 2016: Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults. Design, Automation and Test in Europe. Dresden, Germany, March 2016.

Aswinkumar Sridharan and André Seznec won the best paper award for “Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores” at the 30th IEEE International Parallel & Distributed Processing Symposium, May 2016, Chicago.

For his PhD thesis [10] “Increasing the Performance of Superscalar Processors through Value Prediction”, Arthur Perais received:

  • Prix de thèse Fondation Rennes 1, 1er Prix de l'école doctorale MATISSE;

  • Prix de thèse Gilles Kahn, accessit.

Best Papers Awards:
[46]
A. Seznec.

TAGE-SC-L Branch Predictors Again, in: 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5), Seoul, South Korea, June 2016.

https://hal.inria.fr/hal-01354253


[45]
A. Seznec.

Exploring branch predictability limits with the MTAGE+SC predictor *, in: 5th JILP Workshop on Computer Architecture Competitions (JWAC-5): Championship Branch Prediction (CBP-5), Seoul, South Korea, June 2016, 4 p.

https://hal.inria.fr/hal-01354251


[36]
S. Kalathingal, S. Collange, B. Narasimha Swamy, A. Seznec.

Dynamic Inter-Thread Vectorization Architecture: extracting DLP from TLP, in: International Symposium on Computer Architecture and High-Performance Computing (SBAC-PAD), Los Angeles, United States, October 2016.

https://hal.inria.fr/hal-01356202


[35]
D. Hardy, I. Puaut, Y. Sazeides.

Probabilistic WCET estimation in presence of hardware for mitigating the impact of permanent faults, in: Design, Automation and Test in Europe, Dresden, Germany, March 2016.

https://hal.inria.fr/hal-01259493


[48]
A. Sridharan, A. Seznec.

Discrete Cache Insertion Policies for Shared Last Level Cache Management on Large Multicores, in: 30th IEEE International Parallel & Distributed Processing Symposium, Chicago, United States, May 2016.

https://hal.inria.fr/hal-01259626