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Section: New Software and Platforms

FloPoCo

Floating-Point Cores, but not only

Keyword: Synthesizable VHDL generator

Functional Description: The purpose of the open-source FloPoCo project is to explore the many ways in which the flexibility of the FPGA target can be exploited in the arithmetic realm.

  • Participants: Antoine Martinet, Florent Dupont De Dinechin, Matei Istoan and Nicolas Brunie

  • Partners: CNRS - ENS Lyon - UCBL Lyon 1 - UPVD

  • Contact: Florent Dupont De Dinechin

  • URL: http://flopoco.gforge.inria.fr/