Section: New Results

Co-Modeling for HP-SoC with MARTE

Diagonal mesh modeling with MARTE

As a continuation of this work on modeling at system level, a methodology for modeling concepts of NoC-based architectures is proposed especially the modeling of all kinds of topologies (regular, irregular or hierarchical) and routing algorithms . This contribution includes a VHDL code generation. On the other side we proposed a VLSI implementation of a new NoC topology called diagonal mesh that it designed to offer a good tradeoff between hardware cost and theoretical quality of service (QoS). This NoC is based on a new router architecture called FeRoNoC (Flexible, extensible Router NoC).

MARTE extension for reconfigurable hardware models

Reconfigurable System-on-Chip (RSoC), mainly FPGAs, offer several advantages such as flexibility, adaptivity and especially their capability to allow switching several implementations at run-time, i.e., PDR.

PDR feature requires multiple run-time changes in RSoC such as:

- QoS factors: changes in executing functionalities due to designer requirements, or changes due to resource constraints of targeted hardware/platforms.

- The changes can also take place due to other environmental criteria such as communication quality, time and area consumed for reconfiguration and energy consumption.

In previous work [86] , we provided an initial contribution to the modeling of these systems by extending UML MARTE profile to incorporate significant design criteria such as power consumption. Furthermore, high flexibility of RSoC implies high design complexity of the control of such system. This makes designing a robust control for managing reconfiguration a studious task. In [25] , we present a high level design approach using UML MARTE for modeling dynamic reconfiguration controllers. Our proposed controller is based on distributed monitoring of runtime changes and distributed decision making. Our approach allows to increase flexibility and design reusability compared to centralized solution.

Indeed, in its current version, UML MARTE profile lacks dynamic reconfiguration concepts and requirements for the reconfiguration control mechanism. Even these later are necessary to model and implement rapid prototypes for complex systems. We can only model a state machine at high abstraction levels which is responsible for switching between the available configurations.

So we define a new design methodology using the proposed version of RecoMARTE (extended MARTE) to model PDR concepts at different abstraction levels, mainly architecture (structural and physical models) and allocation (software to Hardware allocation (Sw/Hw Allocate) and Hardware to Hardware allocation (Hw/Hw Allocate)). We also define necessary requirements for the reconfiguration control mechanism in order to manage reconfiguration at every design level. In addition, our solution allows to describe global contracts and constraints for combining automata. As future works, we plan to carry out model transformations to enable automatic code generation of configuration files. The code can then be used as input for commercial tools for final FPGA synthesis.

Comparaison of SAC and ArrayOL for parallelism expression

In this join work with the University of Hertfordshire, we compare and analyse two such schemes. One of them is a domain-specific language, ArrayOL, to OpenCL. The other one is a transformation mechanism for mapping a image/signal processing transformation route for mapping a high-level general purpose array processing language, Single Assignment C (SaC) to CUDA. Using a real-world image processing application as a running example, we demonstrate that albeit the fact of being general purpose, the array processing language be used to specify complex array access patterns generically. Performance of the generated CUDA code is comparable to the OpenCL code created from domain-specific language.

Gaspard Modeling Improvements

Gaspard2 is the IDE proposed by the DaRT team. Its usage can be painful for beginners as well as for experts. We try to improve the usage of Gaspard in different ways:

  • By allowing modifications at any model level, and let propagate the modifications to the higher and lower models (Amen Souissi).

  • By providing missing diagrams in Papyrus (Amine El Kouen) By customizing the Gaspard User Interface (UI). Modeling in Gaspard is done with the Papyrus Modeler. We participate to the Papyrus development, which allow us to propose some customization tools. These laters, are used to provide a modeling UI more adapted to embedded system co-modeling. This work is done by Rahma Yangui (INRIA engineer).

  • By allowing to adapt dynamically the UML modeler environment according to the steps of the modeling process ( Amine El Kouen's thesis). This allows to guide the user in its development process, and to propose a simplified UI, oriented to the current development step.

Also, we have migrated from Papyrus I to Papyrus Eclipse.