Section: Partnerships and Cooperations

European Initiatives

HiPEAC network of excellence

HiPEAC is a network of excellence on High-Performance Embedded Architectures and Compilers. It was first established as an FP6 network in 2004, and renewed as an FP7 4 years later. INRIA is one of the partners of the network. Albert Cohen leads the Compiler Platform cluster (9 research clusters in total). 02/2008–01/2012.

TERAFLUX integrated project

The TERAFLUX project is funded under the FP7 FET pro-active program on teradevice computing, 01/2010-12/2013. Albert Cohen is responsible for WP4. Our work addresses data-flow synchronous parallel programming, polyhedral compilation for data-flow programs, and compiler support for data-driven multi-threaded architectures with hundreds of computing cores. We contribute compilation algorithms and experimental language designs, with prototypes based on Lucid Synchrone and direct contributions to GCC through the design of data-flow synchronous extensions of OpenMP. One of our goals is to transfer results of the project to production tools, including GCC and simulation platforms for many-core processors. A standardization effort (supported by INRIA's D2T) aims for the adoption of the language extensions by the OpenMP Architecture Review Board.

PHARAON specific targeted research project

The PHARAON project is funded on the embedded systems strategic objective, 09/2011–08/2014. Albert Cohen is responsible for WP5. Our work addresses data-flow synchronous programming for multiprocessor systems-on-chip, with an emphasis on an embedded development methodology and tools to optimize energy consumption and facilitate the correct-by-construction refinement of a functional specification. The Heptagon and Streaming OpenMP platforms of the team are used in the project. PHARAON is led by Thales Communications and Security.

CARP specific targeted research project

The CARP project is funded on the computing systems strategic objective, 12/2011–11/2014. Our work addresses polyhedral automatic parallelization for vector accelerators, with an emphasis on extending the scope of polyhedral compilation and integrating vectorization and specialization techniques. isl is an important component of this work, along with a new source-to-source compilation framework being developed in the project. CARP is led by Imperial College, and our team collaborates closely with ARM Cambridge in the specification of a portable parallel intermediate language to facilitate automatic parallelization and vectorization.

Collaborations in European Programs, except FP7

Euro-TM COST action

This new action started in April 2011. It aims at consolidating European research on transactional memory, by coordinating the research groups working on the development of complementary, interdisciplinary aspects of Transactional Memories, including theoretical foundations, algorithms, hardware and operating system support, language integration and development tools, and applications. Our participation is focused on the interaction between data-flow and transactional memory models.