Section: Software and Platforms

IceGEN

Participants : Christophe Alias, Alexandru Plesco [Compsys/Zettice] .

IceGEN (Integrated Circuit Generator) is the back-end of the HLS tool transferred to the start-up Zettice (see Section  7.3 ). IceGEN takes as input the DPN produced by Dcc (see Section  5.8 ) and generates:

• a SystemC description relevant for fast and accurate circuit simulation.

• a VHDL description of the circuit, which can be mapped efficiently to an FPGA.

IceGEN makes an extensive use of the pipelined arithmetic operators of the tool FloPoCo  [18] developed by Florent De Dinechin, formerly from Inria ARIC team.

IceGEN represents more than 6000 lines of C++ code.