Bibliography

Major publications by the team in recent years

• 1L. Besnard, T. Gautier, P. Le Guernic, C. Guy, J.-P. Talpin, B. Larson, E. Borde.
  
  Formal Semantics of Behavior Specifications in the Architecture Analysis and Design Language Standard, in: Cyber-Physical System Design from an Architecture Analysis Viewpoint, Cyber-Physical System Design from an Architecture Analysis Viewpoint, Springer, January 2017. [ DOI : 10.1007/978-981-10-4436-6_3 ]
  
  https://hal.inria.fr/hal-01615143
• 2L. Besnard, T. Gautier, P. Le Guernic, J.-P. Talpin.
  
  Compilation of Polychronous Data Flow Equations, in: Synthesis of Embedded Software, S. K. Shukla, J.-P. Talpin (editors), Springer, 2010, pp. 1-40. [ DOI : 10.1007/978-1-4419-6400-7_1 ]
  
  http://hal.inria.fr/inria-00540493
• 3A. Bouakaz, J.-P. Talpin.
  
  Design of Safety-Critical Java Level 1 Applications Using Affine Abstract Clocks, in: International Workshop on Software and Compilers for Embedded Systems, St. Goar, Germany, June 2013, pp. 58-67. [ DOI : 10.1145/2463596.2463600 ]
  
  https://hal.inria.fr/hal-00916487
• 4A. Gamatié, T. Gautier, P. Le Guernic.
  
  Synchronous design of avionic applications based on model refinements, in: Journal of Embedded Computing (IOS Press), 2006, vol. 2, n^o 3-4, pp. 273-289.
  
  http://hal.archives-ouvertes.fr/hal-00541523
• 5A. Honorat, H. N. Tran, L. Besnard, T. Gautier, J.-P. Talpin, A. Bouakaz.
  
  ADFG: a scheduling synthesis tool for dataflow graphs in real-time systems, in: International Conference on Real-Time Networks and Systems, Grenoble, France, October 2017, pp. 1-10. [ DOI : 10.1145/3139258.3139267 ]
  
  https://hal.inria.fr/hal-01615142
• 6S. Lunel, B. Boyer, J.-P. Talpin.
  
  Compositional proofs in differential dynamic logic dL, in: 17th International Conference on Application of Concurrency to System Design, Zaragoza, Spain, June 2017.
  
  https://hal.inria.fr/hal-01615140
• 7S. Nakajima, J.-P. Talpin, M. Toyoshima, H. Yu.
  
  Cyber-Physical System Design from an Architecture Analysis Viewpoint, Communications of NII Shonan Meetings, Springer, January 2017. [ DOI : 10.1007/978-981-10-4436-6 ]
  
  https://hal.inria.fr/hal-01615144
• 8D. Potop-Butucaru, Y. Sorel, R. de Simone, J.-P. Talpin.
  
  From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations, in: Fundamenta Informaticae, January 2011, vol. 108, n^o 1-2, pp. 91–118.
  
  http://dl.acm.org/citation.cfm?id=2362088.2362094
• 9O. Sankur, J.-P. Talpin.
  
  An Abstraction Technique For Parameterized Model Checking of Leader Election Protocols: Application to FTSP, in: 23rd International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS), Uppsala, Sweden, Lecture Notes in Computer Science, April 2017, vol. 10206.
  
  https://hal.archives-ouvertes.fr/hal-01431472
• 10H. Yu, J. Prashi, J.-P. Talpin, S. K. Shukla, S. Shiraishi.
  
  Model-Based Integration for Automotive Control Software, in: Digital Automation Conference, San Francisco, United States, ACM, June 2015.
  
  https://hal.inria.fr/hal-01148905

Publications of the year

Articles in International Peer-Reviewed Journals

• 11P. Derler, K. Schneider, J.-P. Talpin.
  
  Guest Editorial: Special Issue of ACM TECS on the ACM-IEEE International Conference on Formal Methods and Models for System Design (MEMOCODE 2017), in: ACM Transactions on Embedded Computing Systems (TECS), November 2018, pp. 1-2.
  
  https://hal.inria.fr/hal-01926923
• 12T. Gautier, C. Guy, A. Honorat, P. Le Guernic, J.-P. Talpin, L. Besnard.
  
  Polychronous Automata and their Use for Formal Validation of AADL Models, in: Frontiers of Computer Science, 2018. [ DOI : 10.1007/s11704-017-6134-5 ]
  
  https://hal.inria.fr/hal-01411257

Invited Conferences

• 13J.-P. Talpin.
  
  Refinement types for system design (abstract), in: Forum on specification and Design Languages, Munich, Germany, September 2018.
  
  https://hal.inria.fr/hal-01926978

International Conferences with Proceedings

• 14H. N. Tran, S. S. Bhattacharyya, J.-P. Talpin, T. Gautier.
  
  Toward Efficient Many-core Scheduling of Partial Expansion Graphs, in: SCOPES 2018 - 21st International Workshop on Software and Compilers for Embedded Systems, Saint Goar, Germany, May 2018, vol. 4, pp. 1-4. [ DOI : 10.1145/3207719.3207734 ]
  
  https://hal.inria.fr/hal-01926955

Other Publications

• 15A. Benveniste, T. Gautier.
  
  The Signal synchronous language: the principles beyond the language and how to exploit and extend them, March 2018, pp. 1-68, Lecture.
  
  https://hal.archives-ouvertes.fr/hal-01929567