2025Activity‌ reportProject-TeamTARAN

Moore’s Law​​ is Running Out of​​​‌ Steam

: The limits​ of traditional transistor process​‌ technology have been known​​ for a long time.​​​‌ We are now approaching​ these limits while alternative​‌ technologies are still in​​ early stages of development.​​​‌ The economical drive for​ more performance will persist,​‌ and we expect a​​ surge in specialized architectures​​​‌ in the mid-term to​ squeeze performance out of​‌ CMOS technology. Use of​​ Non-Volatile Memory (NVM), Processing-in-Memory​​​‌ (PIM), and various work​ on approximate computing are​‌ all examples of such​​ architectures.

Specialization is the​​​‌ Common Denominator

: Specialization,​ which has been a​‌ small niche in the​​ past, is now widespread​​​‌ 80. The main​ driver today is energy​‌ efficiency—small embedded devices need​​ specialized hardware to operate​​​‌ under power/energy constraints. In​ the next ten years,​‌ we expect specializations to​​ become even more common​​ to meet increasing demands​​​‌ for performance. In particular,‌ high-throughput workloads traditionally run‌​‌ on servers (e.g., computational​​ science and machine learning)​​​‌ will offload (parts of)‌ their computations to accelerators.‌​‌ We are already seeing​​ some instances of such​​​‌ specialization, most notably accelerators‌ for neural networks that‌​‌ use clusters of nodes​​ equipped with FPGAs and/or​​​‌ ASICs.

The Need for‌ Abstractions

: The main‌​‌ drawback of hardware specialization​​ is that it comes​​​‌ with significant costs in‌ terms of productivity. Although‌​‌ High-Level Synthesis tools have​​ been steadily improving, design​​​‌ and implementation of custom‌ hardware (HW) are still‌​‌ time consuming tasks that​​ require significant expertise. As​​​‌ specializations become inevitable, we‌ need to provide programmers‌​‌ with tools to develop​​ specialized accelerators and explore​​​‌ their large design spaces.‌ Raising the level of‌​‌ abstraction is a promising​​ way to improve productivity,​​​‌ but also introduces additional‌ challenges to maintain the‌​‌ same levels of performance​​ as manually specified counterparts.​​​‌ Taking advantage of domain‌ knowledge to better automate‌​‌ the design flow from​​ higher level specifications to​​​‌ efficient implementations is necessary‌ for making specialized accelerators‌​‌ accessible.

Language/Programming Model

:​​​‌ This is the main‌ interface to the programmer‌​‌ that has two (sometimes​​ conflicting) goals. One is​​​‌ that the programmer should‌ be able to concisely‌​‌ specify the computation. The​​ other is that the​​​‌ domain knowledge of the‌ programmer must also be‌​‌ expressed such that the​​ other layers can utilize​​​‌ it.

Compiler

: The‌ compiler is an important‌​‌ component for both productivity​​ and performance. It improves​​​‌ productivity by allowing the‌ input language to be‌​‌ more concise by recovering​​ necessary information through compiler​​​‌ analysis. It is also‌ where the first set‌​‌ of analyses and transformations​​ are performed to realize​​​‌ efficient custom hardware.

Runtime‌

: Runtime complements adjacent‌​‌ layers with its dynamicity.​​ It has access to​​​‌ more concrete information about‌ the input data that‌​‌ static analyses cannot use.​​ It is also responsible​​​‌ for coordinating various processing‌ elements, especially in heterogeneous‌​‌ settings.

Hardware Design

:​​ There are many design​​​‌ knobs when building an‌ accelerator: the amount/type of‌​‌ parallelism, communication and on-chip​​ storage, number representation and​​​‌ computer arithmetic, and so‌ on. The key challenge‌​‌ is in navigating through​​ this design space with​​​‌ the help of domain‌ knowledge passed through the‌​‌ preceding layers.

Emerging Technology​​

: Use of non-conventional​​​‌ hardware components (e.g., NVM‌ or optical interconnects) opens‌​‌ further avenues to explore​​ specialized designs. For a​​​‌ domain where such emerging‌ technologies make sense, this‌​‌ knowledge should also be​​ taken into account when​​​‌ designing the HW.

Key Investigators:

A.​‌ Chillet, D. Chillet, A.​​ Kritikakou, B. Le Gal,​​​‌ N. Leroux, P. Quinton,​ S. Rokicki, O. Sentieys.​‌

Accelerators are custom hardware​​ that primarily aim to​​​‌ provide high-throughput, energy-efficient, computing​ platforms. Custom hardware can​‌ give much better performance​​ compared to more general​​​‌ architectures simply because they​ are specialized, at the​‌ price of being much​​ harder to “program.” Accelerator​​​‌ designers need to explore​ a massive design space,​‌ which includes many hardware​​ parameters that a software​​​‌ programmer has no control​ over, to find a​‌ suitable design for the​​ application at hand.

Our​​​‌ first objective in this​ context is to further​‌ enlarge the design space​​ and enhance the performance​​ of accelerators. The second,​​​‌ equally important, objective is‌ to provide the designers‌​‌ with the means to​​ efficiently navigate through the​​​‌ ever-expanding design space. Cross-layer‌ expertise is crucial in‌​‌ achieving these goals—we need​​ to fully utilize available​​​‌ domain knowledge to improve‌ both the productivity and‌​‌ the performance of custom​​ hardware design.

Positioning:

Hardware​​​‌ acceleration has already proved‌ its efficiency in many‌​‌ datacenter, cloud-computing or embedded​​ high-performance computing (HPC) applications:​​​‌ machine learning, web search,‌ data mining, database access,‌​‌ information security, cryptography, financial,​​ image/signal/video processing, etc. For​​​‌ example, the work at‌ Microsoft in accelerating the‌​‌ Bing web search engine​​ with large-scale reconfigurable fabrics​​​‌ has shown to improve‌ the ranking throughput of‌​‌ each server by 95%​​ 89, and the​​​‌ increasing need for acceleration‌ of deep learning workloads‌​‌ 92.

Hardware accelerators​​ still lack efficient and​​​‌ standardized compilation toolflows, which‌ makes the technology impractical‌​‌ for large-scale use. Generating​​ and optimizing hardware from​​​‌ high-level specifications is a‌ key research area with‌​‌ considerable interest 81,​​ 87. On this​​​‌ topic, we have been‌ pursuing our efforts to‌​‌ propose tools whose design​​ principles are based on​​​‌ a tight coupling between‌ the compiler and the‌​‌ target hardware architectures.

Key Investigators:​​​‌

S. Filip, O. Sentieys,‌ M. Traiola.

An important‌​‌ design knob in accelerators​​ is the number representation—digital​​​‌ computing is by nature‌ some approximation of real‌​‌ world behavior. Appropriately selecting​​ the number representation that​​​‌ respects a given quality‌ requirement has been a‌​‌ topic of study for​​ many decades in signal/image​​​‌ processing: a process known‌ as Word-Length Optimization (WLO).‌​‌ We are now seeing​​ the scope of number​​​‌ format-centered approximations widen beyond‌ these traditional applications. This‌​‌ gives us many more​​ approximation opportunities to take​​​‌ advantage of, but introduces‌ additional challenges as well.‌​‌

Earlier work on arithmetic​​ optimizations has primarily focused​​​‌ on low-level representations of‌ the computation (i.e., signal-flow‌​‌ graphs) that do not​​ scale to large applications.​​​‌ Working on higher level‌ abstractions of the computation‌​‌ is a promising approach​​ to improve scalability and​​​‌ to explore high-level transformations‌ that affect accuracy. Moreover,‌​‌ the acceptable degree of​​ approximation is decided by​​​‌ the programmer using domain‌ knowledge, which needs to‌​‌ be efficiently utilized.

Positioning:​​

Traditionally, fixed-point (FxP) arithmetic​​​‌ is used to relax‌ accuracy, providing important benefits‌​‌ in terms of delay,​​ power and area 19​​​‌. There is also‌ a large body of‌​‌ work on carefully designing​​ efficient arithmetic operators/functions that​​​‌ preserve good numerical properties.‌ Such numerical precision tuning‌​‌ leads to a massive​​ design space, necessitating the​​​‌ development of efficient and‌ automatic exploration methods.

The‌​‌ need for further improvements​​ in energy efficiency has​​​‌ led to renewed interest‌ in approximation techniques in‌​‌ the recent years 88​​. This field has​​​‌ emerged in the last‌ years, and is very‌​‌ active recently with deep​​ learning as its main​​​‌ driver. Many applications have‌ modest numerical accuracy requirements,‌​‌ allowing for the introduction​​ of approximations in their​​​‌ computations 82.

Key Investigators:‌​‌

D. Chillet, F. Fernandes​​​‌ dos Santos, A. Kritikakou,​ O. Sentieys, M. Traiola.​‌

With advanced technology nodes​​ and the emergence of​​​‌ new devices pressured by​ the end of Moore's​‌ law, manufacturing problems and​​ process variations strongly influence​​​‌ electrical parameters of circuits​ and architectures 86,​‌ leading to dramatically reduced​​ yield rates 90.​​​‌ Transient errors caused by​ particles or radiations will​‌ also more and more​​ often occur during execution​​​‌ 93, 91,​ and process variability will​‌ prevent predicting chip performance​​ (e.g., frequency, power, leakage)​​​‌ without a self-characterization at​ run time. On the​‌ other hand, many systems​​ are under constant attacks​​​‌ from intruders and security​ has become of utmost​‌ importance.

In this research​​ direction, we will explore​​​‌ techniques to protect architectures​ against faults, errors, and​‌ attacks, which have not​​ only a low overhead​​​‌ in terms of area,​ performance, and energy 23​‌, 22, 16​​, but also a​​​‌ significant impact on improving​ the resilience of the​‌ architecture under consideration. Such​​ protections require to act​​​‌ at most layers of​ the design stack.

Key​​ Investigators:

D. Chillet, N.​​​‌ Leroux, O. Sentieys, M.​ Traiola.

Domain specific accelerators​‌ have more exploratory freedom​​ to take advantage of​​​‌ non-conventional technologies that are​ too specialized for general​‌ purpose use. Examples of​​ such technologies include optical​​​‌ interconnects for Network-on-Chip (NoC)​ and Non-Volatile Memory (NVM)​‌ for low-power sensor nodes.​​ The objective of this​​​‌ research direction is to​ explore the use of​‌ such technologies, and find​​ appropriate application domains. The​​​‌ primary cross-layer interaction is​ expected from Hardware Design​‌ to accommodate non-conventional Technologies.​​ However, this research direction​​​‌ may also involve Runtime​ and Compilers.

5.1.1 Gecos

• Name:
  Generic‌ Compiler Suite
• Keywords:
  Source-to-source‌​‌ compiler, Model-driven software engineering,​​ Retargetable compilation
• Scientific Description:​​​‌
  The Gecos (Generic Compiler‌ Suite) project is a‌​‌ source-to-source compiler infrastructure targeted​​ at program transformations mainly​​​‌ for High-Level-Synthesis tools. Gecos‌ uses the Eclipse Modeling‌​‌ Framework (EMF) as an​​ underlying infrastructure. Gecos is​​​‌ open-source and is hosted‌ on the Inria gitlab.‌​‌ The Gecos infrastructure is​​ still under very active​​​‌ development and serves as‌ a backbone infrastructure to‌​‌ several research projects of​​ the group.
• Functional Description:​​​‌
  GeCoS provides a programme‌ transformation toolbox facilitating parallelisation‌​‌ of applications for heterogeneous​​ multiprocessor embedded platforms. In​​​‌ addition to targeting programmable‌ processors, GeCoS can regenerate‌​‌ optimised code for High​​ Level Synthesis tools.
• News​​​‌ of the Year:
  With‌ the recent work on‌​‌ the Speculative HLS project​​ and the new ANR​​​‌ LOTR, we have extended‌ the tool to integrate‌​‌ some new analysis and​​ transformation based on the​​​‌ Circt project (https://circt.llvm.org‌). We are also‌​‌ moving toward generating verilog​​ for a subset of​​​‌ input C code. The‌ objective is to be‌​‌ able to generate hardware​​ with a fully open-source​​​‌ toolchain.
• URL:
  https://­gitlab.­inria.­fr/­gecos
• Publication:‌
  hal-03714101
• Contact:
  Simon Rokicki‌​‌
• Participants:
  Simon Rokicki, Dylan​​ Leothaud, Jean-Michel Gorius, Steven​​​‌ Derrien
• Partner:
  ENS Rennes‌

5.1.2 SmartSense

• Name:
  Sensor-Aided‌​‌ Non-Intrusive Load Monitoring
• Keywords:​​
  Wireless Sensor Networks, Smart​​​‌ building, Non-Intrusive Appliance Load‌ Monitoring
• Functional Description:
  To‌​‌ measure energy consumption by​​ equipment in a building,​​​‌ NILM techniques (Non-Intrusive Appliance‌ Load Monitoring) are based‌​‌ on observation of overall​​ variations in electrical voltage.​​​‌ This avoids having to‌ deploy watt-meters on every‌​‌ device and thus reduces​​ the cost. SmartSense goes​​​‌ a step further to‌ improve on these techniques‌​‌ by combining sensors (light,​​ temperature, electromagnetic wave, vibration​​​‌ and sound sensors, etc.)‌ to provide additional information‌​‌ on the activity of​​ equipment and people. Low-cost​​​‌ sensors can be energy-autonomous‌ too.
• URL:
  https://­smartsense.­inria.­fr/
• Contact:‌​‌
  Olivier Sentieys
• Participants:
  Olivier​​ Sentieys, Guillermo Enrique Andrade​​​‌ Barroso, Mickael Le Gentil‌

5.1.3 TypEx

• Name:
  Type‌​‌ Exploration Tool
• Keywords:
  Embedded​​ systems, Fixed-point arithmetic, Floating-point,​​​‌ Low power consumption, Energy‌ efficiency, FPGA, ASIC, Accuracy‌​‌ optimization, Automatic floating-point to​​ fixed-point conversion
• Scientific Description:​​​‌
  The main goal of‌ TypEx is to explore‌​‌ the design space spanned​​ by possible number formats​​​‌ in the context of‌ High-Level Synthesis. TypEx takes‌​‌ a C code written​​ using floating-point datatypes specifying​​​‌ the application to be‌ explored. The tool also‌​‌ takes as inputs a​​ cost model as well​​​‌ as some user constraints‌ and generates a C‌​‌ code where the floating-point​​​‌ datatypes are replaced by​ the wordlengths found after​‌ exploration. The best set​​ of wordlengths is the​​​‌ one found by the​ tool that respects the​‌ accuracy constraint given and​​ that minimizes a parametrized​​​‌ cost function.
• Functional Description:​
  TypEx is a tool​‌ designed to automatically determine​​ custom number representations and​​​‌ word-lengths (i.e., bit-width) for​ FPGAs and ASIC designs​‌ at the C source​​ level. TypEx is available​​​‌ open-source at https://gitlab.inria.fr/gecos/gecos-float2fix. See​ README.md for detailed instructions​‌ on how to install​​ the software.
• URL:
  https://­gitlab.­inria.­fr/­gecos/­gecos-float2fix​​​‌
• Contact:
  Olivier Sentieys
• Participant:​
  Olivier Sentieys

5.2.1 MPTorch: a​​ PyTorch-based framework for simulating​​​‌ custom precision DNN training​

Participants: Silviu-Ioan Filip.​‌

Keywords: Computer architecture,​​ Arithmetic, Custom Floating-point, Deep​​​‌ learning, Multiple-Precision

Scientific description:​ MPTorch is a wrapper​‌ framework built atop PyTorch​​ that is designed to​​​‌ simulate the use of​ custom/mixed precision arithmetic in​‌ PyTorch, especially for DNN​​ training.

Functional description: MPTorch​​​‌ reimplements the underlying computations​ of commonly used layers​‌ for CNNs (e.g. matrix​​ multiplication and 2D convolutions)​​​‌ using user-specified floating-point formats​ for each operation (e.g.​‌ addition, multiplication). All the​​ operations are internally done​​​‌ using IEEE-754 32-bit floating-point​ arithmetic, with the results​‌ rounded to the specified​​ format.

• Contact: Silviu-Ioan Filip​​​‌
• URL: MPTorch on github​

5.2.2 Hybrid-DBT

Participants: Simon​‌ Rokicki, Louis Savary​​.

Keywords: Dynamic​​​‌ Binary Translation, hardware acceleration,​ VLIW processor, RISC-V

Scientific​‌ description: Hybrid-DBT is a​​ hardware/software Dynamic Binary Translation​​​‌ (DBT) framework capable of​ translating RISC-V binaries into​‌ VLIW binaries. Since the​​ DBT overhead has to​​​‌ be as small as​ possible, our implementation takes​‌ advantage of hardware acceleration​​ for performance critical stages​​​‌ (binary translation, dependency analysis​ and instruction scheduling) of​‌ the flow. Thanks to​​ hardware acceleration, our implementation​​​‌ is two orders of​ magnitude faster than a​‌ pure software implementation and​​ enables an overall performance​​​‌ increase of 23% on​ average, compared to a​‌ native RISC-V execution.

• Contact:​​ Simon Rokicki
• Partners: Univ​​​‌ Rennes
• URL: HybridDBT on​ github

5.2.3 Comet

Participants:​‌ Simon Rokicki, Olivier​​ Sentieys, Joseph Paturel​​​‌.

Keywords: Processor​ core, RISC-V instruction-set architecture​‌

Scientific description: Comet is​​ a RISC-V pipelined processor​​​‌ with data/instruction caches, fully​ developed using High-Level Synthesis.​‌ The behavior of the​​ core is defined in​​​‌ a small C++ code​ which is then fed​‌ into a HLS tool​​ to generate the RTL​​​‌ representation. Thanks to this​ design flow, the C++​‌ description can be used​​ as a fast and​​​‌ cycle-accurate simulator, which behaves​ exactly like the final​‌ hardware. Moreover, modifications in​​ the core can be​​​‌ done easily at the​ C++ level.

Comet is​‌ still in active development.​​ Our roadmap includes 64-bit​​​‌ version, Linux compatible, support​ for vector ISA extension,​‌ out-of-order superscalar microarchitecture. Comet​​ is used in many​​​‌ ongoing research projects (PEPR​ Arsene, Cyberpros, Foch, CocoRISCo​‌ Inria Challenge, EuroHPC DARE​​ (Digital Autonomy with RISC-V​​​‌ in Europe)) and is​ used as support to​‌ several PhD theses.

• Contact:​​ Simon Rokicki
• Partners: Univ​​​‌ Rennes
• URL: Comet on​ gitlab

5.2.4 MMAlpha

Participants:​‌ Patrice Quinton.

Keywords​​: High-level synthesis, polyhedral​​ model

Scientific description:MMAlpha​​​‌ is a software for‌ the high-level synthesis of‌​‌ parallel architectures from high-level​​ specifications written using the​​​‌ Alpha language. Developed over‌ years, it is currently‌​‌ able to generate automatically​​ synthesizable Vhdl programs for​​​‌ various examples. MMAlpha was‌ recently used to generate‌​‌ Vhdl code for the​​ simulation of electrical circuits.​​​‌

• Contact: Patrice Quinton
• Partners:‌ Univ Rennes
• URL: none‌​‌

7.1.1​​​‌ HLS-based hardware acceleration

Participants:​ Olivier Sentieys, Joseph​‌ Paturel, Cédric Killian​​, Daniel Chillet.​​​‌

Contract with Orange Labs​ on hardware acceleration with​‌ reconfigurable FPGA architectures for​​ next-generation edge/cloud infrastructures. The​​​‌ work program includes: (i)​ the evaluation of High-Level​‌ Synthesis (HLS) tools and​​ the quality of synthesized​​​‌ hardware accelerators, and (ii)​ time and space sharing​‌ of hardware accelerators, going​​ beyond coarse-grained device level​​​‌ allocation in virtualized infrastructures.​ The two topics are​‌ driven from requirements from​​ 5G use cases including​​​‌ 5G LDPC and deep​ learning LSTM networks for​‌ network management.

7.2.1​​​‌ Hardware accelerators for sparse​ DNNs on FPGA

Participants:​‌ Olivier Sentieys, Léo​​ Pradels, Daniel Chillet​​​‌, Silviu-Ioan Filip.​

Safran is funding a​‌ PhD to study the​​ FPGA implementation of deep​​​‌ convolutional neural network under​ SWAP (Size, Weight And​‌ Power) constraints for detection,​​ classification, image quality improvement​​​‌ of observation systems, and​ awareness functions (trajectory guarantee,​‌ geolocation by cross view​​ alignment) applied to autonomous​​​‌ vehicle. This thesis in​ particular considers pruning and​‌ reduced precision.

7.2.2 Security​​ of AI implementations

Participants:​​​‌ Olivier Sentieys, Benoit​ Coqueret.

Thales is​‌ funding a PhD on​​ physical security attacks against​​​‌ Artificial Intelligence based algorithms.​

7.2.3 Power consumption model​‌ for virtualization

Participants: Daniel​​ Chillet.

Orange Labs​​​‌ is funding a PhD​ on energy estimation of​‌ applications running on cloud.​​ The goal is to​​​‌ analyze application profiles and​ to develop an accurate​‌ estimator of power consumption​​ based on a selected​​​‌ subset of processor events.​

7.2.4 Efficient implementation of​‌ parallel applications

Participants: Bertrand​​ Le Gal, Simon​​​‌ Rokicki, Olivier Sentieys​.

KeySom SAS is​‌ funding the PhD thesis​​ of Léo Pajot on​​​‌ efficient implementation of parallel​ applications such as CNN​‌ on custom RISC-V processor​​ cores. The goal is​​​‌ to propose a CGRA​ like architecture and its​‌ compilation framework to ease​​ platform designer work in​​​‌ accelerating developed systems.

KeySom​ SAS is also funding​‌ the PhD thesis of​​ Anis Yagoub on the​​​‌ exploration of dynamically reconfigurable​ floating-point units for transprecision​‌ computation in deep learning.​​

7.2.5 Deep learning for​​​‌ video compression

Participants: Taha​ El Drissi, Olivier​‌ Sentieys.

InterDigital is​​ funding the PhD thesis​​​‌ of Taha El Drissi​ on Deep Learning for​‌ video compression.

8.1.1 Inria associate team​​​‌

8.1.2 Participation in other​​​‌ International Programs

8.2.1 Visits of international​‌ scientists

• Gayathri Ananthanarayanan, Assistant​​ professor at Indian Institute​​​‌ of Technology (IIT) Dharwad​ (Inde) and Omkar Shende,​‌ Phd Student at Indian​​ Institute of Technology (IIT)​​ Dharwad (Inde), visted Taran​​​‌ on May-June 2025
• Luigi‌ Carro, Full Professor at‌​‌ UFRGS, Brazil, visted Taran​​ on September 2025

8.2.2​​​‌ Visits to international teams‌

• In March 2025, Fernando‌​‌ Fernandes dos Santos visited​​ the Department of Computer​​​‌ Science of Western Paraná‌ State University, Brazil.

8.3.1 Horizon​​ Europe

8.3.2 Other european programs/initiatives​

8.4.1 ANR​ FASY

Participants: Angeliki Kritikakou​‌, Marcello Traiola,​​ Olivier Sentieys.

• Program:​​​‌ ANR JCJC (young researcher)​
• Project acronym: FASY
• Project​‌ title: FAult-aware timing behaviour​​ for safety-critical multicore SYstems​​​‌
• Duration: Jan. 2022 -​ July 2026
• P.I.: K.​‌ Kritikakou, TARAN

The safety-critical​​ embedded industries, such as​​​‌ avionics, automobile, robotics and​ health-care, require guarantees for​‌ hard real-time, correct application​​ execution, and architectures with​​​‌ multiple processing elements. While​ multicore architectures can meet​‌ the demands of best-effort​​ systems, the same cannot​​​‌ be stated for critical​ systems, due to hard-to-predict​‌ timing behaviour and susceptibility​​ to reliability threats. Existing​​​‌ approaches design systems to​ deal with the impact​‌ of faults regarding functional​​ behaviors. FASY extends the​​​‌ SoA by answering the​ two-fold challenge of time-predictable​‌ and reliable multicore systems​​ through functional and timing​​​‌ analysis of applications behaviour,​ fault-aware WCET estimation and​‌ design of cores with​​ time-predictable execution, under faults.​​​‌

8.4.2 ANR Re-Trusting

Participants:​ Olivier Sentieys, Angeliki​‌ Kritikakou, Marcello Traiola​​.

• Program: ANR PRC​​​‌
• Project acronym: Re-Trusting
• Project​ title: REliable hardware for​‌ TRUSTworthy artificial INtelliGence
• Duration:​​ Oct. 2021 - July​​​‌ 2026
• Coordinator: INL
• Other​ partners: LIP6, TARAN, THALES​‌

To be able to​​ run Artificial Intelligence (AI)​​​‌ algorithms efficiently, customized hardware​ platforms for AI (HW-AI)​‌ are required. Reliability of​​ hardware becomes mandatory for​​​‌ achieving trustworthy AI in​ safety-critical and mission-critical applications,​‌ such as robotics, smart​​ healthcare, and autonomous driving.​​​‌ The RE-TRUSTING project develops​ fault models and performs​‌ failure analysis of HW-AIs​​ to study their vulnerability​​ with the goal of​​​‌ “explaining” HW-AI. Explaining HW-AI‌ means ensuring that the‌​‌ hardware is error-free and​​ that the AI hardware​​​‌ does not compromise the‌ AI prediction accuracy and‌​‌ does not bias AI​​ decision-making. In this regard,​​​‌ the project aims at‌ providing confidence and trust‌​‌ in decision-making based on​​ AI by explaining the​​​‌ hardware wherein AI algorithms‌ are being executed.

8.4.3‌​‌ ANR LOTR

Participants: Simon​​ Rokicki.

• Program: ANR​​​‌ PRC
• Project acronym: LOTR‌
• Project title: Lord Of‌​‌ The RISCs
• Duration: Oct.​​ 2023 - Sep. 2027​​​‌
• Coordinator: Steven Derrien
• Other‌ partners: CEA, TARAN, PACAP,‌​‌ LabSTICC

Lord Of The​​ RISCs (LOTR) is a​​​‌ novel flow for designing‌ highly customized RISC-V processor‌​‌ microarchitectures for embedded and​​ IoT platforms. The LOTR​​​‌ flow operates on a‌ description of the processor‌​‌ Instruction Set Architecture (ISA).​​ It can automatically infer​​​‌ synthesizable Register Transfer Level‌ (RTL) descriptions of a‌​‌ large number of microarchitecture​​ variants with different performance/cost​​​‌ trade-offs. In addition, the‌ flow integrates two domain-specific‌​‌ toolboxes dedicated to the​​ support of timing predictability​​​‌ (for safety-critical systems) and‌ security (through hardware protection‌​‌ mechanisms).

8.4.4 CYBERPROS

Participants:​​ Olivier Sentieys.

• Program:​​​‌ BPI France
• Project title:‌ Fault Injection Emulator for‌​‌ Cyberattacks and System Security​​ Evaluation processeurs
• Duration: Oct.​​​‌ 2023 - Sep. 2026‌
• Coordinator: Patrice Deroux-Dauphin
• Other‌​‌ partners: TEMENTO, IROC

The​​ objective of the CYBERPROS​​​‌ project is to be‌ able to predict the‌​‌ behavior of a circuit​​ subjected to to cyberattacks​​​‌ by fault injection. The‌ research work consists of‌​‌ developing a active attack​​ emulator and associated simulation​​​‌ tools. A hardened processor‌ core will be developed‌​‌ as a test vehicle.​​ Test results will be​​​‌ digitized for editing of‌ learning algorithms underlying the‌​‌ creation of a database​​ and tools for predictive​​​‌ behavior.

8.4.5 PEPR ARSENE‌

Participants: Louis Savary,‌​‌ Herinomena Andrianatrehina, Simon​​ Rokicki, Olivier Sentieys​​​‌.

• Program: PEPR Cyber‌
• Project title: Secure architectures‌​‌ for embedded digital systems​​
• Duration: Jul. 2022 -​​​‌ Jun. 2028
• Coordinator: CEA‌
• Other partners: CEA, PACAP,‌​‌ TARAN, LHC, Lab-STICC, LIRMM,​​ Verimag, TIMA, LCIS, EMSE,​​​‌ Telecom Paris

The main‌ objectives of the ARSENE‌​‌ project are to allow​​ the French community to​​​‌ make significant advances in‌ the field to strengthen‌​‌ the community’s expertise and​​ visibility on the international​​​‌ stage. Taran's contribution is‌ on the study and‌​‌ implementation of two families​​ of RISC-V processors: 32-bit​​​‌ RISC-V for low power‌ secure circuits against physical‌​‌ attacks for IoT applications​​ and 64-bit RISC-V secure​​​‌ circuits against micro-architectural attacks.‌

8.4.6 ANR RADYAL

Participants:‌​‌ Marcello Traiola, Olivier​​ Sentieys.

• Program: ANR​​​‌ PRC
• Project acronym: RADYAL‌
• Project title: Resource-Aware DYnamically‌​‌ Adaptable machine Learning
• Duration:​​ Oct 2023 – Apr​​​‌ 2027
• Coordinator: Stefan Duffner,‌ LIRIS, Lyon
• Other partners:‌​‌ TARAN, LIRIS, CTRL-A (Inria​​ Grenoble), GIPSA-LAB

Nowadays, for​​​‌ many applications, the performance‌ requirements of a DNN‌​‌ model deployed on a​​ given hardware platform are​​​‌ not static but evolving‌ dynamically as its operating‌​‌ conditions and environment change.​​ RADYAL studies original interdisciplinary​​​‌ approaches that allow DNN‌ models to be dynamically‌​‌ configurable at run-time on​​​‌ a given reconfigurable hardware​ accelerator architecture, depending on​‌ the external environment, following​​ an approach based on​​​‌ feedback loops and control​ theory.

8.4.7 ANR SEC-V​‌

Participants: Bertrand Le Gal​​.

• Program: ANR PRCE​​​‌
• Project acronym: SEC-V
• Project​ title: open-source, secure and​‌ high-performance processor core based​​ on the RISC-V ISA​​​‌
• Duration: Oct 2021 –​ Apr 2025
• Coordinator: Sebastien​‌ Pillement, IETR, Nantes
• Other​​ partners: TARAN, LS2N, THALES​​​‌ TRT, THALES INVIA

In​ recent years, attacks exploiting​‌ optimization mechanisms have appeared.​​ Exploiting, for example, flaws​​​‌ in cache memories, performance​ counters or speculation units,​‌ they call into question​​ the safety and security​​​‌ of processors and the​ industrial systems that use​‌ them. SEC-V studies original​​ interdisciplinary approaches that rely​​​‌ on RISC-V open-hardware architectures​ and CISC paradigm to​‌ prodive runtime flexibility and​​ adaptability. The originality of​​​‌ the approach lies in​ the integration of a​‌ dynamic code transformation unit​​ covering 4 of the​​​‌ 5 NIST functions of​ cybersecurity, notably via monitoring​‌ (identify, detect), obfuscation (protect),​​ and dynamic adaptation (react).​​​‌ This dynamic management paves​ the way for on-line​‌ optimizations to improve the​​ security and safety of​​​‌ the microarchitecture, without reworking​ either the software or​‌ the chip architecture.

8.4.8​​ PEPR HOLIGRAIL

Participants: Nesrine​​​‌ Sfar, Rémi Garcia​, Mehdi El Arar​‌, Silviu Filip,​​ Olivier Sentieys.

• Program:​​​‌ PEPR IA
• Project acronym:​ HOLIGRAIL
• Project title: HOLIistic​‌ approaches to GReener model​​ Archi-tectures for Inference and​​​‌ Learning
• Duration: Oct 2023​ – Dec 2029
• Coordinator:​‌ Olivier Sentieys, Taran
• Other​​ partners: CEA List, INSA​​​‌ Lyon, Inria Corse, Grenoble-INP​

Accelerators of artificial intelligence​‌ algorithms currently consume much​​ more power than they​​​‌ should, in particular in​ the learning phase. The​‌ many aspects of this​​ question are too often​​​‌ considered in isolation. Based​ on the complementary expertise​‌ of the partners, and​​ thanks to the integration​​​‌ into the rich community​ build by the PEPR​‌ on foundation of frugal​​ AI, we will instead​​​‌ systematically look at a​ holistic, global comprehension of​‌ all these issues in​​ established and upcoming AI​​​‌ algorithms. We will therefore​ combine more compact and​‌ efficient number representations, hard-ware-aware​​ training algorithms that enhance​​​‌ structured sparsity, coding compactness​ and tensor transformations, with​‌ their adaptation to efficient​​ hardware mechanisms and compiler​​​‌ optimizations. Our ambition is​ to provide breakthroughs in​‌ efficiency when running inference​​ and training algorithms on​​​‌ specialized hardware. The results​ are intended to be​‌ integrated into development solutions​​ for embedded systems, in​​​‌ particular within the DeepGreen​ national platform for the​‌ deployment of deep learning​​ in embedded systems.

8.4.9​​​‌ PEPR ARCHI-SESAM

Participants: Marcello​ Traiola, Olivier Sentieys​‌.

• Program: PEPR Cloud​​
• Project acronym: ARCHI-SESAM
• Project​​​‌ title: Converged, Efficient and​ Safe Architecture based on​‌ Near Memory Accelerators
• Duration:​​ Oct 2023 – Dec​​​‌ 2029
• Coordinator: Denis Dutoit,​ CEA, Grenoble
• Other partners:​‌ Taran, CEA List, IMT,​​ Inria Convecs, Grenoble-INP

European​​​‌ sovereignty in the cloud​ also means sovereignty over​‌ hardware, especially processors and​​ accelerators. Improvement of processor​​​‌ performance requires hardware architectures​ that evolve towards more​‌ parallelism (multi-core), more specialization​​ (accelerators), a closer relationship​​ between computing and memory​​​‌ and new types of‌ interconnections between components. On‌​‌ the other hand, by​​ dissociating hardware resources (computing,​​​‌ memory, interconnection) from logical‌ resources, virtualization facilitates the‌​‌ deployment of converged architectures​​ that bring together the​​​‌ computing, storage and network‌ infrastructure. The cloud gains‌​‌ in modularity, speed and​​ agility for the deployment​​​‌ of new services with‌ optimal use of resources.‌​‌ Hardware disaggregation on the​​ one hand and resource​​​‌ virtualization on the other‌ are making the intermediate‌​‌ adaptation layer increasingly complex,​​ difficult to validate and​​​‌ prone to failure. The‌ Archi-CESAM project proposes to‌​‌ rethink the hardware (computing,​​ memory and interconnection) so​​​‌ that it is co-designed‌ with the application in‌​‌ a perspective of converged​​ architecture and trust, in​​​‌ an environment known for‌ its abundance of data‌​‌ to be processed. The​​ Archi-CESAM project addresses this​​​‌ major evolution of the‌ Cloud in a global‌​‌ and coordinated approach between​​ distributed architectures, acceleration, interconnection​​​‌ and security bricks, without‌ forgetting the design methods.‌​‌

8.4.10 PEPR IA -​​ AdaptING project

Participants: Angeliki​​​‌ Kritikakou, Marcello Traiola‌.

• Program: PEPR IA‌​‌
• Project acronym: AdaptING
• Project​​ title: Adaptive architectures for​​​‌ embedded artificial INtelliGence
• Duration:‌ Oct 2023 – Dec‌​‌ 2029
• Coordinator: Alberto Bosio,​​ ECL/INL, Lyon
• Other partners:​​​‌ CEA-List, IETR, Lab-STICC, Inria‌ (MALT, TARAN), LIP6

The‌​‌ increasing need to distribute​​ AI applications from the​​​‌ cloud to edge devices‌ is becoming a pressing‌​‌ concern for addressing data​​ privacy, bandwidth limitations, power​​​‌ consumption reduction, and low‌ latency requirements, especially for‌​‌ real-time, mission- and safety-critical​​ applications. Consequently, there is​​​‌ an ongoing effort to‌ design custom and embedded‌​‌ AI hardware architectures (AI-HW)​​ that can support energy-intensive​​​‌ data movement, speed of‌ computation, and large memory‌​‌ resources that AI requires​​ to achieve their full​​​‌ potential. However, the current‌ AI-HW architectures are mainly‌​‌ based on GPU, TPU,​​ or specialized designs, which​​​‌ are devoted to improving‌ the energy/performance efficiency for‌​‌ a specific class of​​ AI applications, such as​​​‌ Convolutional Neural Networks. Thus,‌ they are not designed‌​‌ to provide the high​​ flexibility and massive parallelism​​​‌ needed to support a‌ wide range of AI‌​‌ algorithms, including dynamic networks,​​ Recurrent NNs, Transformers, etc.​​​‌ To address these limitations,‌ the AdaptING project proposes‌​‌ a new architectural paradigm​​ called adaptive architecture, which​​​‌ aims to make HW‌ adaptable to any given‌​‌ AI application and its​​ constraints in terms of​​​‌ accuracy, energy, latency, and‌ reliability. The adaptive architecture‌​‌ is designed to provide​​ flexibility, efficiency, sustainability, and​​​‌ reliability for embedded AI.‌ This approach goes beyond‌​‌ the current state-of-the-art HW​​ architectures and targets the​​​‌ next generation of AI‌ by investigating and designing‌​‌ flexible, efficient, sustainable, and​​ reliable embedded AI on​​​‌ adaptive architectures.

8.4.11 Inria‌ Challenge CocoRISCo

Participants: Simon‌​‌ Rokicki, Olivier Sentieys​​.

• Program: Inria Challenge​​​‌
• Project acronym: CocoRISCo
• Project‌ title: Hardware-software interface for‌​‌ general purpose computing with​​ RISC-V
• Duration: Oct 2024​​​‌ – Sep 2028
• Coordinator:‌ Olivier Sentieys, Taran, Arthur‌​‌ Pérais, TIMA
• Other partners:​​ CEA List, Inria (Corse,​​​‌ Benagil, Pacap, Sushi, Madmax,‌ Taran)

CocoRISCo focuses on‌​‌ the hardware and low-level​​​‌ software aspects of computer​ systems. Specifically, those systems​‌ have dramatically evolved in​​ the past decades, yet​​​‌ many interfaces between hardware​ and software layers have​‌ remained in place with​​ little changes. Indeed, hardware​​​‌ has become heavily multithreaded​ (e.g., multi-, many-cores, GPUs),​‌ heterogeneous (e.g., dedicated accelerators​​ attached to CPUs), and​​​‌ open to vulnerabilities caused​ by increased complexity (e.g.,​‌ speculation-based attacks à la​​ Spectre). We aim to​​​‌ leverage the RISC-V open​ Instruction Set Architecture (ISA)​‌ – the interface between​​ software and the CPU​​​‌ – to revisit and​ improve those aspects, for​‌ instance by exposing more​​ hardware features to the​​​‌ programmer. CocoRISCo will gather​ 5 Inria teams that​‌ have a background in​​ architecture, microarchitecture, compilation, operating​​​‌ systems, and security, along​ with the SLS team​‌ of the TIMA laboratory​​ and the DSCIN of​​​‌ laboratory CEA List.

8.4.12​ Inria Exploratory Action RobotiCore​‌

Participants: Marcello Traiola.​​

• Program: Exploratory Action
• Project​​​‌ acronym: RobotiCore
• Project title:​ Integrated Hardware Acceleration :​‌ the Brain and Heart​​ Behind Next-Generation Robots
• Duration:​​​‌ Nov 2025 – Oct​ 2028
• Coordinator: Marcello Traiola,​‌ Taran and Marco Tognon,​​ RAINBOW

Imagine a world​​​‌ where small-scale robots become​ indispensable companions in our​‌ daily lives — aiding​​ in medical emergencies, ensuring​​​‌ personal safety, and performing​ tasks we hadn’t even​‌ imagined. RobotiCore aims at​​ making this vision a​​​‌ reality by pioneering a​ unified hardware accelerator that​‌ slashes power consumption and​​ boosts efficiency for autonomous​​​‌ systems. Traditional robotic platforms​ are bulky, energy-hungry, and​‌ costly, limiting their potential.​​ But RobotiCore wants to​​​‌ change the game with​ a groundbreaking approach: a​‌ single, low-power, compact hardware​​ solution designed to accelerate​​​‌ perception, planning, and control​ simultaneously. This innovation opens​‌ the door to frugal,​​ scalable, and affordable robots​​​‌ that can operate for​ far longer than current​‌ ones, unlocking unprecedented possibilities.​​ By merging cutting-edge expertise​​​‌ in computer architecture and​ robotics, RobotiCore is paving​‌ the way for a​​ future where energy-efficient, intelligent​​​‌ robots seamlessly integrate into​ our lives.

8.4.13 RAPID​‌ FOCH

Participants: Joseph Paturel​​, Olivier Sentieys.​​​‌

• Program: RAPID
• Project acronym:​ FOCH
• Project title: Development​‌ of a fault-tolerant FPGA​​ with tests in high-radiation​​​‌ environments
• Duration: Jan 2023​ – Dec 2025
• Coordinator:​‌ NanoXplore
• Other partners: Taran,​​ Onera, Nucletudes

FPGA components​​​‌ are widely used in​ aerospace and military applications.​‌ This project aims to​​ consider constrained radiative environments​​​‌ and to develop a​ fault-tolerant FPGA IP. A​‌ RISC-V processor will be​​ used as a test​​​‌ case for implementation on​ the FPGA IP and​‌ for evaluation in high-radiation​​ environments.

8.4.14 Inria Challenge​​​‌ OmicFinder

Participants: Bertrand Le​ Gal, Olivier Sentieys​‌.

• Program: Inria Challenge​​
• Project acronym: OmicFinder
• Project​​​‌ title: Biological data indexation​
• Duration: Oct 2023 –​‌ Dec 2027
• Coordinator: Pierre​​ Peterlongo, Genscale
• Other partners:​​​‌ Taran, Dyliss, Zenith, CEA-GenoScope,​ Elixir, Pasteur Institute, CEA-CNRGH,​‌ Mediterranean Institute of Oceanography​​

Genomic data enable critical​​​‌ advances in medicine, ecology,​ ocean monitoring, and agronomy.​‌ Precious sequencing data accumulate​​ exponentially in public genomic​​​‌ data banks such as​ the ENA. A major​‌ limitation is that it​​ is impossible to query​​ these entire data (petabytes​​​‌ of sequences). OmicFinder aims‌ to provide a novel‌​‌ global search engine making​​ it possible to query​​​‌ nucleotidic sequences against the‌ vast amount of publicly‌​‌ available genomic data. The​​ central algorithmic idea of​​​‌ a genomic search engine‌ is to index and‌​‌ query small exact words​​ (hundreds of billions over​​​‌ millions of datasets), as‌ well as the associated‌​‌ metadata. In addition to​​ the creation of fundamental​​​‌ novel algorithms and data‌ structures, the project develops‌​‌ new approaches to improve​​ the query experience and​​​‌ the answer information by‌ integrating the Semantic Web‌​‌ technologies framework. In view​​ of the considered volume​​​‌ of data, a part‌ of the research focuses‌​‌ on clever index distribution.​​ Throughout the project, we​​​‌ are committed to proposing‌ methods that minimize the‌​‌ environmental impact generated by​​ the massive use of​​​‌ the tools that will‌ be produced, in particular‌​‌ through the use of​​ specialized hardware.

9.1.1 Scientific events:​​​‌ organisation

9.1.2 Scientific events:‌ selection

9.1.3 Journal

9.1.4​​​‌ Invited talks

• F. Fernandes​ dos Santos gave an​‌ invited talk on Challenges​​ in Adopting Emerging AI​​​‌ Accelerators For Safety-Critical and​ Space Applications at IEEE​‌ NSREC Short Course 2025.​​
• F. Fernandes dos Santos​​​‌ gave an invited talk​ (Online) on How Radiation​‌ Can Mess with Your​​ DNN — and What​​​‌ We Can Do About​ It! at I workshop​‌ on design and manufacturing​​ of integrated circuits with​​​‌ open source tools, Universidad​ Pedagógica y Tecnológica de​‌ Colombia, 2025.
• F. Fernandes​​ dos Santos gave an​​​‌ invited talk on Hardware​ Fault Effects in DNN​‌ Inference and Strategies for​​ Efficient Mitigation at Computer​​​‌ Science Departament at Western​ Paraná State University, Brazil,​‌ 2025.
• A. Kritikakou gave​​ a keynote talk on​​​‌ Building Reliable AI Systems:​ Rethinking Assessment Across the​‌ Stack during AI and​​ Infrastructures scientific days, organized​​​‌ by GDR-SOC2 and GDR-RSD,​ France, 2025
• M. Traiola​‌ gave a keynote talk​​ titled “Toward Adaptive Embedded​​​‌ Systems: from Multi-Objective Design​ to Runtime Adaptation" at​‌ the 13th Prague Embedded​​ Systems Workshop (PESW), Czech​​​‌ Republic, 2025
• O. Sentieys​ gave an invited talk​‌ on Compressing Neural Networks​​ for Deployment or Training​​​‌ at InterDigital seminar, 2025.​

9.1.5 Leadership within the​‌ scientific community

• D. Chillet​​ is a member of​​ the French National University​​​‌ Council in Signal Processing‌ and Electronics (CNU -‌​‌ Conseil National des Universites,​​ 61ème section) since 2019.​​​‌
• D. Chillet is member‌ of the Board of‌​‌ Directors of Gretsi Association.​​
• A. Kritikakou is a​​​‌ member of the French‌ National University Council in‌​‌ Computer Science (CNU -​​ Conseil National des Universites,​​​‌ 27ème section) since 2022‌ and until 11/2025.
• A.‌​‌ Kritikakou is co-animator of​​ the "High performance embedded​​​‌ computing" topic of GDR‌ SoC2.
• A. Kritikakou is‌​‌ the president of IEEE​​ CEDA French Chapter, founded​​​‌ in September 2025.
• O.‌ Sentieys is a member‌​‌ of the steering committee​​ of a CNRS Spring​​​‌ School for graduate students‌ on embedded systems architectures‌​‌ and associated design tools​​ (ARCHI).
• O. Sentieys is​​​‌ a member of the‌ steering committee of GDR‌​‌ SoC2.
• M. Traiola is​​ co-chair of the "Méthodologies​​​‌ et Outils" topic of‌ GDR SoC2.

9.1.6 Scientific‌​‌ expertise

• A. Kritikakou was​​ a reviewer for ANR​​​‌ France 2030.
• B. Le‌ Gal was a reviewer‌​‌ for the NWO Talent​​ Programme (Nederland)
• M. Traiola​​​‌ was a reviewer for‌ ANR-DFG joint call 2025.‌​‌

9.1.7 Standardization activities

• S.​​ Filip and O. Sentieys​​​‌ are members of the‌ IEEE P3109 Standardization Group‌​‌ on Arithmetic Formats for​​ Machine Learning.

9.2.1 Teaching​​ administration

• A. Kritikakou is​​​‌ a member of the‌ Examination Committee of Industrial‌​‌ Engineering Sciences and Computer​​ Engineering (SII) Aggregation.
• B.​​​‌ Le Gal is associate‌ director of studies at‌​‌ ENSSAT Engineering Graduate School​​ since Nov 2024.
• S.​​​‌ Rokicki is responsible of‌ the second year of‌​‌ the computer science department​​ at ENS Rennes

9.2.2​​​‌ Teaching

• D. Chillet: Basic‌ processor architectures, 30h, Enssat‌​‌ (L3)
• D. Chillet: Multimedia​​ processor architectures, 30h, Enssat​​​‌ (M2)
• D. Chillet: Advanced‌ processor architectures, 20h, Enssat‌​‌ (M2)
• D. Chillet: Embedded​​ Systems 40h (M1)
• D.​​​‌ Chillet: Embedded Software Development,‌ 16h, Enssat (L3)
• D.‌​‌ Chillet: Low-power digital CMOS​​ circuits, 6h, UBO (M2)​​​‌
• A. Kritikakou: Tools and‌ programming in C, 24.75h,‌​‌ istic (L3)
• A. Kritikakou:​​ Computer programming, 22.5h, istic​​​‌ (L3)
• A. Kritikakou: Unix‌ commands and programming, 6.75h,‌​‌ istic (L3)
• A. Kritikakou:​​ Fault tolerant embedded systems,​​​‌ 6h, INSA (M2)
• A.‌ Kritikakou: Energy sobriety of‌​‌ digital architectures, 7.5h, INSA​​ (M2)
• B. Le Gal:​​​‌ Digital fundamentals, 24h, ENSSAT‌ (L3)
• B. Le Gal:‌​‌ VHDL design, 32h, ENSSAT​​ (M1)
• B. Le Gal:​​​‌ Hardware & software verification,‌ 12h, ENSSAT (M1)
• B.‌​‌ Le Gal: Processor design​​ (RISC-V), 26h, ENSSAT (M1)​​​‌
• B. Le Gal: Real-time‌ programming, 26h, ENSSAT (M1)‌​‌
• B. Le Gal: Software​​ compilation, 16h, ENSSAT (M2)​​​‌
• B. Le Gal: System‌ on Chip design, 18h,‌​‌ ENSSAT (M2)
• B. Le​​ Gal: High performance computing,​​​‌ 16h, ENSSAT (M2)
• S.‌ Rokicki: Compilers, 24h, ENS‌​‌ Rennes
• S. Rokicki: Advanced​​ Compilers, 10h, ENS Rennes​​​‌
• O. Sentieys: Hardware Accelerators‌ for Deep Neural Networks,‌​‌ 54h, Master of Embedded​​ Systems, istic (M2)
• O.​​​‌ Sentieys, High-Level synthesis, 20h,‌ Master of Computer Science,‌​‌ istic (M2)
• M. Traiola:​​ Operating Systems, 24h, ENS​​​‌ Rennes (Aggregation Mecatronique)
• M.‌ Traiola: Hardware Accelerators for‌​‌ Deep Neural Networks, 12h​​​‌ TP, Master of Embedded​ Systems, istic (M2)
• F.​‌ Fernandes dos Santos: TinyML​​ at Master SE istic​​​‌(6h).
• F. Fernandes dos​ Santos: C/Unix for L3​‌ (39h TPs)
• F. Fernandes​​ dos Santos: Frugal AI​​​‌ at Master 2 at​ ISTIC alternance (39h TPs)​‌

9.2.3 Supervision

• PhD defended:​​ Hamza Amara, Evaluation and​​​‌ Protection of Compressed Network​ on Chip Communications Against​‌ Hardware Trojan Attacks, Dec.​​ 2025, E. Casseau, D.​​​‌ Chillet, C. Killian 63​.
• PhD defended: Gaetan​‌ Barret, Predictive models for​​ the energy cost of​​​‌ cloud-native applications, Dec. 2025,​ D. Chillet 64.​‌
• PhD defended: Sami Ben​​ Ali, Efficient Low-Precision Training​​​‌ for Deep Learning Accelerators,​ April 2025, O. Sentieys,​‌ S. Filip 66.​​
• PhD defended: Benoit Coqueret,​​​‌ On the Complementarity of​ Software and Side-Channel Attacks​‌ against Deep Learning Algorithms,​​ CIFRE Thesis with Thales,​​​‌ Dec. 2025, O. Sentieys,​ M. Carbone (Thales), G.​‌ Zaid (Thales) 67.​​
• PhD defended: Wilfread Guilleme,​​​‌ Fault-Tolerant Hardware Architectures for​ Artificial Intelligence Algorithms, Dec.​‌ 2025, D. Chillet, C.​​ Killian, A.Kritikakou 68.​​​‌
• PhD defended: Baptiste Rossigneux,​ Sparsity in neural networks:​‌ the trade-off between operation​​ count and complexity for​​​‌ embedded systems, Oct. 2025,​ E. Casseau, I. Kucher​‌ (CEA), V. Lorrain (CEA)​​ 72.
• PhD defended:​​​‌ Léo De La Fuente,​ Energy optimization in near-memory​‌ computing through local instruction​​ generation, May 2025, O.​​​‌ Sentieys, J.-F. Christmann (CEA)​ 70.
• PhD defended:​‌ Seungah Lee, Efficient Designs​​ of On-Board Heterogeneous Embedded​​​‌ Systems for Space Applications,​ Jan. 2025, A. Kritikakou,​‌ E. Casseau, R. Salvador,​​ O. Sentieys 69.​​​‌

• PhD defended: Amélie Marotta,​ Effects of synchronous clock​‌ glitch effect on the​​ security of an integrated​​​‌ circuit, June 2025, O.​ Sentieys, R. Lashermes (LHS),​‌ Rachid Dafali (DGA) 71​​.

   

• PhD in progress:​​​‌ Valentin Abgrall, Vulnerability analysis,​ fault modeling, and countermeasures​‌ towards dependable real-time computing​​ in safety-critical drone systems,​​​‌ December 2025, A. Kritikakou,​ M. Traiola.
• PhD in​‌ progress: Noam Bires, Trustworthy​​ AI Hardware Architecture, October​​​‌ 2025, A. Kritikakou, M.​ Traiola.
• PhD in progress:​‌ Nour Chiboub, FPGA hardware​​ acceleration of genomic data​​​‌ indexing, April 2025, D.​ Chillet, B. Le Gal.​‌
• PhD in progress: Taha​​ El Idrissi, Architectures for​​​‌ Deep Video Compression, April​ 2025, O; Sentieys, O.​‌ Le Meur (InterDigital).
• PhD​​ in progress: Alexandros Farmakis,​​​‌ Hardware Accelerations for Unmanned​ Aerial Vehicle Control Algorithms,​‌ Nov. 2025, M. Traiola,​​ M. Tognon (Rainbow), T.​​​‌ Belvedere (Rainbow)
• PhD in​ progress: Thomas Feuilletin, An​‌ HDL for Mircroarchitecture Design,​​ Oct. 2025, S. Rokicki,​​​‌ I. Puaut (PACAP), S.​ Derrien (Lab-STICC).
• PhD in​‌ progress: Gwendal Le Martin,​​ Enhancing security through dynamic​​​‌ micro-instruction decoding management, Dec.​ 2025, B. Le Gal,​‌ S. Pillement (IETR).
• PhD​​ in progress: Elyakim Mirande-Ney,​​​‌ Dedicated DSL for modelisation,​ simulation and generation of​‌ heterogeneous NoCs, Dec. 2025,​​ D. Chillet, B. Le​​​‌ Gal.
• PhD in progress:​ Hadrien Moulherat, Automated Exploration​‌ of Microarchitectures for RISC​​ V Processors, Oct. 2025,​​​‌ A. Chillet. L. Zaourar​ (CEA), O. Sentieys.
• PhD​‌ in progress: Marwa Saad,​​ Increasing the operational lifespan​​​‌ of a Multiprocessor Circuit​ based on the open​‌ and free RISC V​​ architecture, September 2025, E.​​ Casseau, D. Chillet, B.​​​‌ Le Gal.
• PhD in‌ progress: Mario Wagner, Reliability‌​‌ of unconventional non-Von Neuman​​ hardware accelerators, October 2025,​​​‌ F. Fernandes dos Santos,‌ M. Traiola, A. Kritikakou.‌​‌
• PhD in progress: Sohaib​​ Errabii, Dynamically Configurable Deep​​​‌ Neural Network Hardware Accelerators,‌ April 2024, M. Traiola,‌​‌ O. Sentieys.
• PhD in​​ progress: Anis Yagoub, Exploring​​​‌ dynamically reconfigurable floating-point units‌ for transprecision computation in‌​‌ deep learning, CIFRE Thesis​​ with Keysom SAS, Sep.​​​‌ 2024, B. Le Gal,‌ O. Sentieys.
• PhD in‌​‌ progress: Lucas Roquet, Dependability​​ Evaluation and Enhancing Methods​​​‌ for Large Machine Learning‌ Models, Oct. 2024, F.‌​‌ Fernandes dos Santos, A.​​ Kritikakou.
• PhD in progress:​​​‌ Romain Facq, Exploring low‌ precision arithmetic for continual‌​‌ learning tasks on edge​​ devices, Oct. 2024, O.​​​‌ Sentieys, S. Filip.
• PhD‌ in progress: Nesrine Sfar,‌​‌ Compression, fine-tuning, and hardware​​ acceleration of Transformer-based models,​​​‌ Dec. 2024, O. Sentieys,‌ S. Filip.
• PhD in‌​‌ progress: Dylan Leothaud, Automatic​​ synthesis of secure and​​​‌ predictable processors for the‌ Internet of Thing, Oct.‌​‌ 2023, S. Derrien, S.​​ Rokicki.
• PhD in progress:​​​‌ Leo Pajot, Soft-core processor‌ with dynamic binary execution‌​‌ exploiting instruction-level parallelism, CIFRE​​ Thesis with Keysom SAS,​​​‌ Sep. 2023, B. Le‌ Gal, S. Rokicki.
• PhD‌​‌ in progress: Oussama Ait​​ Sidi Ali, Virtualisation of​​​‌ a multi-mission telemetry receiver,‌ CIFRE Thesis with Safran,‌​‌ Apr. 2022, B. Le​​ Gal.
• PhD in progress:​​​‌ Herinomena Andrianatrehina, Ensuring confidentiality‌ in modern Out-of-Order cores,‌​‌ Nov 2022, S. Rokicki,​​ R. Lashermes.
• PhD in​​​‌ progress: Guillaume Lomet, Guess‌ What I'm Learning: Side-Channel‌​‌ Analysis of Edge AI​​ Training Accelerators, Oct. 2022,​​​‌ C. Killian, R. Salvador,‌ O. Sentieys
• PhD in‌​‌ progress: Romaric (Pegdwende) Nikiema,​​ Time-guaranteed and reliable execution​​​‌ for real-time multicore architectures,‌ Oct. 2022, A. Kritikakou,‌​‌ M. Traiola
• PhD in​​ progress: Louis Savary, Security​​​‌ of DBT-based processors, Sept‌ 2022, S. Rokicki, S.‌​‌ Derrien.

International​ journals

• 30 articleA.​‌Abdallah Abdallah, C.​​Camille Monière, B.​​​‌Bertrand Le Gal and​ E.E. Boutillon.​‌ Adaptive Multiple-Attempts Approach to​​ Optimize Multiple-Vote Symbol-Flipping NB-LDPC​​​‌ Decoder.IEEE Communications​ Letters2025, 1-5​‌In press. HALDOI​​back to text
• 31​​​‌ articleA.Alberto Bosio​, S.Samuele Germiniani​‌, G.Graziano Pravadelli​​ and M.Marcello Traiola​​​‌. A genetic approach​ for automatic AxC design​‌ exploration at RTL based​​ on assertion mining and​​​‌ fault analysis.IEEE​ Transactions on Emerging Topics​‌ in ComputingSeptember 2025​​, 1-15HALDOI​​​‌back to textback​ to textback to​‌ text
• 32 articleB.​​Bruno Loureiro Coelho,​​​‌ F.Fernando Fernandes dos​ Santos, M.Matteo​‌ Saveriano, G.Gregory​​ Allen, A.Andrew​​ Daniel, S.Steven​​​‌ Guertin, S.Sergeh‌ Vartania, E.Edward‌​‌ Wyrwas, C.Christopher​​ Frost and P.Paolo​​​‌ Rech. Impact of‌ Radiation-Induced Effects on Embedded‌​‌ GPUs Executing Large Machine​​ Learning Models.IEEE​​​‌ Transactions on Nuclear Science‌728August 2025‌​‌, 2652-2661HALDOI​​back to text
• 33​​​‌ articleP.Pablo de‌ Oliveira Castro, E.-M.‌​‌El-Mehdi El Arar,​​ E.Eric Petit and​​​‌ D.Devan Sohier.‌ Error Analysis of Sum-Product‌​‌ Algorithms under Stochastic Rounding​​.SIAM Journal on​​​‌ Scientific Computing476‌2025, B1481--B1502HAL‌​‌DOIback to text​​
• 34 articleJ.Juliette​​​‌ Pottier, M.Maria‌ Méndez Real, B.‌​‌Bertrand Le Gal and​​ S.Sébastien Pillement.​​​‌ DynHaMo: Dynamic Hardware-based Monitoring‌ dedicated to Attacks Detection‌​‌.ACM Transactions on​​ Embedded Computing Systems (TECS)​​​‌245sSeptember 2025‌, 1 - 25‌​‌HALDOIback to​​ text
• 35 articleM.​​​‌Mael Tourres, C.‌Cyrille Chavet, B.‌​‌ L.Bertrand Le Gal​​ and P.Philippe Coussy​​​‌. Specialized Scalar and‌ SIMD Instructions for Error‌​‌ Correction Codes Decoding on​​ RISC-V Processors.IEEE​​​‌ Access132025,‌ 6964-6976HALDOIback‌​‌ to text

International peer-reviewed​​ conferences

• 36 inproceedingsH.​​​‌Hamza Amara, C.‌Cédric Killian, D.‌​‌Daniel Chillet and E.​​Emmanuel Casseau. DyEKF:​​​‌ Dynamic Protection of Approximate‌ NoC Communications Against Hardware‌​‌ Trojan Attacks.38th​​ IEEE International System-on-Chip Conference​​​‌SOCC 2025 - 38th‌ IEEE International System-on-Chip Conference‌​‌Dubai, United Arab Emirates​​IEEE2025, 1-9​​​‌HALback to text‌
• 37 inproceedingsH.Herinomena‌​‌ Andrianatrehina, R.Ronan​​ Lashermes, J.Joseph​​​‌ Paturel, S.Simon‌ Rokicki and T.Thomas‌​‌ Rubiano. Exploring speculation​​ barriers for RISC-V selective​​​‌ speculation.ARES 2025‌ - 20th International Conference‌​‌ on Availability, Reliability and​​ SecurityGhent, BelgiumAugust​​​‌ 2025, 1-23HAL‌back to text
• 38‌​‌ inproceedingsM.Mario Barbareschi​​, S.Salvatore Barone​​​‌, A.Alberto Bosio‌, B.Bastien Deveautour‌​‌, A.Ali Piri​​ and M.Marcello Traiola​​​‌. Automatic generation of‌ input-aware approximate arithmetic circuits‌​‌.DDECS 2025 -​​ IEEE 28th International Symposium​​​‌ on Design and Diagnostics‌ of Electronic Circuits and‌​‌ SystemsLyon, FranceIEEE​​2025, 139-144HAL​​​‌DOIback to text‌back to textback‌​‌ to text
• 39 inproceedings​​G.Gaëtan Barret,​​​‌ D.Daniel Chillet,‌ R.Roland Picard and‌​‌ J.Joël Penhoat.​​ Towards Accurate Static Power​​​‌ Model on Multi-Core Operating‌ Systems.RAPIDO 2025‌​‌ - 17th Workshop on​​ Rapid Simulation and Performance​​​‌ Evaluation for Design Optimization‌Barcelona Spain, FranceACM‌​‌2025, 1-7HAL​​DOIback to text​​​‌
• 40 inproceedingsG.Gaëtan‌ Barret, J.Joël‌​‌ Penhoat, R.Roland​​ Picard and D.Daniel​​​‌ Chillet. Empirical Analysis‌ and Estimation of the‌​‌ Energy Cost of Data​​ Transfers in CPU Caches​​​‌ in Multi-Core Systems.‌2025 14th Mediterranean Conference‌​‌ on Embedded Computing (MECO)​​MECO 2025 - 14th​​​‌ Mediterranean Conference on Embedded‌ ComputingBudva, MontenegroIEEE‌​‌ (Institute of Electrical and​​​‌ Electronics Engineers)2025,​ 1-4HALDOIback​‌ to text
• 41 inproceedings​​S.Sami Ben Ali​​​‌, S.-I.Silviu-Ioan Filip​, O.Olivier Sentieys​‌ and G.Guy Lemieux​​. MPTorch-FPGA: a Custom​​​‌ Mixed-Precision Framework for FPGA-based​ DNN Training.DATE​‌ 2025 - 28th IEEE/ACM​​ Design, Automation and Test​​​‌ in EuropeLyon, France​2025, 1-6HAL​‌back to text
• 42​​ inproceedingsS.Sohaib Errabii​​​‌, O.Olivier Sentieys​ and M.Marcello Traiola​‌. KAN-SAs: Efficient Acceleration​​ of Kolmogorov-Arnold Networks on​​​‌ Systolic Arrays.DATE​ 2026 - IEEE/ACM Design,​‌ Automation & Test in​​ Europe ConferenceVerona, Italy​​​‌2026HALback to​ text
• 43 inproceedingsT.​‌Thomas Feuilletin, D.​​Dylan Leothaud, S.​​​‌Simon Rokicki, S.​Steven Derrien and I.​‌Isabelle Puaut. Automatic​​ Extraction of Timing Models​​​‌ for WCET Estimation From​ a High-Level Synthesis Flow​‌.DATE 2026 -​​ Design, Automation and Test​​​‌ in Europe ConferenceVerona,​ ItalyApril 2026HAL​‌back to text
• 44​​ inproceedingsR.Rémi Garcia​​​‌, L.Léo Pradels​, S.-I.Silviu-Ioan Filip​‌ and O.Olivier Sentieys​​. Hardware-Aware Training for​​​‌ Multiplierless Convolutional Neural Networks​.ARITH 2025 -​‌ 32nd IEEE International Symposium​​ on Computer ArithmeticEl​​​‌ Paso, United StatesIEEE​2025, 1-8HAL​‌back to text
• 45​​ inproceedingsW.Wilfread Guillemé​​​‌, A.Angeliki Kritikakou​, Y.Youri Helen​‌, C.Cédric Killian​​ and D.Daniel Chillet​​​‌. Fault Tolerance in​ Quantized and Pruned Convolutional​‌ Neural Networks.IOLTS​​ 2025 - IEEE 31st​​​‌ International Symposium on On-Line​ Testing and Robust System​‌ DesignIschia, ItalyIEEE​​2025, 1-7HAL​​​‌DOIback to text​
• 46 inproceedingsM.Maksim​‌ Jenihhin, J.Jaan​​ Raik, A.Artur​​​‌ Jutman, N.Natalia​ Cherezova, R.Raimund​‌ Ubar, L.Liviu​​ Miclea, S.Szilard​​​‌ Enyedi, I.Iulia​ Stefan, O.Ovidiu​‌ Stan, C.Cosmina​​ Corches, Z.Zebo​​​‌ Peng, P.Petru​ Eles, R.Rolf​‌ Drechsler, S.Stephan​​ Eggersglüß, G.Görschwin​​​‌ Fey, A.Andreas​ Glowatz, D.Daniel​‌ Tille, G.Georges​​ Gielen, A.Anthony​​​‌ Coyette, W.Wim​ Dobbelaere, R.Ronny​‌ Vanhooren, P.-Y.Po-Yao​​ Chuang, E. J.​​​‌Erik Jan Marinissen,​ G.Giorgio Di Natale​‌, M.Manuel Barragan​​, P.Paolo Maistri​​​‌, S.Salvador Mir​, I.Ioana Vatajelu​‌, P.Paolo Bernardi​​, S.Stefano Di​​​‌ Carlo, P.Paolo​ Prinetto, M.Matteo​‌ Sonza Reorda, M.​​Massimo Violante, H.​​​‌Haralampos Stratigopoulos, M.​ K.Maria K. Michael​‌, S.Stelios Neophytou​​, S.Stavros Hadjitheophanous​​​‌, K. A.Kyriakos​ A. Christou, M.​‌Michael Skitsas, A.​​Alberto Bosio, B.​​​‌Bastien Deveautour, P.​Patrick Girard, M.​‌Marcello Traiola, A.​​Arnaud Virazel, F.​​​‌Fernando Fernandes dos Santos​, A.Angeliki Kritikakou​‌, G.Giulia Casagranda​​, M.Marzio Vallero​​​‌, F.Flavio Vella​, P.Paolo Rech​‌, L. M.Letícia​​ Maria Bolzani Poehls,​​ M.Milos Krstic,​​​‌ M.Marko Andjelkovic,‌ F. L.Fabian Luis‌​‌ Vargas, G.Grigor​​ Tshagharyan, G.Gurgen​​​‌ Harutyunyan, V.Valery‌ Vardanian, S. K.‌​‌Samvel K. Shoukourian,​​ Y.Yervant Zorian,​​​‌ J.Jennifer Dworak,‌ K.Kundan Nepal,‌​‌ T.Theodore Manikas,​​ M.Motta Taouil,​​​‌ M.Moritz Fieback,‌ A.Anteneh Gebregiorgis,‌​‌ R.Rajendra Bishnoi,​​ S.Said Hamdioui,​​​‌ A.Abhijit Chatterjee,‌ A.Anurup Saha,‌​‌ S. G.Sri Gowri​​ Komarraju, K.Kwondo​​​‌ Ma, C.Chandramouli‌ Amarnath, M. B.‌​‌Mehdi B. Tahoori,​​ M.Mahta Mayahinia,​​​‌ M.Maryam Rajabalipanah,‌ K.Katayoon Basharkhah,‌​‌ N.Nooshin Nosrati,​​ Z.Zahra Jahanpeima,​​​‌ Z.Zainalabedin Navabi,‌ H.-J.Hans-Joachim Wunderlich and‌​‌ S.Sybille Hellebrand.​​ European Test Symposium Teams​​​‌ : an Anniversary Snapshot‌.2025 IEEE European‌​‌ Test Symposium (ETS)ETS​​ 2025 - 30th IEEE​​​‌ European Test SymposiumTallinn,‌ EstoniaIEEEJuly 2025‌​‌, 1-48HALDOI​​
• 47 inproceedingsD.Dylan​​​‌ Leothaud, J.-M.Jean-Michel‌ Gorius, S.Simon‌​‌ Rokicki and S.Steven​​ Derrien. Optimizing Recovery​​​‌ Logic in Speculative High-Level‌ Synthesis.DAC 2025‌​‌ - 62nd Design Automation​​ ConferenceSan Fransisco, United​​​‌ States2025, 1-7‌HALDOIback to‌​‌ text
• 48 inproceedingsD.​​Dylan Leothaud, S.​​​‌Simon Rokicki, S.‌Steven Derrien and I.‌​‌Isabelle Puaut. Area​​ Efficient Speculative Loop Pipelining​​​‌ for High-Level Synthesis.‌DATE 2026 - Design,‌​‌ Automation and Test in​​ Europe ConferenceVerona, Italy​​​‌April 2026HALback‌ to text
• 49 inproceedings‌​‌G.Guillaume Lomet,​​ R.Ruben Salvador,​​​‌ B.Brice Colombier,‌ V.Vincent Grosso,‌​‌ O.Olivier Sentieys and​​ C.Cédric Killian.​​​‌ Side-Channel Extraction of Dataflow‌ AI Accelerator Hardware Parameters‌​‌.2025 IEEE 30th​​ International Symposium on On-Line​​​‌ Testing and Robust System‌ Design (IOLTS)2025 IEEE‌​‌ 31st International Symposium on​​ On-Line Testing and Robust​​​‌ System Design (IOLTS)Ischia,‌ Italy2025, 1-7‌​‌HALDOIback to​​ text
• 50 inproceedingsV.​​​‌Vishesh Mishra, M.‌Marcello Traiola, A.‌​‌Angeliki Kritikakou, O.​​Olivier Sentieys and U.​​​‌Urbi Chatterjee. SERA-Float:‌ A Soft Error Resilient‌​‌ Approximate Floating-Point Computing Format​​.ICCAD 2025 -​​​‌ ACM/IEEE International Conference On‌ Computer Aided DesignMunich‌​‌ (Allemagne), GermanyIEEE2025​​, 1-9HALback​​​‌ to text
• 51 inproceedings‌L.Lucas Roquet,‌​‌ F.Fernando Fernandes dos​​ Santos, L.Luigi​​​‌ Carro and A.Angeliki‌ Kritikakou. Assessing the‌​‌ Limitations of Activation Clipping​​ for Fault Mitigation in​​​‌ Vision and Language Transformers‌.LATS 2026 -‌​‌ 27th IEEE Latin American​​ Test SymposiumFlorianópolis, SC,​​​‌ BrazilIEEE2026HAL‌back to text
• 52‌​‌ inproceedingsL.Lucas Roquet​​, F.Fernando Fernandes​​​‌ dos Santos, M.‌Maria Kastriotou and A.‌​‌Angeliki Kritikakou. Strategic​​ Input Selection For Deep​​​‌ Neural Networks Reliability Evaluation‌.NSREC 2025 -‌​‌ IEEE Nuclear & Space​​ Radiation Effects ConferenceNashville​​​‌ (Tennessee), United StatesIEEE‌2025, 1-5HAL‌​‌back to text
• 53​​​‌ inproceedingsB.Baptiste Rossigneux​, V.Vincent Lorrain​‌, I.Inna Kucher​​ and E.Emmanuel Casseau​​​‌. Importance Resides In​ Activations: Fast Input-Based Nonlinearity​‌ Pruning.ICONIP 2024​​ Conference ProceedingsICONIP 2024​​​‌ - 31st International Conference​ on Neural Information Processing​‌Auckland, New ZealandMarch​​ 2025, 1-13HAL​​​‌back to text
• 54​ inproceedingsL.Louis Savary​‌, S.Simon Rokicki​​ and S.Steven Derrien​​​‌. Ahead of Time​ Generation for GPSA Protection​‌ in RISC-V Embedded Cores​​.ASAP 2025 -​​​‌ 36th IEEE International Conference​ on Application-specific Systems, Architectures​‌ and ProcessorsVancouver (BC),​​ CanadaIEEE2025,​​​‌ 1-7HALback to​ text
• 55 inproceedingsL.​‌Louis Savary, S.​​Simon Rokicki and S.​​​‌Steven Derrien. Hardware/Software​ Runtime for GPSA Protection​‌ in RISC-V Embedded Cores​​.DATE 2025 -​​​‌ Design, Automation and Test​ in Europe ConferenceLyon,​‌ France2025, 1-7​​HALback to text​​​‌
• 56 inproceedingsR. B.​Rafael Billig Tonetto,​‌ M.Marcello Traiola,​​ F.Fernando Fernandes and​​​‌ A.Angeliki Kritikakou.​ ENFOR-SA: End-to-end Cross-layer Transient​‌ Fault Injector for Efficient​​ and Accurate DNN Reliability​​​‌ Assessment on Systolic Arrays​.VTS 2026 -​‌ IEEE VLSI Test Symposium​​VTS 2026 - IEEE​​​‌ VLSI Test SymposiumNapa​ Valley, CA, United States​‌2026HAL

Conferences without​​ proceedings

• 57 inproceedingsR.​​​‌Robinson Carrere, G.​Guillaume Ferre, B.​‌Bertrand Le Gal and​​ P.Philippe Cais.​​​‌ Software defined radio implementation​ optimized for nanosatellites.​‌FAR 2025 - 3rd​​ International Conference on Flight​​​‌ Vehicles, Aerothermodynamics and Re-entry​Arcachon, France2025,​‌ 1-8HAL
• 58 inproceedings​​G.Guillaume Didier,​​​‌ A.Augustin Lucas and​ T.Thomas Rokicki.​‌ Cache Attacks in Modern/Multi-Socket​​ x86 Systems (Work in​​​‌ Progress).HS3 2025​ - 1st Workshop on​‌ Hardware-Supported Software SecurityToulouse,​​ FranceSeptember 2025,​​​‌ 1-10HAL
• 59 inproceedings​R.Rémi Garcia and​‌ A.Anna Lambert.​​ Bug dans plusieurs solveurs​​​‌ de programmation linéaire en​ nombres entiers.ROADEF​‌ 2026 - 27ème édition​​ du congrès annuel de​​​‌ la Société Française de​ Recherche Opérationnelle et d'Aide​‌ à la DécisionTours,​​ France2026HAL
• 60​​​‌ inproceedingsW.Wilfread Guilleme​, A.Angeliki Kritikakou​‌, Y.Youri Helen​​, C.Cédric Killian​​​‌ and D.Daniel Chillet​. Tolérance aux Fautes​‌ des CNNs Quantifiés et​​ Élagués.Gretsi 2025​​​‌ - XXXème Colloque Francophone​ de Traitement du Signal​‌ et des ImagesStrasbourg,​​ FranceAugust 2025,​​​‌ 1-4HAL
• 61 inproceedings​L.Léo Pradels,​‌ R.Rémi Garcia,​​ S.-I.Silviu-Ioan Filip,​​​‌ O.Olivier Sentieys and​ D.Daniel Chillet.​‌ Origami : L'art du​​ pliage appliqué à l'accélération​​​‌ des CNNs sur FPGA​.GRETSI 2025 -​‌ Groupe de Recherche et​​ d'Etudes de Traitement du​​​‌ Signal et des Images​Strasboug, France2025,​‌ 1-4HAL
• 62 inproceedings​​S. S.Siva Satyendra​​​‌ Sahoo, B.Bastien​ Deveautour, M.Marcello​‌ Traiola, C.Chongyan​​ Gu, Y.Yun​​​‌ Wu, A.Aditya​ Japa, S.Salim​‌ Ullah and A.Akash​​ Kumar. Special Sessions​​ -Emerging Scope and Design​​​‌ Challenges for Approximate Computing:‌ Optimizing Accuracy-PPA trade-offs and‌​‌ Beyond.CASES -​​ 2025 International Conference on​​​‌ Compilers, Architecture, and Synthesis‌ for Embedded SystemsESWEEK‌​‌ 2025 - Embedded Systems​​ WeekTAIPEI, TaiwanNovember​​​‌ 2025, 11-20HAL‌DOI

Doctoral dissertations and‌​‌ habilitation theses

• 63 thesis​​H.Hamza Amara.​​​‌ Evaluation and Protection of‌ Compressed Network-on-Chip Communications Against‌​‌ Hardware Trojan Attacks.​​Université de RennesDecember​​​‌ 2025HALback to‌ text
• 64 thesisG.‌​‌Gaëtan Barret. Energy​​ estimation of cloud-native applications​​​‌.Université de rennes‌December 2025HALback‌​‌ to text
• 65 thesis​​S.Sami Ben Ali​​​‌. Entraînement à basse‌ précision pour les accélérateurs‌​‌ d’apprentissage profond.Université​​ de RennesApril 2025​​​‌HAL
• 66 thesisS.‌Sami Ben Ali.‌​‌ Low-Precision Accelerators for Efficient​​ Deep Learning Training.​​​‌Université de RennesApril‌ 2025HALback to‌​‌ text
• 67 thesisB.​​Benoît Coqueret. On​​​‌ the Complementarity of Software‌ and Side-Channel Attacks against‌​‌ Deep Learning Algorithms.​​Université de RennesDecember​​​‌ 2025HALback to‌ text
• 68 thesisW.‌​‌Wilfread Guillemé. Fault-Tolerant​​ Hardware Architectures for Artificial​​​‌ Intelligence Algorithms.Université‌ de RennesDecember 2025‌​‌HALback to text​​
• 69 thesisS.Seungah​​​‌ LEE. Efficient designs‌ of on-board heterogeneous embedded‌​‌ systems for space applications​​.Université de Rennes​​​‌January 2025HALback‌ to text
• 70 thesis‌​‌L. D.Léo De​​ La Fuente. Energy​​​‌ optimization in near-memory computing‌ through local instruction generation‌​‌.Université de Rennes​​May 2025HALback​​​‌ to text
• 71 thesis‌A.Amélie Marotta.‌​‌ Effects of synchronous clock​​ glitch on the security​​​‌ of integrated circuits.‌Université de Rennes; RENNES‌​‌June 2025HALback​​ to text
• 72 thesis​​​‌B.Baptiste Rossigneux.‌ Sparsity in neural networks‌​‌ : the trade-off between​​ operation count and complexity​​​‌ for embedded systems.‌Université de RennesOctober‌​‌ 2025HALback to​​ text

Reports & preprints​​​‌

• 73 miscR.Robin‌ Boëzennec, F.Fernando‌​‌ Fernandes dos Santos,​​ B.Brice Goglin,​​​‌ A.Angeliki Kritikakou,‌ G.Guillaume Pallez,‌​‌ E.Erven Rohou,​​ O.Olivier Sentieys and​​​‌ M.Marcello Traiola.‌ Increasing the Lifetime of‌​‌ HPC Machines: Issues, Implications,​​ and Open Challenges.​​​‌2025HAL
• 74 misc‌G.Guillaume Didier,‌​‌ T.Thomas Rokicki and​​ A.Augustin Lucas.​​​‌ Flush-based Cache Attacks on‌ Modern / Multi-Socket x86‌​‌ Systems.December 2025​​HAL
• 75 miscE.-M.​​​‌El-Mehdi El Arar,‌ S.-I.Silviu-Ioan Filip,‌​‌ T.Theo Mary and​​ E.Elisa Riccietti.​​​‌ Mixed precision accumulation for‌ neural network inference guided‌​‌ by componentwise forward error​​ analysis.2025HAL​​​‌back to text
• 76‌ miscV.Victor Levallois‌​‌, Y.Yoshihiro Shibuya​​, B.Bertrand Le​​​‌ Gal, R.Rob‌ Patro, P.Pierre‌​‌ Peterlongo and G. E.​​Giulio Ermanno Pibiri.​​​‌ Kaminari: a resource-frugal index‌ for approximate colored k‌​‌ -mer queries.May​​ 2025HALDOI

Other​​​‌ scientific publications

• 77 inproceedings‌T.Thomas Feuilletin,‌​‌ D.Dylan Leothaud,​​​‌ J.-M.Jean-Michel Gorius,​ S.Steven Derrien and​‌ S.Simon Rokicki.​​ Speculative High-Level Synthesis of​​​‌ RISC-V Processors.RISC-V​ summit Europe 2025Paris,​‌ France2025, 1-1​​HAL
• 78 inproceedingsD.​​​‌Dylan Leothaud, J.-M.​Jean-Michel Gorius, S.​‌Simon Rokicki and S.​​Steven Derrien. Optimizing​​​‌ Recovery Logic in Speculative​ High-Level Synthesis.DAC​‌ 2025 - Design Automation​​ ConferenceSan francisco, United​​​‌ StatesJune 2025HAL​
• 79 inproceedingsL.Lucas​‌ Roquet, F.Fernando​​ Fernandes dos Santos,​​​‌ M.Maria Kastriotou and​ A.Angeliki Kritikakou.​‌ Strategic Input Selection for​​ Deep Neural Networks Reliability​​​‌ Evaluation.NSREC 2025​ - IEEE Nuclear &​‌ Space Radiation Effects Conference​​Nashville (Tennessee), United States​​​‌2025HAL