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Bibliography

Major publications by the team in recent years
  • 1F. Bodin, T. Kisuki, P. M. W. Knijnenburg, M. F. P. O'Boyle, E. Rohou.

    Iterative Compilation in a Non-Linear Optimisation Space, in: Workshop on Profile and Feedback-Directed Compilation (FDO-1), in conjunction with PACT '98, October 1998.
  • 2N. Hallou, E. Rohou, P. Clauss, A. Ketterlin.

    Dynamic Re-Vectorization of Binary Code, in: SAMOS, July 2015.

    https://hal.inria.fr/hal-01155207
  • 3D. Hardy, I. Puaut.

    Static probabilistic Worst Case Execution Time Estimation for architectures with Faulty Instruction Caches, in: 21st International Conference on Real-Time Networks and Systems, Sophia Antipolis, France, October 2013. [ DOI : 10.1145/2516821.2516842 ]

    https://hal.inria.fr/hal-00862604
  • 4D. Hardy, I. Sideris, N. Ladas, Y. Sazeides.

    The performance vulnerability of architectural and non-architectural arrays to permanent faults, in: MICRO 45, Vancouver, Canada, December 2012.

    https://hal.inria.fr/hal-00747488
  • 5S. Kalathingal, S. Collange, B. Swamy, A. Seznec.

    DITVA: Dynamic Inter-Thread Vectorization Architecture, in: Journal of Parallel and Distributed Computing, October 2018, pp. 1-32. [ DOI : 10.1016/j.jpdc.2017.11.006 ]

    https://hal.archives-ouvertes.fr/hal-01655904
  • 6P. Michaud.

    Best-Offset Hardware Prefetching, in: International Symposium on High-Performance Computer Architecture, Barcelona, Spain, March 2016. [ DOI : 10.1109/HPCA.2016.7446087 ]

    https://hal.inria.fr/hal-01254863
  • 7P. Michaud, A. Mondelli, A. Seznec.

    Revisiting Clustered Microarchitecture for Future Superscalar Cores: A Case for Wide Issue Clusters, in: ACM Transactions on Architecture and Code Optimization (TACO), August 2015, vol. 13, no 3, 22 p. [ DOI : 10.1145/2800787 ]

    https://hal.inria.fr/hal-01193178
  • 8A. Perais, A. Seznec.

    EOLE: Paving the Way for an Effective Implementation of Value Prediction, in: International Symposium on Computer Architecture, Minneapolis, MN, United States, ACM/IEEE, June 2014, vol. 42, pp. 481-492. [ DOI : 10.1109/ISCA.2014.6853205 ]

    https://hal.inria.fr/hal-01088130
  • 9A. Perais, A. Seznec.

    Practical data value speculation for future high-end processors, in: International Symposium on High Performance Computer Architecture, Orlando, FL, United States, IEEE, February 2014, pp. 428-439. [ DOI : 10.1109/HPCA.2014.6835952 ]

    https://hal.inria.fr/hal-01088116
  • 10E. Rohou, B. Narasimha Swamy, A. Seznec.

    Branch Prediction and the Performance of Interpreters - Don't Trust Folklore, in: International Symposium on Code Generation and Optimization, Burlingame, United States, February 2015.

    https://hal.inria.fr/hal-01100647
  • 11S. Sardashti, A. Seznec, D. A. Wood.

    Skewed Compressed Caches, in: 47th Annual IEEE/ACM International Symposium on Microarchitecture, 2014, Minneapolis, United States, December 2014.

    https://hal.inria.fr/hal-01088050
  • 12S. Sardashti, A. Seznec, D. A. Wood.

    Yet Another Compressed Cache: a Low Cost Yet Effective Compressed Cache, in: ACM Transactions on Architecture and Code Optimization, September 2016, 25 p.

    https://hal.inria.fr/hal-01354248
  • 13A. Seznec, P. Michaud.

    A case for (partially)-tagged geometric history length branch prediction, in: Journal of Instruction Level Parallelism, February 2006.

    http://www.jilp.org/vol8
  • 14D. D. C. Teixeira, S. Collange, F. M. Quintão Pereira.

    Fusion of calling sites, in: International Symposium on Computer Architecture and High-Performance Computing (SBAC-PAD), Florianópolis, Santa Catarina, Brazil, October 2015. [ DOI : 10.1109/SBAC-PAD.2015.16 ]

    https://hal.archives-ouvertes.fr/hal-01410221
Publications of the year

Doctoral Dissertations and Habilitation Theses

  • 15A. A. Anapparakkal.

    Performance Centric Dynamic Function Level Binary Transformation, Université de Rennes 1 [UR1], December 2019.

    https://hal.inria.fr/tel-02394383

Articles in International Peer-Reviewed Journals

  • 16L. Besnard, P. Pinto, I. Lasri, J. Bispo, E. Rohou, J. M. P. Cardoso.

    A framework for automatic and parameterizable memoization, in: SoftwareX, July 2019, vol. 10, 100322 p. [ DOI : 10.1016/j.softx.2019.100322 ]

    https://hal.inria.fr/hal-02305415
  • 17C. Lima, J. Cezar, G. Vieira Leobas, E. Rohou, F. M. Quintão Pereira.

    Guided just-in-time specialization, in: Science of Computer Programming, November 2019, vol. 185, 41 p. [ DOI : 10.1016/j.scico.2019.102318 ]

    https://hal.inria.fr/hal-02314442
  • 18V. A. Nguyen, D. Hardy, I. Puaut.

    Cache-conscious Off-Line Real-Time Scheduling for Multi-Core Platforms: Algorithms and Implementation, in: Real-Time Systems, 2019, pp. 1-37, forthcoming. [ DOI : 10.4230/LIPIcs.ECRTS.2017.14 ]

    https://hal.inria.fr/hal-02044110
  • 19S. Reder, F. Kempf, H. Bucher, J. Becker, P. Alefragis, N. S. Voros, S. Skalistis, S. Derrien, I. Puaut, O. Oey, T. Stripf, C. Ferdinand, C. David, P. Ulbig, D. Mueller, U. Durak.

    Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications, in: Journal of Aerospace Information Systems, November 2019, vol. 16, no 11, pp. 521-533. [ DOI : 10.2514/1.I010749 ]

    https://hal.archives-ouvertes.fr/hal-02383381
  • 20C. Silvano, G. Agosta, A. Bartolini, A. R. Beccari, L. Benini, L. Besnard, J. Bispo, R. Cmar, J. M. P. Cardoso, C. Cavazzoni, D. Cesarini, S. Cherubin, F. Ficarelli, D. Gadioli, M. Golasowski, A. Libri, J. Martinovič, G. Palermo, P. Pinto, E. Rohou, K. Slaninová, E. Vitali.

    The ANTAREX domain specific language for high performance computing, in: Microprocessors and Microsystems: Embedded Hardware Design (MICPRO), July 2019, vol. 68, pp. 58-73. [ DOI : 10.1016/j.micpro.2019.05.005 ]

    https://hal.inria.fr/hal-02189586
  • 21M. Yusuf, A. El-Mahdy, E. Rohou.

    Runtime On-Stack Parallelization of Dependence-Free For-Loops in Binary Programs, in: IEEE Letters of the Computer Society, March 2019, vol. 2, no 1, pp. 1-4. [ DOI : 10.1109/LOCS.2019.2896559 ]

    https://hal.inria.fr/hal-02061340
  • 22M. Yusuf, A. El-Mahdy, E. Rohou.

    Towards Automatic Binary Runtime Loop De-Parallelization using On-Stack Replacement, in: Information Processing Letters, May 2019, vol. 145, pp. 53-57. [ DOI : 10.1016/j.ipl.2019.01.009 ]

    https://hal.inria.fr/hal-02002812

International Conferences with Proceedings

  • 23N. Charmchi, C. Collange, A. Seznec.

    Compressed cache layout aware prefetching, in: SBAC-PAD 2019 - International Symposium on Computer Architecture and High Performance Computing, Campo Grande, MS, Brazil, October 2019, pp. 1-4.

    https://hal.inria.fr/hal-02316773
  • 24M. Dardaillon, S. Skalistis, I. Puaut, S. Derrien.

    Reconciling Compiler Optimizations and WCET Estimation Using Iterative Compilation, in: RTSS 2019 - 40th IEEE Real-Time Systems Symposium, Hong Kong, China, IEEE, December 2019, pp. 1-13.

    https://hal.archives-ouvertes.fr/hal-02286164
  • 25K. Kalaitzidis, A. Seznec.

    Value Speculation through Equality Prediction, in: ICCD 2019 - 37th IEEE International Conference on Computer Design, Abu Dhabi, United Arab Emirates, IEEE, November 2019, pp. 1-4.

    https://hal.archives-ouvertes.fr/hal-02383480
  • 26R. Mancuso, H. Yun, I. Puaut.

    Impact of DM-LRU on WCET: A Static Analysis Approach, in: ECRTS 2019 - 31st Euromicro Conference on Real-Time Systems, Stuttgart, Germany, July 2019, pp. 1-25. [ DOI : 10.4230/LIPIcs.ECRTS.2019.17 ]

    https://hal.archives-ouvertes.fr/hal-02190255
  • 27S. Rokicki, E. Rohou, S. Derrien.

    Aggressive Memory Speculation in HW/SW Co-Designed Machines, in: DATE 2019 - 22nd IEEE/ACM Design, Automation and Test in Europe, Florence, Italy, IEEE, March 2019, pp. 332-335. [ DOI : 10.23919/DATE.2019.8715010 ]

    https://hal.archives-ouvertes.fr/hal-01941876
  • 29M. Schoeberl, B. Rouxel, I. Puaut.

    A Time-predictable Branch Predictor, in: SAC 2019 - 34th ACM/SIGAPP Symposium on Applied Computing, Limassol, Cyprus, April 2019, pp. 1-10. [ DOI : 10.1145/3297280.3297337 ]

    https://hal.inria.fr/hal-01976187
  • 30C. Silvano, G. Agosta, A. Bartolini, A. R. Beccari, L. Benini, L. Besnard, J. Bispo, R. Cmar, J. M. P. Cardoso, C. Cavazzoni, D. Cesarini, S. Cherubin, F. Ficarelli, D. Gadioli, M. Golasowski, I. Lasri, A. Libri, J. Martinovič, G. Palermo, P. Pinto, E. Rohou, N. Sanna, K. Slaninová, E. Vitali.

    Adaptive Optimization and Enforcement of Extra-Functional Properties in High Performance Computing: The ANTAREX Project, in: PDP 2019 - 27th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, Pavia, Italy, IEEE, February 2019, pp. 116-123. [ DOI : 10.1109/EMPDP.2019.8671584 ]

    https://hal.inria.fr/hal-02197811
  • 31M. Y. Siraichi, V. F. d. Santos, C. Collange, F. M. Quintão Pereira.

    Qubit allocation as a combination of subgraph isomorphism and token swapping, in: OOPSLA, Athens, Greece, October 2019, vol. 3, pp. 1-29. [ DOI : 10.1145/3360546 ]

    https://hal.inria.fr/hal-02316820
  • 32S. Skalistis, A. Kritikakou.

    Timely Fine-grained Interference-sensitive Run-time Adaptation of Time-triggered Schedules, in: RTSS 2019 - 40th IEEE Real-Time Systems Symposium, Hong Kong, China, IEEE, December 2019, pp. 1-13.

    https://hal.archives-ouvertes.fr/hal-02316392

Conferences without Proceedings

  • 33N. Charmchi, C. Collange.

    Toward compression-aware prefetching, in: COMPAS 2019 - Conférence d'informatique en Parallélisme, Architecture et Système, Anglet, France, June 2019, pp. 1-9.

    https://hal.inria.fr/hal-02351461
  • 34C. Collange.

    Ordinateurs quantiques : ouvrons la boîte, in: COMPAS 2019 - Conférence d'informatique en Parallélisme, Architecture et Système, Anglet, France, June 2019, pp. 1-9.

    https://hal.inria.fr/hal-02318324
  • 35A. Kouyoumdjian, C. Collange, E. Rohou.

    Vers la reconfiguration adaptative de GPU pour chaque application, in: COMPAS 2019 - Conférence d'informatique en Parallélisme, Architecture et Système, Anglet, France, June 2019, pp. 1-6.

    https://hal.inria.fr/hal-02390821
  • 36K. Le Bon, B. Hawkins, E. Rohou, G. Hiet, F. Tronel.

    Plateforme de protection de binaires configurable et dynamiquement adaptative, in: RESSI 2019 - Rendez-Vous de la Recherche et de l'Enseignement de la Sécurité des Systèmes d'Information, Erquy, France, May 2019, pp. 1-3.

    https://hal.inria.fr/hal-02385216

Internal Reports

  • 37P. Michaud.

    A Simple Model of Processor Temperature for Deterministic Turbo Clock Frequency, Inria Rennes, December 2019, no RR-9308.

    https://hal.inria.fr/hal-02391970

Other Publications

References in notes
  • 39G. Berthou, A. Carer, H.-P. Charles, S. Derrien, K. Marquet, I. Miro-Panades, D. Pala, I. Puaut, F. Rastello, T. Risset, E. Rohou, G. Salagnac, O. Sentieys, B. Yarahmadi.

    The Inria ZEP project: NVRAM and Harvesting for Zero Power Computations, March 2018, 1 p, NVMW 2018 - 10th Annual Non-Volatile Memories Workshop, Poster.

    https://hal.inria.fr/hal-01941766
  • 40A. Cohen, E. Rohou.

    Processor Virtualization and Split Compilation for Heterogeneous Multicore Embedded Systems, in: DAC, June 2010, pp. 102–107.
  • 41M. Hataba, A. El-Mahdy, E. Rohou.

    OJIT: A Novel Obfuscation Approach Using Standard Just-In-Time Compiler Transformations, in: International Workshop on Dynamic Compilation Everywhere, January 2015.
  • 42S. Kalathingal, S. Collange, B. Narasimha Swamy, A. Seznec.

    Dynamic Inter-Thread Vectorization Architecture: extracting DLP from TLP, in: International Symposium on Computer Architecture and High-Performance Computing (SBAC-PAD), Los Angeles, United States, October 2016.

    https://hal.inria.fr/hal-01356202
  • 43R. Kumar, D. M. Tullsen, N. P. Jouppi, P. Ranganathan.

    Heterogeneous chip multiprocessors, in: IEEE Computer, nov. 2005, vol. 38, no 11, pp. 32–38.
  • 44P. Michaud, A. Seznec.

    Pushing the branch predictability limits with the multi-poTAGE+SC predictor : Champion in the unlimited category, in: 4th JILP Workshop on Computer Architecture Competitions (JWAC-4): Championship Branch Prediction (CBP-4), Minneapolis, United States, June 2014.

    https://hal.archives-ouvertes.fr/hal-01087719
  • 45R. Omar, A. El-Mahdy, E. Rohou.

    Arbitrary control-flow embedding into multiple threads for obfuscation: a preliminary complexity and performance analysis, in: Proceedings of the 2nd international workshop on Security in cloud computing, ACM, 2014, pp. 51–58.
  • 46E. Riou, E. Rohou, P. Clauss, N. Hallou, A. Ketterlin.

    PADRONE: a Platform for Online Profiling, Analysis, and Optimization, in: Dynamic Compilation Everywhere, Vienna, Austria, January 2014.
  • 47A. Sembrant, T. Carlson, E. Hagersten, D. Black-Shaffer, A. Perais, A. Seznec, P. Michaud.

    Long Term Parking (LTP): Criticality-aware Resource Allocation in OOO Processors, in: International Symposium on Microarchitecture, Micro 2015, Honolulu, United States, Proceeding of the International Symposium on Microarchitecture, Micro 2015, ACM, December 2015.

    https://hal.inria.fr/hal-01225019
  • 48A. Seznec, J. San Miguel, J. Albericio.

    The Inner Most Loop Iteration counter: a new dimension in branch history , in: 48th International Symposium On Microarchitecture, Honolulu, United States, ACM, December 2015, 11 p.

    https://hal.inria.fr/hal-01208347
  • 49A. Seznec, N. Sendrier.

    HAVEGE: A user-level software heuristic for generating empirically strong random numbers, in: ACM Transactions on Modeling and Computer Simulation (TOMACS), 2003, vol. 13, no 4, pp. 334–346.
  • 50A. Seznec.

    TAGE-SC-L Branch Predictors: Champion in 32Kbits and 256 Kbits category, in: JILP - Championship Branch Prediction, Minneapolis, United States, June 2014.

    https://hal.inria.fr/hal-01086920


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